Lines Matching refs:emc_readl
500 value = emc_readl(emc, EMC_DBG); in tegra210_emc_r21021_periodic_compensation()
501 emc_cfg_o = emc_readl(emc, EMC_CFG); in tegra210_emc_r21021_periodic_compensation()
525 emc_cfg_update = value = emc_readl(emc, EMC_CFG_UPDATE); in tegra210_emc_r21021_periodic_compensation()
630 value = emc_readl(emc, EMC_FBIO_CFG5) & EMC_FBIO_CFG5_DRAM_TYPE_MASK; in tegra210_emc_r21021_set_clock()
648 emc_readl(emc, EMC_CFG); in tegra210_emc_r21021_set_clock()
649 emc_readl(emc, EMC_AUTO_CAL_CONFIG); in tegra210_emc_r21021_set_clock()
661 emc_dbg = emc_readl(emc, EMC_DBG); in tegra210_emc_r21021_set_clock()
662 emc_pin = emc_readl(emc, EMC_PIN); in tegra210_emc_r21021_set_clock()
663 emc_cfg_pipe_clk = emc_readl(emc, EMC_CFG_PIPE_CLK); in tegra210_emc_r21021_set_clock()
696 value = emc_readl(emc, EMC_CFG_DIG_DLL); in tegra210_emc_r21021_set_clock()
715 emc_readl(emc, EMC_AUTO_CAL_CONFIG); /* Flush write. */ in tegra210_emc_r21021_set_clock()
1642 value = emc_readl(emc, EMC_CFG_DIG_DLL); in tegra210_emc_r21021_set_clock()
1754 value = emc_readl(emc, EMC_CFG_DIG_DLL); in tegra210_emc_r21021_set_clock()