Lines Matching refs:ios
722 struct mmc_ios *ios, u32 rate) in sunxi_mmc_clk_set_phase() argument
740 if (ios->timing != MMC_TIMING_UHS_DDR50 && in sunxi_mmc_clk_set_phase()
741 ios->timing != MMC_TIMING_MMC_DDR52) { in sunxi_mmc_clk_set_phase()
743 } else if (ios->bus_width == MMC_BUS_WIDTH_8) { in sunxi_mmc_clk_set_phase()
760 struct mmc_ios *ios) in sunxi_mmc_clk_set_rate() argument
764 u32 rval, clock = ios->clock, div = 1; in sunxi_mmc_clk_set_rate()
774 if (!ios->clock) in sunxi_mmc_clk_set_rate()
786 if (ios->timing == MMC_TIMING_MMC_DDR52 && in sunxi_mmc_clk_set_rate()
788 ios->bus_width == MMC_BUS_WIDTH_8)) { in sunxi_mmc_clk_set_rate()
842 ret = sunxi_mmc_clk_set_phase(host, ios, rate); in sunxi_mmc_clk_set_rate()
884 static void sunxi_mmc_set_clk(struct sunxi_mmc_host *host, struct mmc_ios *ios) in sunxi_mmc_set_clk() argument
890 if (ios->timing == MMC_TIMING_UHS_DDR50 || in sunxi_mmc_set_clk()
891 ios->timing == MMC_TIMING_MMC_DDR52) in sunxi_mmc_set_clk()
897 host->ferror = sunxi_mmc_clk_set_rate(host, ios); in sunxi_mmc_set_clk()
902 struct mmc_ios *ios) in sunxi_mmc_card_power() argument
906 switch (ios->power_mode) { in sunxi_mmc_card_power()
913 ios->vdd); in sunxi_mmc_card_power()
947 static void sunxi_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) in sunxi_mmc_set_ios() argument
951 sunxi_mmc_card_power(host, ios); in sunxi_mmc_set_ios()
952 sunxi_mmc_set_bus_width(host, ios->bus_width); in sunxi_mmc_set_ios()
953 sunxi_mmc_set_clk(host, ios); in sunxi_mmc_set_ios()
956 static int sunxi_mmc_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios) in sunxi_mmc_volt_switch() argument
962 ret = mmc_regulator_set_vqmmc(mmc, ios); in sunxi_mmc_volt_switch()
967 if (mmc->ios.signal_voltage == MMC_SIGNAL_VOLTAGE_330) in sunxi_mmc_volt_switch()
1506 sunxi_mmc_set_bus_width(host, mmc->ios.bus_width); in sunxi_mmc_runtime_resume()
1507 sunxi_mmc_set_clk(host, &mmc->ios); in sunxi_mmc_runtime_resume()