Lines Matching refs:outb
266 outb(E8390_NODMA + E8390_PAGE1 + E8390_STOP, ioaddr + E8390_CMD); in ne2k_pci_init_one()
268 outb(0xff, ioaddr + 0x0d); in ne2k_pci_init_one()
269 outb(E8390_NODMA + E8390_PAGE0, ioaddr + E8390_CMD); in ne2k_pci_init_one()
273 outb(reg0, ioaddr); in ne2k_pci_init_one()
275 outb(regd, ioaddr + 0x0d); in ne2k_pci_init_one()
296 outb(inb(ioaddr + NE_RESET), ioaddr + NE_RESET); in ne2k_pci_init_one()
309 outb(0xff, ioaddr + EN0_ISR); in ne2k_pci_init_one()
342 outb(program_seq[i].value, in ne2k_pci_init_one()
358 outb(0x49, ioaddr + EN0_DCFG); in ne2k_pci_init_one()
420 outb(0xC0 + E8390_NODMA, ioaddr + NE_CMD); /* Page 3 */ in set_realtek_fdx()
421 outb(0xC0, ioaddr + 0x01); /* Enable writes to CONFIG3 */ in set_realtek_fdx()
422 outb(0x40, ioaddr + 0x06); /* Enable full duplex */ in set_realtek_fdx()
423 outb(0x00, ioaddr + 0x01); /* Disable writes to CONFIG3 */ in set_realtek_fdx()
424 outb(E8390_PAGE0 + E8390_NODMA, ioaddr + NE_CMD); /* Page 0 */ in set_realtek_fdx()
432 outb(inb(ioaddr + 0x20) | 0x80, ioaddr + 0x20); in set_holtek_fdx()
479 outb(inb(NE_BASE + NE_RESET), NE_BASE + NE_RESET); in ne2k_pci_reset_8390()
491 outb(ENISR_RESET, NE_BASE + EN0_ISR); in ne2k_pci_reset_8390()
514 outb(E8390_NODMA + E8390_PAGE0 + E8390_START, nic_base + NE_CMD); in ne2k_pci_get_8390_hdr()
515 outb(sizeof(struct e8390_pkt_hdr), nic_base + EN0_RCNTLO); in ne2k_pci_get_8390_hdr()
516 outb(0, nic_base + EN0_RCNTHI); in ne2k_pci_get_8390_hdr()
517 outb(0, nic_base + EN0_RSARLO); /* On page boundary */ in ne2k_pci_get_8390_hdr()
518 outb(ring_page, nic_base + EN0_RSARHI); in ne2k_pci_get_8390_hdr()
519 outb(E8390_RREAD+E8390_START, nic_base + NE_CMD); in ne2k_pci_get_8390_hdr()
529 outb(ENISR_RDC, nic_base + EN0_ISR); in ne2k_pci_get_8390_hdr()
556 outb(E8390_NODMA + E8390_PAGE0 + E8390_START, nic_base + NE_CMD); in ne2k_pci_block_input()
557 outb(count & 0xff, nic_base + EN0_RCNTLO); in ne2k_pci_block_input()
558 outb(count >> 8, nic_base + EN0_RCNTHI); in ne2k_pci_block_input()
559 outb(ring_offset & 0xff, nic_base + EN0_RSARLO); in ne2k_pci_block_input()
560 outb(ring_offset >> 8, nic_base + EN0_RSARHI); in ne2k_pci_block_input()
561 outb(E8390_RREAD + E8390_START, nic_base + NE_CMD); in ne2k_pci_block_input()
582 outb(ENISR_RDC, nic_base + EN0_ISR); in ne2k_pci_block_input()
611 outb(E8390_PAGE0+E8390_START+E8390_NODMA, nic_base + NE_CMD); in ne2k_pci_block_output()
619 outb(0x42, nic_base + EN0_RCNTLO); in ne2k_pci_block_output()
620 outb(0x00, nic_base + EN0_RCNTHI); in ne2k_pci_block_output()
621 outb(0x42, nic_base + EN0_RSARLO); in ne2k_pci_block_output()
622 outb(0x00, nic_base + EN0_RSARHI); in ne2k_pci_block_output()
623 outb(E8390_RREAD+E8390_START, nic_base + NE_CMD); in ne2k_pci_block_output()
625 outb(ENISR_RDC, nic_base + EN0_ISR); in ne2k_pci_block_output()
628 outb(count & 0xff, nic_base + EN0_RCNTLO); in ne2k_pci_block_output()
629 outb(count >> 8, nic_base + EN0_RCNTHI); in ne2k_pci_block_output()
630 outb(0x00, nic_base + EN0_RSARLO); in ne2k_pci_block_output()
631 outb(start_page, nic_base + EN0_RSARHI); in ne2k_pci_block_output()
632 outb(E8390_RWRITE+E8390_START, nic_base + NE_CMD); in ne2k_pci_block_output()
659 outb(ENISR_RDC, nic_base + EN0_ISR); in ne2k_pci_block_output()