Lines Matching refs:aenq
131 struct ena_com_aenq *aenq = &ena_dev->aenq; in ena_com_admin_init_aenq() local
135 ena_dev->aenq.q_depth = ENA_ASYNC_QUEUE_DEPTH; in ena_com_admin_init_aenq()
137 aenq->entries = dma_alloc_coherent(ena_dev->dmadev, size, in ena_com_admin_init_aenq()
138 &aenq->dma_addr, GFP_KERNEL); in ena_com_admin_init_aenq()
140 if (!aenq->entries) { in ena_com_admin_init_aenq()
145 aenq->head = aenq->q_depth; in ena_com_admin_init_aenq()
146 aenq->phase = 1; in ena_com_admin_init_aenq()
148 addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(aenq->dma_addr); in ena_com_admin_init_aenq()
149 addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(aenq->dma_addr); in ena_com_admin_init_aenq()
155 aenq_caps |= ena_dev->aenq.q_depth & ENA_REGS_AENQ_CAPS_AENQ_DEPTH_MASK; in ena_com_admin_init_aenq()
167 aenq->aenq_handlers = aenq_handlers; in ena_com_admin_init_aenq()
1542 u16 depth = ena_dev->aenq.q_depth; in ena_com_admin_aenq_enable()
1544 WARN(ena_dev->aenq.head != depth, "Invalid AENQ state\n"); in ena_com_admin_aenq_enable()
1566 if ((get_resp.u.aenq.supported_groups & groups_flag) != groups_flag) { in ena_com_set_aenq_config()
1569 get_resp.u.aenq.supported_groups, groups_flag); in ena_com_set_aenq_config()
1579 cmd.u.aenq.enabled_groups = groups_flag; in ena_com_set_aenq_config()
1687 struct ena_com_aenq *aenq = &ena_dev->aenq; in ena_com_admin_destroy() local
1704 size = ADMIN_AENQ_SIZE(aenq->q_depth); in ena_com_admin_destroy()
1705 if (ena_dev->aenq.entries) in ena_com_admin_destroy()
1706 dma_free_coherent(ena_dev->dmadev, size, aenq->entries, in ena_com_admin_destroy()
1707 aenq->dma_addr); in ena_com_admin_destroy()
1708 aenq->entries = NULL; in ena_com_admin_destroy()
2007 memcpy(&get_feat_ctx->aenq, &get_resp.u.aenq, in ena_com_get_dev_attr_feat()
2008 sizeof(get_resp.u.aenq)); in ena_com_get_dev_attr_feat()
2055 struct ena_aenq_handlers *aenq_handlers = ena_dev->aenq.aenq_handlers; in ena_com_get_specific_aenq_cb()
2071 struct ena_com_aenq *aenq = &ena_dev->aenq; in ena_com_aenq_intr_handler() local
2077 masked_head = aenq->head & (aenq->q_depth - 1); in ena_com_aenq_intr_handler()
2078 phase = aenq->phase; in ena_com_aenq_intr_handler()
2079 aenq_e = &aenq->entries[masked_head]; /* Get first entry */ in ena_com_aenq_intr_handler()
2106 if (unlikely(masked_head == aenq->q_depth)) { in ena_com_aenq_intr_handler()
2110 aenq_e = &aenq->entries[masked_head]; in ena_com_aenq_intr_handler()
2114 aenq->head += processed; in ena_com_aenq_intr_handler()
2115 aenq->phase = phase; in ena_com_aenq_intr_handler()
2123 writel_relaxed((u32)aenq->head, in ena_com_aenq_intr_handler()