Lines Matching refs:oct
29 int lio_cn6xxx_soft_reset(struct octeon_device *oct) in lio_cn6xxx_soft_reset() argument
31 octeon_write_csr64(oct, CN6XXX_WIN_WR_MASK_REG, 0xFF); in lio_cn6xxx_soft_reset()
33 dev_dbg(&oct->pci_dev->dev, "BIST enabled for soft reset\n"); in lio_cn6xxx_soft_reset()
35 lio_pci_writeq(oct, 1, CN6XXX_CIU_SOFT_BIST); in lio_cn6xxx_soft_reset()
36 octeon_write_csr64(oct, CN6XXX_SLI_SCRATCH1, 0x1234ULL); in lio_cn6xxx_soft_reset()
38 lio_pci_readq(oct, CN6XXX_CIU_SOFT_RST); in lio_cn6xxx_soft_reset()
39 lio_pci_writeq(oct, 1, CN6XXX_CIU_SOFT_RST); in lio_cn6xxx_soft_reset()
44 if (octeon_read_csr64(oct, CN6XXX_SLI_SCRATCH1)) { in lio_cn6xxx_soft_reset()
45 dev_err(&oct->pci_dev->dev, "Soft reset failed\n"); in lio_cn6xxx_soft_reset()
49 dev_dbg(&oct->pci_dev->dev, "Reset completed\n"); in lio_cn6xxx_soft_reset()
50 octeon_write_csr64(oct, CN6XXX_WIN_WR_MASK_REG, 0xFF); in lio_cn6xxx_soft_reset()
55 void lio_cn6xxx_enable_error_reporting(struct octeon_device *oct) in lio_cn6xxx_enable_error_reporting() argument
59 pci_read_config_dword(oct->pci_dev, CN6XXX_PCIE_DEVCTL, &val); in lio_cn6xxx_enable_error_reporting()
61 dev_err(&oct->pci_dev->dev, "PCI-E Link error detected: 0x%08x\n", in lio_cn6xxx_enable_error_reporting()
67 dev_dbg(&oct->pci_dev->dev, "Enabling PCI-E error reporting..\n"); in lio_cn6xxx_enable_error_reporting()
68 pci_write_config_dword(oct->pci_dev, CN6XXX_PCIE_DEVCTL, val); in lio_cn6xxx_enable_error_reporting()
71 void lio_cn6xxx_setup_pcie_mps(struct octeon_device *oct, in lio_cn6xxx_setup_pcie_mps() argument
78 pci_read_config_dword(oct->pci_dev, CN6XXX_PCIE_DEVCTL, &val); in lio_cn6xxx_setup_pcie_mps()
85 pci_write_config_dword(oct->pci_dev, CN6XXX_PCIE_DEVCTL, val); in lio_cn6xxx_setup_pcie_mps()
89 r64 = lio_pci_readq(oct, CN6XXX_DPI_SLI_PRTX_CFG(oct->pcie_port)); in lio_cn6xxx_setup_pcie_mps()
91 lio_pci_writeq(oct, r64, CN6XXX_DPI_SLI_PRTX_CFG(oct->pcie_port)); in lio_cn6xxx_setup_pcie_mps()
94 void lio_cn6xxx_setup_pcie_mrrs(struct octeon_device *oct, in lio_cn6xxx_setup_pcie_mrrs() argument
101 pci_read_config_dword(oct->pci_dev, CN6XXX_PCIE_DEVCTL, &val); in lio_cn6xxx_setup_pcie_mrrs()
108 pci_write_config_dword(oct->pci_dev, CN6XXX_PCIE_DEVCTL, val); in lio_cn6xxx_setup_pcie_mrrs()
112 r64 = octeon_read_csr64(oct, CN6XXX_SLI_S2M_PORTX_CTL(oct->pcie_port)); in lio_cn6xxx_setup_pcie_mrrs()
114 octeon_write_csr64(oct, CN6XXX_SLI_S2M_PORTX_CTL(oct->pcie_port), r64); in lio_cn6xxx_setup_pcie_mrrs()
117 r64 = lio_pci_readq(oct, CN6XXX_DPI_SLI_PRTX_CFG(oct->pcie_port)); in lio_cn6xxx_setup_pcie_mrrs()
119 lio_pci_writeq(oct, r64, CN6XXX_DPI_SLI_PRTX_CFG(oct->pcie_port)); in lio_cn6xxx_setup_pcie_mrrs()
122 u32 lio_cn6xxx_coprocessor_clock(struct octeon_device *oct) in lio_cn6xxx_coprocessor_clock() argument
127 return ((lio_pci_readq(oct, CN6XXX_MIO_RST_BOOT) >> 24) & 0x3f) * 50; in lio_cn6xxx_coprocessor_clock()
130 u32 lio_cn6xxx_get_oq_ticks(struct octeon_device *oct, in lio_cn6xxx_get_oq_ticks() argument
134 u32 oqticks_per_us = lio_cn6xxx_coprocessor_clock(oct); in lio_cn6xxx_get_oq_ticks()
155 void lio_cn6xxx_setup_global_input_regs(struct octeon_device *oct) in lio_cn6xxx_setup_global_input_regs() argument
158 octeon_write_csr(oct, CN6XXX_SLI_PKT_INPUT_CONTROL, in lio_cn6xxx_setup_global_input_regs()
162 octeon_write_csr64(oct, CN6XXX_SLI_PKT_INSTR_RD_SIZE, in lio_cn6xxx_setup_global_input_regs()
166 octeon_write_csr64(oct, CN6XXX_SLI_IN_PCIE_PORT, in lio_cn6xxx_setup_global_input_regs()
167 (oct->pcie_port * 0x5555555555555555ULL)); in lio_cn6xxx_setup_global_input_regs()
170 static void lio_cn66xx_setup_pkt_ctl_regs(struct octeon_device *oct) in lio_cn66xx_setup_pkt_ctl_regs() argument
174 struct octeon_cn6xxx *cn6xxx = (struct octeon_cn6xxx *)oct->chip; in lio_cn66xx_setup_pkt_ctl_regs()
176 pktctl = octeon_read_csr64(oct, CN6XXX_SLI_PKT_CTL); in lio_cn66xx_setup_pkt_ctl_regs()
190 octeon_write_csr64(oct, CN6XXX_SLI_PKT_CTL, pktctl); in lio_cn66xx_setup_pkt_ctl_regs()
193 void lio_cn6xxx_setup_global_output_regs(struct octeon_device *oct) in lio_cn6xxx_setup_global_output_regs() argument
196 struct octeon_cn6xxx *cn6xxx = (struct octeon_cn6xxx *)oct->chip; in lio_cn6xxx_setup_global_output_regs()
199 octeon_write_csr64(oct, CN6XXX_SLI_PKT_PCIE_PORT64, in lio_cn6xxx_setup_global_output_regs()
200 (oct->pcie_port * 0x5555555555555555ULL)); in lio_cn6xxx_setup_global_output_regs()
203 octeon_write_csr64(oct, CN6XXX_SLI_OQ_WMARK, 32); in lio_cn6xxx_setup_global_output_regs()
206 octeon_write_csr64(oct, CN6XXX_SLI_OQ_WMARK, 0); in lio_cn6xxx_setup_global_output_regs()
210 octeon_write_csr(oct, CN6XXX_SLI_PKT_OUT_BMODE, 0); in lio_cn6xxx_setup_global_output_regs()
215 octeon_write_csr(oct, CN6XXX_SLI_PKT_DPADDR, 0xFFFFFFFF); in lio_cn6xxx_setup_global_output_regs()
220 octeon_write_csr(oct, CN6XXX_SLI_PKT_SLIST_ROR, 0); in lio_cn6xxx_setup_global_output_regs()
221 octeon_write_csr(oct, CN6XXX_SLI_PKT_SLIST_NS, 0); in lio_cn6xxx_setup_global_output_regs()
225 octeon_write_csr64(oct, CN6XXX_SLI_PKT_SLIST_ES64, in lio_cn6xxx_setup_global_output_regs()
228 octeon_write_csr64(oct, CN6XXX_SLI_PKT_SLIST_ES64, 0ULL); in lio_cn6xxx_setup_global_output_regs()
232 octeon_write_csr(oct, CN6XXX_SLI_PKT_DATA_OUT_ROR, 0); in lio_cn6xxx_setup_global_output_regs()
233 octeon_write_csr(oct, CN6XXX_SLI_PKT_DATA_OUT_NS, 0); in lio_cn6xxx_setup_global_output_regs()
234 octeon_write_csr64(oct, CN6XXX_SLI_PKT_DATA_OUT_ES64, in lio_cn6xxx_setup_global_output_regs()
238 octeon_write_csr(oct, CN6XXX_SLI_OQ_INT_LEVEL_PKTS, in lio_cn6xxx_setup_global_output_regs()
241 lio_cn6xxx_get_oq_ticks(oct, (u32) in lio_cn6xxx_setup_global_output_regs()
244 octeon_write_csr(oct, CN6XXX_SLI_OQ_INT_LEVEL_TIME, time_threshold); in lio_cn6xxx_setup_global_output_regs()
247 static int lio_cn6xxx_setup_device_regs(struct octeon_device *oct) in lio_cn6xxx_setup_device_regs() argument
249 lio_cn6xxx_setup_pcie_mps(oct, PCIE_MPS_DEFAULT); in lio_cn6xxx_setup_device_regs()
250 lio_cn6xxx_setup_pcie_mrrs(oct, PCIE_MRRS_512B); in lio_cn6xxx_setup_device_regs()
251 lio_cn6xxx_enable_error_reporting(oct); in lio_cn6xxx_setup_device_regs()
253 lio_cn6xxx_setup_global_input_regs(oct); in lio_cn6xxx_setup_device_regs()
254 lio_cn66xx_setup_pkt_ctl_regs(oct); in lio_cn6xxx_setup_device_regs()
255 lio_cn6xxx_setup_global_output_regs(oct); in lio_cn6xxx_setup_device_regs()
260 octeon_write_csr64(oct, CN6XXX_SLI_WINDOW_CTL, 0x200000ULL); in lio_cn6xxx_setup_device_regs()
264 void lio_cn6xxx_setup_iq_regs(struct octeon_device *oct, u32 iq_no) in lio_cn6xxx_setup_iq_regs() argument
266 struct octeon_instr_queue *iq = oct->instr_queue[iq_no]; in lio_cn6xxx_setup_iq_regs()
268 octeon_write_csr64(oct, CN6XXX_SLI_IQ_PKT_INSTR_HDR64(iq_no), 0); in lio_cn6xxx_setup_iq_regs()
271 octeon_write_csr64(oct, CN6XXX_SLI_IQ_BASE_ADDR64(iq_no), in lio_cn6xxx_setup_iq_regs()
273 octeon_write_csr(oct, CN6XXX_SLI_IQ_SIZE(iq_no), iq->max_count); in lio_cn6xxx_setup_iq_regs()
278 iq->doorbell_reg = oct->mmio[0].hw_addr + CN6XXX_SLI_IQ_DOORBELL(iq_no); in lio_cn6xxx_setup_iq_regs()
279 iq->inst_cnt_reg = oct->mmio[0].hw_addr in lio_cn6xxx_setup_iq_regs()
281 dev_dbg(&oct->pci_dev->dev, "InstQ[%d]:dbell reg @ 0x%p instcnt_reg @ 0x%p\n", in lio_cn6xxx_setup_iq_regs()
290 static void lio_cn66xx_setup_iq_regs(struct octeon_device *oct, u32 iq_no) in lio_cn66xx_setup_iq_regs() argument
292 lio_cn6xxx_setup_iq_regs(oct, iq_no); in lio_cn66xx_setup_iq_regs()
297 octeon_write_csr64(oct, CN66XX_SLI_IQ_BP64(iq_no), in lio_cn66xx_setup_iq_regs()
301 void lio_cn6xxx_setup_oq_regs(struct octeon_device *oct, u32 oq_no) in lio_cn6xxx_setup_oq_regs() argument
304 struct octeon_droq *droq = oct->droq[oq_no]; in lio_cn6xxx_setup_oq_regs()
306 octeon_write_csr64(oct, CN6XXX_SLI_OQ_BASE_ADDR64(oq_no), in lio_cn6xxx_setup_oq_regs()
308 octeon_write_csr(oct, CN6XXX_SLI_OQ_SIZE(oq_no), droq->max_count); in lio_cn6xxx_setup_oq_regs()
310 octeon_write_csr(oct, CN6XXX_SLI_OQ_BUFF_INFO_SIZE(oq_no), in lio_cn6xxx_setup_oq_regs()
315 oct->mmio[0].hw_addr + CN6XXX_SLI_OQ_PKTS_SENT(oq_no); in lio_cn6xxx_setup_oq_regs()
317 oct->mmio[0].hw_addr + CN6XXX_SLI_OQ_PKTS_CREDIT(oq_no); in lio_cn6xxx_setup_oq_regs()
320 intr = octeon_read_csr(oct, CN6XXX_SLI_PKT_TIME_INT_ENB); in lio_cn6xxx_setup_oq_regs()
322 octeon_write_csr(oct, CN6XXX_SLI_PKT_TIME_INT_ENB, intr); in lio_cn6xxx_setup_oq_regs()
325 intr = octeon_read_csr(oct, CN6XXX_SLI_PKT_CNT_INT_ENB); in lio_cn6xxx_setup_oq_regs()
327 octeon_write_csr(oct, CN6XXX_SLI_PKT_CNT_INT_ENB, intr); in lio_cn6xxx_setup_oq_regs()
330 int lio_cn6xxx_enable_io_queues(struct octeon_device *oct) in lio_cn6xxx_enable_io_queues() argument
334 mask = octeon_read_csr(oct, CN6XXX_SLI_PKT_INSTR_SIZE); in lio_cn6xxx_enable_io_queues()
335 mask |= oct->io_qmask.iq64B; in lio_cn6xxx_enable_io_queues()
336 octeon_write_csr(oct, CN6XXX_SLI_PKT_INSTR_SIZE, mask); in lio_cn6xxx_enable_io_queues()
338 mask = octeon_read_csr(oct, CN6XXX_SLI_PKT_INSTR_ENB); in lio_cn6xxx_enable_io_queues()
339 mask |= oct->io_qmask.iq; in lio_cn6xxx_enable_io_queues()
340 octeon_write_csr(oct, CN6XXX_SLI_PKT_INSTR_ENB, mask); in lio_cn6xxx_enable_io_queues()
342 mask = octeon_read_csr(oct, CN6XXX_SLI_PKT_OUT_ENB); in lio_cn6xxx_enable_io_queues()
343 mask |= oct->io_qmask.oq; in lio_cn6xxx_enable_io_queues()
344 octeon_write_csr(oct, CN6XXX_SLI_PKT_OUT_ENB, mask); in lio_cn6xxx_enable_io_queues()
349 void lio_cn6xxx_disable_io_queues(struct octeon_device *oct) in lio_cn6xxx_disable_io_queues() argument
356 mask = octeon_read_csr(oct, CN6XXX_SLI_PKT_INSTR_ENB); in lio_cn6xxx_disable_io_queues()
357 mask ^= oct->io_qmask.iq; in lio_cn6xxx_disable_io_queues()
358 octeon_write_csr(oct, CN6XXX_SLI_PKT_INSTR_ENB, mask); in lio_cn6xxx_disable_io_queues()
361 mask = (u32)oct->io_qmask.iq; in lio_cn6xxx_disable_io_queues()
362 d32 = octeon_read_csr(oct, CN6XXX_SLI_PORT_IN_RST_IQ); in lio_cn6xxx_disable_io_queues()
364 d32 = octeon_read_csr(oct, CN6XXX_SLI_PORT_IN_RST_IQ); in lio_cn6xxx_disable_io_queues()
369 for (i = 0; i < MAX_OCTEON_INSTR_QUEUES(oct); i++) { in lio_cn6xxx_disable_io_queues()
370 if (!(oct->io_qmask.iq & BIT_ULL(i))) in lio_cn6xxx_disable_io_queues()
372 octeon_write_csr(oct, CN6XXX_SLI_IQ_DOORBELL(i), 0xFFFFFFFF); in lio_cn6xxx_disable_io_queues()
373 d32 = octeon_read_csr(oct, CN6XXX_SLI_IQ_DOORBELL(i)); in lio_cn6xxx_disable_io_queues()
377 mask = octeon_read_csr(oct, CN6XXX_SLI_PKT_OUT_ENB); in lio_cn6xxx_disable_io_queues()
378 mask ^= oct->io_qmask.oq; in lio_cn6xxx_disable_io_queues()
379 octeon_write_csr(oct, CN6XXX_SLI_PKT_OUT_ENB, mask); in lio_cn6xxx_disable_io_queues()
383 mask = (u32)oct->io_qmask.oq; in lio_cn6xxx_disable_io_queues()
384 d32 = octeon_read_csr(oct, CN6XXX_SLI_PORT_IN_RST_OQ); in lio_cn6xxx_disable_io_queues()
386 d32 = octeon_read_csr(oct, CN6XXX_SLI_PORT_IN_RST_OQ); in lio_cn6xxx_disable_io_queues()
392 for (i = 0; i < MAX_OCTEON_OUTPUT_QUEUES(oct); i++) { in lio_cn6xxx_disable_io_queues()
393 if (!(oct->io_qmask.oq & BIT_ULL(i))) in lio_cn6xxx_disable_io_queues()
395 octeon_write_csr(oct, CN6XXX_SLI_OQ_PKTS_CREDIT(i), 0xFFFFFFFF); in lio_cn6xxx_disable_io_queues()
396 d32 = octeon_read_csr(oct, CN6XXX_SLI_OQ_PKTS_CREDIT(i)); in lio_cn6xxx_disable_io_queues()
398 d32 = octeon_read_csr(oct, CN6XXX_SLI_OQ_PKTS_SENT(i)); in lio_cn6xxx_disable_io_queues()
399 octeon_write_csr(oct, CN6XXX_SLI_OQ_PKTS_SENT(i), d32); in lio_cn6xxx_disable_io_queues()
402 d32 = octeon_read_csr(oct, CN6XXX_SLI_PKT_CNT_INT); in lio_cn6xxx_disable_io_queues()
404 octeon_write_csr(oct, CN6XXX_SLI_PKT_CNT_INT, d32); in lio_cn6xxx_disable_io_queues()
406 d32 = octeon_read_csr(oct, CN6XXX_SLI_PKT_TIME_INT); in lio_cn6xxx_disable_io_queues()
408 octeon_write_csr(oct, CN6XXX_SLI_PKT_TIME_INT, d32); in lio_cn6xxx_disable_io_queues()
412 lio_cn6xxx_bar1_idx_setup(struct octeon_device *oct, in lio_cn6xxx_bar1_idx_setup() argument
420 bar1 = lio_pci_readq(oct, CN6XXX_BAR1_REG(idx, oct->pcie_port)); in lio_cn6xxx_bar1_idx_setup()
421 lio_pci_writeq(oct, (bar1 & 0xFFFFFFFEULL), in lio_cn6xxx_bar1_idx_setup()
422 CN6XXX_BAR1_REG(idx, oct->pcie_port)); in lio_cn6xxx_bar1_idx_setup()
423 bar1 = lio_pci_readq(oct, CN6XXX_BAR1_REG(idx, oct->pcie_port)); in lio_cn6xxx_bar1_idx_setup()
430 lio_pci_writeq(oct, (((core_addr >> 22) << 4) | PCI_BAR1_MASK), in lio_cn6xxx_bar1_idx_setup()
431 CN6XXX_BAR1_REG(idx, oct->pcie_port)); in lio_cn6xxx_bar1_idx_setup()
433 bar1 = lio_pci_readq(oct, CN6XXX_BAR1_REG(idx, oct->pcie_port)); in lio_cn6xxx_bar1_idx_setup()
436 void lio_cn6xxx_bar1_idx_write(struct octeon_device *oct, in lio_cn6xxx_bar1_idx_write() argument
440 lio_pci_writeq(oct, mask, CN6XXX_BAR1_REG(idx, oct->pcie_port)); in lio_cn6xxx_bar1_idx_write()
443 u32 lio_cn6xxx_bar1_idx_read(struct octeon_device *oct, u32 idx) in lio_cn6xxx_bar1_idx_read() argument
445 return (u32)lio_pci_readq(oct, CN6XXX_BAR1_REG(idx, oct->pcie_port)); in lio_cn6xxx_bar1_idx_read()
470 void lio_cn6xxx_enable_interrupt(struct octeon_device *oct, in lio_cn6xxx_enable_interrupt() argument
473 struct octeon_cn6xxx *cn6xxx = (struct octeon_cn6xxx *)oct->chip; in lio_cn6xxx_enable_interrupt()
480 void lio_cn6xxx_disable_interrupt(struct octeon_device *oct, in lio_cn6xxx_disable_interrupt() argument
483 struct octeon_cn6xxx *cn6xxx = (struct octeon_cn6xxx *)oct->chip; in lio_cn6xxx_disable_interrupt()
489 static void lio_cn6xxx_get_pcie_qlmport(struct octeon_device *oct) in lio_cn6xxx_get_pcie_qlmport() argument
494 oct->pcie_port = octeon_read_csr(oct, CN6XXX_SLI_MAC_NUMBER) & 0xff; in lio_cn6xxx_get_pcie_qlmport()
496 dev_dbg(&oct->pci_dev->dev, "Using PCIE Port %d\n", oct->pcie_port); in lio_cn6xxx_get_pcie_qlmport()
500 lio_cn6xxx_process_pcie_error_intr(struct octeon_device *oct, u64 intr64) in lio_cn6xxx_process_pcie_error_intr() argument
502 dev_err(&oct->pci_dev->dev, "Error Intr: 0x%016llx\n", in lio_cn6xxx_process_pcie_error_intr()
506 static int lio_cn6xxx_process_droq_intr_regs(struct octeon_device *oct) in lio_cn6xxx_process_droq_intr_regs() argument
513 droq_cnt_enb = octeon_read_csr(oct, CN6XXX_SLI_PKT_CNT_INT_ENB); in lio_cn6xxx_process_droq_intr_regs()
514 droq_cnt_mask = octeon_read_csr(oct, CN6XXX_SLI_PKT_CNT_INT); in lio_cn6xxx_process_droq_intr_regs()
517 droq_time_mask = octeon_read_csr(oct, CN6XXX_SLI_PKT_TIME_INT); in lio_cn6xxx_process_droq_intr_regs()
518 droq_int_enb = octeon_read_csr(oct, CN6XXX_SLI_PKT_TIME_INT_ENB); in lio_cn6xxx_process_droq_intr_regs()
521 droq_mask &= oct->io_qmask.oq; in lio_cn6xxx_process_droq_intr_regs()
523 oct->droq_intr = 0; in lio_cn6xxx_process_droq_intr_regs()
525 for (oq_no = 0; oq_no < MAX_OCTEON_OUTPUT_QUEUES(oct); oq_no++) { in lio_cn6xxx_process_droq_intr_regs()
529 droq = oct->droq[oq_no]; in lio_cn6xxx_process_droq_intr_regs()
532 oct->droq_intr |= BIT_ULL(oq_no); in lio_cn6xxx_process_droq_intr_regs()
538 (struct octeon_cn6xxx *)oct->chip; in lio_cn6xxx_process_droq_intr_regs()
544 value = octeon_read_csr(oct, reg); in lio_cn6xxx_process_droq_intr_regs()
546 octeon_write_csr(oct, reg, value); in lio_cn6xxx_process_droq_intr_regs()
548 value = octeon_read_csr(oct, reg); in lio_cn6xxx_process_droq_intr_regs()
550 octeon_write_csr(oct, reg, value); in lio_cn6xxx_process_droq_intr_regs()
557 droq_time_mask &= oct->io_qmask.oq; in lio_cn6xxx_process_droq_intr_regs()
558 droq_cnt_mask &= oct->io_qmask.oq; in lio_cn6xxx_process_droq_intr_regs()
562 octeon_write_csr(oct, CN6XXX_SLI_PKT_TIME_INT, droq_time_mask); in lio_cn6xxx_process_droq_intr_regs()
565 octeon_write_csr(oct, CN6XXX_SLI_PKT_CNT_INT, droq_cnt_mask); in lio_cn6xxx_process_droq_intr_regs()
572 struct octeon_device *oct = (struct octeon_device *)dev; in lio_cn6xxx_process_interrupt_regs() local
573 struct octeon_cn6xxx *cn6xxx = (struct octeon_cn6xxx *)oct->chip; in lio_cn6xxx_process_interrupt_regs()
585 oct->int_status = 0; in lio_cn6xxx_process_interrupt_regs()
588 lio_cn6xxx_process_pcie_error_intr(oct, intr64); in lio_cn6xxx_process_interrupt_regs()
591 lio_cn6xxx_process_droq_intr_regs(oct); in lio_cn6xxx_process_interrupt_regs()
592 oct->int_status |= OCT_DEV_INTR_PKT_DATA; in lio_cn6xxx_process_interrupt_regs()
596 oct->int_status |= OCT_DEV_INTR_DMA0_FORCE; in lio_cn6xxx_process_interrupt_regs()
599 oct->int_status |= OCT_DEV_INTR_DMA1_FORCE; in lio_cn6xxx_process_interrupt_regs()
607 void lio_cn6xxx_setup_reg_address(struct octeon_device *oct, in lio_cn6xxx_setup_reg_address() argument
611 u8 __iomem *bar0_pciaddr = oct->mmio[0].hw_addr; in lio_cn6xxx_setup_reg_address()
642 lio_cn6xxx_get_pcie_qlmport(oct); in lio_cn6xxx_setup_reg_address()
647 bar0_pciaddr + CN6XXX_SLI_INT_ENB64(oct->pcie_port); in lio_cn6xxx_setup_reg_address()
650 int lio_setup_cn66xx_octeon_device(struct octeon_device *oct) in lio_setup_cn66xx_octeon_device() argument
652 struct octeon_cn6xxx *cn6xxx = (struct octeon_cn6xxx *)oct->chip; in lio_setup_cn66xx_octeon_device()
654 if (octeon_map_pci_barx(oct, 0, 0)) in lio_setup_cn66xx_octeon_device()
657 if (octeon_map_pci_barx(oct, 1, MAX_BAR1_IOREMAP_SIZE)) { in lio_setup_cn66xx_octeon_device()
658 dev_err(&oct->pci_dev->dev, "%s CN66XX BAR1 map failed\n", in lio_setup_cn66xx_octeon_device()
660 octeon_unmap_pci_barx(oct, 0); in lio_setup_cn66xx_octeon_device()
666 oct->fn_list.setup_iq_regs = lio_cn66xx_setup_iq_regs; in lio_setup_cn66xx_octeon_device()
667 oct->fn_list.setup_oq_regs = lio_cn6xxx_setup_oq_regs; in lio_setup_cn66xx_octeon_device()
669 oct->fn_list.soft_reset = lio_cn6xxx_soft_reset; in lio_setup_cn66xx_octeon_device()
670 oct->fn_list.setup_device_regs = lio_cn6xxx_setup_device_regs; in lio_setup_cn66xx_octeon_device()
671 oct->fn_list.update_iq_read_idx = lio_cn6xxx_update_read_index; in lio_setup_cn66xx_octeon_device()
673 oct->fn_list.bar1_idx_setup = lio_cn6xxx_bar1_idx_setup; in lio_setup_cn66xx_octeon_device()
674 oct->fn_list.bar1_idx_write = lio_cn6xxx_bar1_idx_write; in lio_setup_cn66xx_octeon_device()
675 oct->fn_list.bar1_idx_read = lio_cn6xxx_bar1_idx_read; in lio_setup_cn66xx_octeon_device()
677 oct->fn_list.process_interrupt_regs = lio_cn6xxx_process_interrupt_regs; in lio_setup_cn66xx_octeon_device()
678 oct->fn_list.enable_interrupt = lio_cn6xxx_enable_interrupt; in lio_setup_cn66xx_octeon_device()
679 oct->fn_list.disable_interrupt = lio_cn6xxx_disable_interrupt; in lio_setup_cn66xx_octeon_device()
681 oct->fn_list.enable_io_queues = lio_cn6xxx_enable_io_queues; in lio_setup_cn66xx_octeon_device()
682 oct->fn_list.disable_io_queues = lio_cn6xxx_disable_io_queues; in lio_setup_cn66xx_octeon_device()
684 lio_cn6xxx_setup_reg_address(oct, oct->chip, &oct->reg_list); in lio_setup_cn66xx_octeon_device()
687 oct_get_config_info(oct, LIO_210SV); in lio_setup_cn66xx_octeon_device()
689 dev_err(&oct->pci_dev->dev, "%s No Config found for CN66XX\n", in lio_setup_cn66xx_octeon_device()
691 octeon_unmap_pci_barx(oct, 0); in lio_setup_cn66xx_octeon_device()
692 octeon_unmap_pci_barx(oct, 1); in lio_setup_cn66xx_octeon_device()
696 oct->coproc_clock_rate = 1000000ULL * lio_cn6xxx_coprocessor_clock(oct); in lio_setup_cn66xx_octeon_device()
701 int lio_validate_cn6xxx_config_info(struct octeon_device *oct, in lio_validate_cn6xxx_config_info() argument
705 dev_err(&oct->pci_dev->dev, "%s: Num IQ (%d) exceeds Max (%d)\n", in lio_validate_cn6xxx_config_info()
712 dev_err(&oct->pci_dev->dev, "%s: Num OQ (%d) exceeds Max (%d)\n", in lio_validate_cn6xxx_config_info()
720 dev_err(&oct->pci_dev->dev, "%s: Invalid instr type for IQ\n", in lio_validate_cn6xxx_config_info()
725 dev_err(&oct->pci_dev->dev, "%s: Invalid parameter for OQ\n", in lio_validate_cn6xxx_config_info()
731 dev_err(&oct->pci_dev->dev, "%s: No Time Interrupt for OQ\n", in lio_validate_cn6xxx_config_info()