Lines Matching refs:adap
128 struct adapter *adap = mc5->adapter; in init_mask_data_array() local
135 unsigned int server_base = t3_read_reg(adap, A_MC5_DB_SERVER_INDEX); in init_mask_data_array()
143 dbgi_wr_data3(adap, 0, 0, 0); in init_mask_data_array()
145 if (mc5_write(adap, data_array_base + (i << addr_shift), in init_mask_data_array()
150 dbgi_wr_data3(adap, 0xffffffff, 0xffffffff, 0xff); in init_mask_data_array()
153 t3_write_reg(adap, A_MC5_DB_DBGI_REQ_DATA0, in init_mask_data_array()
156 if (mc5_write(adap, mask_array_base + (i << addr_shift), in init_mask_data_array()
166 struct adapter *adap = mc5->adapter; in init_idt52100() local
168 t3_write_reg(adap, A_MC5_DB_RSP_LATENCY, in init_idt52100()
170 t3_write_reg(adap, A_MC5_DB_PART_ID_INDEX, 2); in init_idt52100()
176 t3_write_reg(adap, A_MC5_DB_POPEN_DATA_WR_CMD, IDT_CMD_WRITE); in init_idt52100()
177 t3_write_reg(adap, A_MC5_DB_POPEN_MASK_WR_CMD, IDT_CMD_WRITE); in init_idt52100()
178 t3_write_reg(adap, A_MC5_DB_AOPEN_SRCH_CMD, IDT_CMD_SEARCH); in init_idt52100()
179 t3_write_reg(adap, A_MC5_DB_AOPEN_LRN_CMD, IDT_CMD_LEARN); in init_idt52100()
180 t3_write_reg(adap, A_MC5_DB_SYN_SRCH_CMD, IDT_CMD_SEARCH | 0x6000); in init_idt52100()
181 t3_write_reg(adap, A_MC5_DB_SYN_LRN_CMD, IDT_CMD_LEARN); in init_idt52100()
182 t3_write_reg(adap, A_MC5_DB_ACK_SRCH_CMD, IDT_CMD_SEARCH); in init_idt52100()
183 t3_write_reg(adap, A_MC5_DB_ACK_LRN_CMD, IDT_CMD_LEARN); in init_idt52100()
184 t3_write_reg(adap, A_MC5_DB_ILOOKUP_CMD, IDT_CMD_SEARCH); in init_idt52100()
185 t3_write_reg(adap, A_MC5_DB_ELOOKUP_CMD, IDT_CMD_SEARCH | 0x7000); in init_idt52100()
186 t3_write_reg(adap, A_MC5_DB_DATA_WRITE_CMD, IDT_CMD_WRITE); in init_idt52100()
187 t3_write_reg(adap, A_MC5_DB_DATA_READ_CMD, IDT_CMD_READ); in init_idt52100()
190 t3_write_reg(adap, A_MC5_DB_DBGI_CONFIG, DBGI_MODE_IDT52100); in init_idt52100()
193 dbgi_wr_data3(adap, IDT_LAR_MODE144, 0, 0); in init_idt52100()
194 if (mc5_write(adap, IDT_LAR_ADR0, IDT_CMD_WRITE)) in init_idt52100()
198 dbgi_wr_data3(adap, 0xffffffff, 0xffffffff, 0); in init_idt52100()
199 if (mc5_write(adap, IDT_SSR0_ADR0, IDT_CMD_WRITE) || in init_idt52100()
200 mc5_write(adap, IDT_SSR1_ADR0, IDT_CMD_WRITE)) in init_idt52100()
206 dbgi_wr_data3(adap, 0xfffffff9, 0xffffffff, 0xff); in init_idt52100()
208 dbgi_wr_data3(adap, 0xfffffff9, 0xffff8007, 0xff); in init_idt52100()
210 dbgi_wr_data3(adap, 0xffffffff, 0xffffffff, 0xff); in init_idt52100()
212 if (mc5_write(adap, IDT_GMR_BASE_ADR0 + i, IDT_CMD_WRITE)) in init_idt52100()
217 dbgi_wr_data3(adap, 1, 0, 0); in init_idt52100()
218 if (mc5_write(adap, IDT_SCR_ADR0, IDT_CMD_WRITE)) in init_idt52100()
230 struct adapter *adap = mc5->adapter; in init_idt43102() local
232 t3_write_reg(adap, A_MC5_DB_RSP_LATENCY, in init_idt43102()
233 adap->params.rev == 0 ? V_RDLAT(0xd) | V_SRCHLAT(0x11) : in init_idt43102()
240 t3_write_reg(adap, A_MC5_DB_POPEN_DATA_WR_CMD, IDT4_CMD_WRITE); in init_idt43102()
241 t3_write_reg(adap, A_MC5_DB_POPEN_MASK_WR_CMD, IDT4_CMD_WRITE); in init_idt43102()
242 t3_write_reg(adap, A_MC5_DB_AOPEN_SRCH_CMD, in init_idt43102()
244 t3_write_reg(adap, A_MC5_DB_SYN_SRCH_CMD, IDT4_CMD_SEARCH144); in init_idt43102()
245 t3_write_reg(adap, A_MC5_DB_ACK_SRCH_CMD, IDT4_CMD_SEARCH144 | 0x3800); in init_idt43102()
246 t3_write_reg(adap, A_MC5_DB_ILOOKUP_CMD, IDT4_CMD_SEARCH144 | 0x3800); in init_idt43102()
247 t3_write_reg(adap, A_MC5_DB_ELOOKUP_CMD, IDT4_CMD_SEARCH144 | 0x800); in init_idt43102()
248 t3_write_reg(adap, A_MC5_DB_DATA_WRITE_CMD, IDT4_CMD_WRITE); in init_idt43102()
249 t3_write_reg(adap, A_MC5_DB_DATA_READ_CMD, IDT4_CMD_READ); in init_idt43102()
251 t3_write_reg(adap, A_MC5_DB_PART_ID_INDEX, 3); in init_idt43102()
254 t3_write_reg(adap, A_MC5_DB_DBGI_CONFIG, DBGI_MODE_IDT52100); in init_idt43102()
257 dbgi_wr_data3(adap, 0xffffffff, 0xffffffff, 0xff); in init_idt43102()
259 if (mc5_write(adap, IDT4_GMR_BASE0 + i, IDT4_CMD_WRITE)) in init_idt43102()
263 if (mc5_write(adap, IDT4_GMR_BASE2 + i, IDT4_CMD_WRITE)) in init_idt43102()
266 dbgi_wr_data3(adap, 0xfffffff9, 0xffffffff, 0xff); in init_idt43102()
267 if (mc5_write(adap, IDT4_GMR_BASE1, IDT4_CMD_WRITE) || in init_idt43102()
268 mc5_write(adap, IDT4_GMR_BASE1 + 1, IDT4_CMD_WRITE) || in init_idt43102()
269 mc5_write(adap, IDT4_GMR_BASE1 + 4, IDT4_CMD_WRITE)) in init_idt43102()
272 dbgi_wr_data3(adap, 0xfffffff9, 0xffff8007, 0xff); in init_idt43102()
273 if (mc5_write(adap, IDT4_GMR_BASE1 + 5, IDT4_CMD_WRITE)) in init_idt43102()
277 dbgi_wr_data3(adap, 0xf0000000, 0, 0); in init_idt43102()
278 if (mc5_write(adap, IDT4_SCR_ADR0, IDT4_CMD_WRITE)) in init_idt43102()
313 struct adapter *adap = mc5->adapter; in t3_mc5_init() local
322 cfg = t3_read_reg(adap, A_MC5_DB_CONFIG) & ~F_TMMODE; in t3_mc5_init()
324 t3_write_reg(adap, A_MC5_DB_CONFIG, cfg); in t3_mc5_init()
325 if (t3_wait_op_done(adap, A_MC5_DB_CONFIG, F_TMRDY, 1, 500, 0)) { in t3_mc5_init()
326 CH_ERR(adap, "TCAM reset timed out\n"); in t3_mc5_init()
330 t3_write_reg(adap, A_MC5_DB_ROUTING_TABLE_INDEX, tcam_size - nroutes); in t3_mc5_init()
331 t3_write_reg(adap, A_MC5_DB_FILTER_TABLE, in t3_mc5_init()
333 t3_write_reg(adap, A_MC5_DB_SERVER_INDEX, in t3_mc5_init()
339 t3_write_reg(adap, A_MC5_DB_DBGI_REQ_ADDR1, 0); in t3_mc5_init()
340 t3_write_reg(adap, A_MC5_DB_DBGI_REQ_ADDR2, 0); in t3_mc5_init()
352 CH_ERR(adap, "Unsupported TCAM type %d\n", mc5->part_type); in t3_mc5_init()
369 struct adapter *adap = mc5->adapter; in t3_mc5_intr_handler() local
370 u32 cause = t3_read_reg(adap, A_MC5_DB_INT_CAUSE); in t3_mc5_intr_handler()
373 CH_ALERT(adap, "MC5 parity error\n"); in t3_mc5_intr_handler()
378 CH_ALERT(adap, "MC5 request queue parity error\n"); in t3_mc5_intr_handler()
383 CH_ALERT(adap, "MC5 dispatch queue parity error\n"); in t3_mc5_intr_handler()
396 t3_fatal_err(adap); in t3_mc5_intr_handler()
398 t3_write_reg(adap, A_MC5_DB_INT_CAUSE, cause); in t3_mc5_intr_handler()