Lines Matching refs:u_long
660 #define DE4X5_ALIGN4 ((u_long)4 - 1) /* 1 longword align */
661 #define DE4X5_ALIGN8 ((u_long)8 - 1) /* 2 longword align */
662 #define DE4X5_ALIGN16 ((u_long)16 - 1) /* 4 longword align */
663 #define DE4X5_ALIGN32 ((u_long)32 - 1) /* 8 longword align */
664 #define DE4X5_ALIGN64 ((u_long)64 - 1) /* 16 longword align */
665 #define DE4X5_ALIGN128 ((u_long)128 - 1) /* 32 longword align */
790 u_long interrupt; /* Aligned ISR flag */
827 u_long lock; /* Lock the cache accesses */
912 static int de4x5_hw_init(struct net_device *dev, u_long iobase, struct device *gendev);
957 static void DevicePresent(struct net_device *dev, u_long iobase);
958 static void enet_addr_rst(u_long aprom_addr);
960 static short srom_rd(u_long address, u_char offset);
961 static void srom_latch(u_int command, u_long address);
962 static void srom_command(u_int command, u_long address);
963 static void srom_address(u_int command, u_long address, u_char offset);
964 static short srom_data(u_int command, u_long address);
966 static void sendto_srom(u_int command, u_long addr);
967 static int getfrom_srom(u_long addr);
972 static int mii_rd(u_char phyreg, u_char phyaddr, u_long ioaddr);
973 static void mii_wr(int data, u_char phyreg, u_char phyaddr, u_long ioaddr);
974 static int mii_rdata(u_long ioaddr);
975 static void mii_wdata(int data, int len, u_long ioaddr);
976 static void mii_ta(u_long rw, u_long ioaddr);
978 static void mii_address(u_char addr, u_long ioaddr);
979 static void sendto_mii(u32 command, int data, u_long ioaddr);
980 static int getfrom_mii(u32 command, u_long ioaddr);
981 static int mii_get_oui(u_char phyaddr, u_long ioaddr);
1096 de4x5_hw_init(struct net_device *dev, u_long iobase, struct device *gendev) in de4x5_hw_init()
1294 u_long iobase = dev->base_addr; in de4x5_open()
1384 u_long iobase = dev->base_addr; in de4x5_sw_reset()
1462 u_long iobase = dev->base_addr; in de4x5_queue_pkt()
1463 u_long flags = 0; in de4x5_queue_pkt()
1483 if (netif_queue_stopped(dev) || (u_long) lp->tx_skb[lp->tx_new] > 1) { in de4x5_queue_pkt()
1490 …(DE4X5_STS), netif_queue_stopped(dev), inl(DE4X5_IMR), inl(DE4X5_OMR), ((u_long) lp->tx_skb[lp->tx… in de4x5_queue_pkt()
1500 (u_long) lp->tx_skb[lp->tx_new] <= 1) { in de4x5_queue_pkt()
1543 u_long iobase; in de4x5_interrupt()
1606 u_long iobase = dev->base_addr; in de4x5_rx()
1684 if ((u_long) lp->tx_skb[entry] > 1) in de4x5_free_tx_buff()
1696 u_long iobase = dev->base_addr; in de4x5_tx()
1774 u_long iobase = dev->base_addr; in de4x5_txur()
1797 u_long iobase = dev->base_addr; in de4x5_rx_ovfc()
1818 u_long iobase = dev->base_addr; in de4x5_close()
1854 u_long iobase = dev->base_addr; in de4x5_get_stats()
1922 u_long iobase = dev->base_addr; in set_multicast_list()
1953 u_long iobase = dev->base_addr; in SetMulticastFilter()
1999 u_long iobase; in de4x5_eisa_probe()
2085 u_long iobase; in de4x5_eisa_remove()
2128 u_long iobase = 0; /* Clear upper 32 bits in Alphas */ in srom_search()
2202 u_long iobase = 0; /* Clear upper 32 bits in Alphas */ in de4x5_pci_probe()
2321 u_long iobase; in de4x5_pci_remove()
2364 u_long iobase = dev->base_addr; in autoconf_media()
2394 u_long iobase = dev->base_addr; in dc21040_autoconf()
2548 u_long iobase = dev->base_addr; in dc21041_autoconf()
2752 u_long imr, omr, iobase = dev->base_addr; in dc21140m_autoconf()
2934 u_long iobase = dev->base_addr; in dc2114x_autoconf()
3269 u_long iobase = dev->base_addr; in de4x5_init_connection()
3270 u_long flags = 0; in de4x5_init_connection()
3296 u_long iobase = dev->base_addr; in de4x5_reset_phy()
3330 u_long iobase = dev->base_addr; in test_media()
3368 u_long iobase = dev->base_addr; in test_tp()
3451 u_long iobase = dev->base_addr; in test_mii_reg()
3473 u_long iobase = dev->base_addr; in is_spd_100()
3497 u_long iobase = dev->base_addr; in is_100_up()
3518 u_long iobase = dev->base_addr; in is_10_up()
3541 u_long iobase = dev->base_addr; in is_anc_capable()
3560 u_long iobase = dev->base_addr; in ping_media()
3605 u_long i=0, tmp; in de4x5_alloc_rx_buff()
3618 if ((u_long) ret > 1) { in de4x5_alloc_rx_buff()
3650 if ((u_long) lp->rx_skb[i] > 1) { in de4x5_free_rx_buffs()
3685 u_long iobase = dev->base_addr; in de4x5_save_skbs()
3704 u_long iobase = dev->base_addr; in de4x5_rst_desc_ring()
3735 u_long iobase = dev->base_addr; in de4x5_cache_state()
3791 u_long iobase = dev->base_addr; in test_ans()
3819 u_long iobase = dev->base_addr; in de4x5_setup_intr()
3838 u_long iobase = dev->base_addr; in reset_init_sia()
3951 DevicePresent(struct net_device *dev, u_long aprom_addr) in DevicePresent()
3990 enet_addr_rst(u_long aprom_addr) in enet_addr_rst()
4030 u_long iobase = dev->base_addr; in get_hw_addr()
4202 srom_rd(u_long addr, u_char offset) in srom_rd()
4214 srom_latch(u_int command, u_long addr) in srom_latch()
4222 srom_command(u_int command, u_long addr) in srom_command()
4230 srom_address(u_int command, u_long addr, u_char offset) in srom_address()
4244 srom_data(u_int command, u_long addr) in srom_data()
4278 sendto_srom(u_int command, u_long addr) in sendto_srom()
4285 getfrom_srom(u_long addr) in getfrom_srom()
4390 u_long iobase = dev->base_addr; in srom_exec()
4813 mii_rd(u_char phyreg, u_char phyaddr, u_long ioaddr) in mii_rd()
4826 mii_wr(int data, u_char phyreg, u_char phyaddr, u_long ioaddr) in mii_wr()
4839 mii_rdata(u_long ioaddr) in mii_rdata()
4853 mii_wdata(int data, int len, u_long ioaddr) in mii_wdata()
4864 mii_address(u_char addr, u_long ioaddr) in mii_address()
4876 mii_ta(u_long rw, u_long ioaddr) in mii_ta()
4901 sendto_mii(u32 command, int data, u_long ioaddr) in sendto_mii()
4913 getfrom_mii(u32 command, u_long ioaddr) in getfrom_mii()
4927 mii_get_oui(u_char phyaddr, u_long ioaddr) in mii_get_oui()
4977 u_long iobase = dev->base_addr; in mii_get_phy()
5084 u_long iobase = dev->base_addr; in de4x5_switch_mac_port()
5120 u_long iobase = dev->base_addr; in gep_wr()
5133 u_long iobase = dev->base_addr; in gep_rd()
5148 u_long iobase = dev->base_addr; in yawn()
5239 printk("\t0x%8.8lx 0x%8.8lx\n",(u_long)lp->rx_ring,(u_long)lp->tx_ring); in de4x5_dbg_open()
5243 printk("0x%8.8lx ",(u_long)&lp->rx_ring[i].status); in de4x5_dbg_open()
5246 printk("...0x%8.8lx\n",(u_long)&lp->rx_ring[i].status); in de4x5_dbg_open()
5250 printk("0x%8.8lx ", (u_long)&lp->tx_ring[i].status); in de4x5_dbg_open()
5253 printk("...0x%8.8lx\n", (u_long)&lp->tx_ring[i].status); in de4x5_dbg_open()
5278 u_long iobase = dev->base_addr; in de4x5_dbg_mii()
5375 u_long iobase = dev->base_addr; in de4x5_siocdevprivate()
5383 u_long flags = 0; in de4x5_siocdevprivate()