Lines Matching defs:fec
24 struct fec { struct
25 u32 fec_reserved0; argument
26 u32 fec_ievent; /* Interrupt event reg */ argument
27 u32 fec_imask; /* Interrupt mask reg */ argument
28 u32 fec_reserved1; argument
29 u32 fec_r_des_active; /* Receive descriptor reg */ argument
30 u32 fec_x_des_active; /* Transmit descriptor reg */ argument
31 u32 fec_reserved2[3]; argument
32 u32 fec_ecntrl; /* Ethernet control reg */ argument
33 u32 fec_reserved3[6]; argument
34 u32 fec_mii_data; /* MII manage frame reg */ argument
35 u32 fec_mii_speed; /* MII speed control reg */ argument
36 u32 fec_reserved4[7]; argument
37 u32 fec_mib_ctrlstat; /* MIB control/status reg */ argument
38 u32 fec_reserved5[7]; argument
39 u32 fec_r_cntrl; /* Receive control reg */ argument
40 u32 fec_reserved6[15]; argument
41 u32 fec_x_cntrl; /* Transmit Control reg */ argument
42 u32 fec_reserved7[7]; argument
43 u32 fec_addr_low; /* Low 32bits MAC address */ argument
44 u32 fec_addr_high; /* High 16bits MAC address */ argument
45 u32 fec_opd; /* Opcode + Pause duration */ argument
46 u32 fec_reserved8[10]; argument
47 u32 fec_hash_table_high; /* High 32bits hash table */ argument
48 u32 fec_hash_table_low; /* Low 32bits hash table */ argument
49 u32 fec_grp_hash_table_high; /* High 32bits hash table */ argument
50 u32 fec_grp_hash_table_low; /* Low 32bits hash table */ argument
51 u32 fec_reserved9[7]; argument
52 u32 fec_x_wmrk; /* FIFO transmit water mark */ argument
53 u32 fec_reserved10; argument
54 u32 fec_r_bound; /* FIFO receive bound reg */ argument
55 u32 fec_r_fstart; /* FIFO receive start reg */ argument
56 u32 fec_reserved11[11]; argument
57 u32 fec_r_des_start; /* Receive descriptor ring */ argument
58 u32 fec_x_des_start; /* Transmit descriptor ring */ argument
59 u32 fec_r_buff_size; /* Maximum receive buff size */ argument
60 u32 fec_reserved12[26]; argument
61 u32 fec_dma_control; /* DMA Endian and other ctrl */ argument
163 } fec; member