Lines Matching refs:writel_relaxed
315 writel_relaxed(val, priv->ctrl_base); in hix5hd2_config_port()
318 writel_relaxed(BIT_MODE_CHANGE_EN, priv->base + MODE_CHANGE_EN); in hix5hd2_config_port()
325 writel_relaxed(val, priv->base + PORT_MODE); in hix5hd2_config_port()
326 writel_relaxed(0, priv->base + MODE_CHANGE_EN); in hix5hd2_config_port()
327 writel_relaxed(duplex, priv->base + MAC_DUPLEX_HALF_CTRL); in hix5hd2_config_port()
332 writel_relaxed(BITS_RX_FQ_DEPTH_EN, priv->base + RX_FQ_REG_EN); in hix5hd2_set_desc_depth()
333 writel_relaxed(rx << 3, priv->base + RX_FQ_DEPTH); in hix5hd2_set_desc_depth()
334 writel_relaxed(0, priv->base + RX_FQ_REG_EN); in hix5hd2_set_desc_depth()
336 writel_relaxed(BITS_RX_BQ_DEPTH_EN, priv->base + RX_BQ_REG_EN); in hix5hd2_set_desc_depth()
337 writel_relaxed(rx << 3, priv->base + RX_BQ_DEPTH); in hix5hd2_set_desc_depth()
338 writel_relaxed(0, priv->base + RX_BQ_REG_EN); in hix5hd2_set_desc_depth()
340 writel_relaxed(BITS_TX_BQ_DEPTH_EN, priv->base + TX_BQ_REG_EN); in hix5hd2_set_desc_depth()
341 writel_relaxed(tx << 3, priv->base + TX_BQ_DEPTH); in hix5hd2_set_desc_depth()
342 writel_relaxed(0, priv->base + TX_BQ_REG_EN); in hix5hd2_set_desc_depth()
344 writel_relaxed(BITS_TX_RQ_DEPTH_EN, priv->base + TX_RQ_REG_EN); in hix5hd2_set_desc_depth()
345 writel_relaxed(tx << 3, priv->base + TX_RQ_DEPTH); in hix5hd2_set_desc_depth()
346 writel_relaxed(0, priv->base + TX_RQ_REG_EN); in hix5hd2_set_desc_depth()
351 writel_relaxed(BITS_RX_FQ_START_ADDR_EN, priv->base + RX_FQ_REG_EN); in hix5hd2_set_rx_fq()
352 writel_relaxed(phy_addr, priv->base + RX_FQ_START_ADDR); in hix5hd2_set_rx_fq()
353 writel_relaxed(0, priv->base + RX_FQ_REG_EN); in hix5hd2_set_rx_fq()
358 writel_relaxed(BITS_RX_BQ_START_ADDR_EN, priv->base + RX_BQ_REG_EN); in hix5hd2_set_rx_bq()
359 writel_relaxed(phy_addr, priv->base + RX_BQ_START_ADDR); in hix5hd2_set_rx_bq()
360 writel_relaxed(0, priv->base + RX_BQ_REG_EN); in hix5hd2_set_rx_bq()
365 writel_relaxed(BITS_TX_BQ_START_ADDR_EN, priv->base + TX_BQ_REG_EN); in hix5hd2_set_tx_bq()
366 writel_relaxed(phy_addr, priv->base + TX_BQ_START_ADDR); in hix5hd2_set_tx_bq()
367 writel_relaxed(0, priv->base + TX_BQ_REG_EN); in hix5hd2_set_tx_bq()
372 writel_relaxed(BITS_TX_RQ_START_ADDR_EN, priv->base + TX_RQ_REG_EN); in hix5hd2_set_tx_rq()
373 writel_relaxed(phy_addr, priv->base + TX_RQ_START_ADDR); in hix5hd2_set_tx_rq()
374 writel_relaxed(0, priv->base + TX_RQ_REG_EN); in hix5hd2_set_tx_rq()
390 writel_relaxed(0, priv->base + ENA_PMU_INT); in hix5hd2_hw_init()
391 writel_relaxed(~0, priv->base + RAW_PMU_INT); in hix5hd2_hw_init()
393 writel_relaxed(BIT_CRC_ERR_PASS, priv->base + REC_FILT_CONTROL); in hix5hd2_hw_init()
394 writel_relaxed(MAC_MAX_FRAME_SIZE, priv->base + CONTROL_WORD); in hix5hd2_hw_init()
395 writel_relaxed(0, priv->base + COL_SLOT_TIME); in hix5hd2_hw_init()
398 writel_relaxed(val, priv->base + IN_QUEUE_TH); in hix5hd2_hw_init()
400 writel_relaxed(RX_BQ_IN_TIMEOUT, priv->base + RX_BQ_IN_TIMEOUT_TH); in hix5hd2_hw_init()
401 writel_relaxed(TX_RQ_IN_TIMEOUT, priv->base + TX_RQ_IN_TIMEOUT_TH); in hix5hd2_hw_init()
409 writel_relaxed(DEF_INT_MASK, priv->base + ENA_PMU_INT); in hix5hd2_irq_enable()
414 writel_relaxed(0, priv->base + ENA_PMU_INT); in hix5hd2_irq_disable()
419 writel_relaxed(0xf, priv->base + DESC_WR_RD_ENA); in hix5hd2_port_enable()
420 writel_relaxed(BITS_RX_EN | BITS_TX_EN, priv->base + PORT_EN); in hix5hd2_port_enable()
425 writel_relaxed(~(u32)(BITS_RX_EN | BITS_TX_EN), priv->base + PORT_EN); in hix5hd2_port_disable()
426 writel_relaxed(0, priv->base + DESC_WR_RD_ENA); in hix5hd2_port_disable()
436 writel_relaxed(val, priv->base + STATION_ADDR_HIGH); in hix5hd2_hw_set_mac_addr()
439 writel_relaxed(val, priv->base + STATION_ADDR_LOW); in hix5hd2_hw_set_mac_addr()
505 writel_relaxed(dma_byte(pos), priv->base + RX_FQ_WR_ADDR); in hix5hd2_rx_refill()
559 writel_relaxed(dma_byte(pos), priv->base + RX_BQ_RD_ADDR); in hix5hd2_rx()
629 writel_relaxed(dma_byte(pos), priv->base + TX_RQ_RD_ADDR); in hix5hd2_xmit_reclaim()
657 writel_relaxed(ints, priv->base + RAW_PMU_INT); in hix5hd2_poll()
674 writel_relaxed(ints, priv->base + RAW_PMU_INT); in hix5hd2_interrupt()
783 writel_relaxed(dma_byte(pos), priv->base + TX_BQ_WR_ADDR); in hix5hd2_net_xmit()
942 writel_relaxed(MDIO_READ | phy << 8 | reg, base + MDIO_SINGLE_CMD); in hix5hd2_mdio_read()
970 writel_relaxed(val, base + MDIO_SINGLE_DATA); in hix5hd2_mdio_write()
971 writel_relaxed(MDIO_WRITE | phy << 8 | reg, base + MDIO_SINGLE_CMD); in hix5hd2_mdio_write()