Lines Matching refs:hw_dbg
541 hw_dbg("PHY module has not been recognized\n"); in igb_set_sfp_media_type_82575()
768 hw_dbg("PHY Address %u is out of range\n", offset); in igb_read_phy_reg_sgmii_82575()
800 hw_dbg("PHY Address %d is out of range\n", offset); in igb_write_phy_reg_sgmii_82575()
884 hw_dbg("Vendor ID 0x%08X read at address %u\n", in igb_get_phy_id_82575()
892 hw_dbg("PHY address %u was unreadable\n", phy->addr); in igb_get_phy_id_82575()
927 hw_dbg("Soft resetting SGMII attached PHY...\n"); in igb_phy_hw_reset_sgmii_82575()
1184 hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n"); in igb_acquire_swfw_sync_82575()
1249 hw_dbg("MNG configuration cycle has not completed.\n"); in igb_get_cfg_done_82575()
1312 hw_dbg("Error configuring flow control\n"); in igb_check_for_link_82575()
1402 hw_dbg("2500 Mbs, "); in igb_get_pcs_speed_and_duplex_82575()
1403 hw_dbg("Full Duplex\n"); in igb_get_pcs_speed_and_duplex_82575()
1461 hw_dbg("PCI-E Master disable polling has failed.\n"); in igb_reset_hw_82575()
1466 hw_dbg("PCI-E Set completion timeout has failed.\n"); in igb_reset_hw_82575()
1468 hw_dbg("Masking off all interrupts\n"); in igb_reset_hw_82575()
1479 hw_dbg("Issuing a global reset to MAC\n"); in igb_reset_hw_82575()
1488 hw_dbg("Auto Read Done did not complete\n"); in igb_reset_hw_82575()
1527 hw_dbg("Error initializing identification LED\n"); in igb_init_hw_82575()
1532 hw_dbg("Initializing the IEEE VLAN\n"); in igb_init_hw_82575()
1539 hw_dbg("Zeroing the MTA\n"); in igb_init_hw_82575()
1544 hw_dbg("Zeroing the UTA\n"); in igb_init_hw_82575()
1603 hw_dbg("Error resetting the PHY.\n"); in igb_setup_copper_link_82575()
1713 hw_dbg(KERN_DEBUG "NVM Read Error\n\n"); in igb_setup_serdes_link_82575()
1768 hw_dbg("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg); in igb_setup_serdes_link_82575()
1776 hw_dbg("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg); in igb_setup_serdes_link_82575()
1811 hw_dbg("Running reset init script for 82575\n"); in igb_reset_init_script_82575()
1976 hw_dbg("Queue disable timed out after 10ms\n"); in igb_rx_fifo_flush_82575()
2229 hw_dbg("NVM Read Error\n"); in igb_reset_mdicnfg_82580()
2274 hw_dbg("PCI-E Master disable polling has failed.\n"); in igb_reset_hw_82580()
2276 hw_dbg("Masking off all interrupts\n"); in igb_reset_hw_82580()
2308 hw_dbg("Auto Read Done did not complete\n"); in igb_reset_hw_82580()
2320 hw_dbg("Could not reset MDICNFG based on EEPROM\n"); in igb_reset_hw_82580()
2371 hw_dbg("NVM Read Error\n"); in igb_validate_nvm_checksum_with_offset()
2378 hw_dbg("NVM Checksum Invalid\n"); in igb_validate_nvm_checksum_with_offset()
2406 hw_dbg("NVM Read Error while updating checksum.\n"); in igb_update_nvm_checksum_with_offset()
2415 hw_dbg("NVM Write Error while updating checksum.\n"); in igb_update_nvm_checksum_with_offset()
2438 hw_dbg("NVM Read Error\n"); in igb_validate_nvm_checksum_82580()
2477 hw_dbg("NVM Read Error while updating checksum compatibility bit.\n"); in igb_update_nvm_checksum_82580()
2487 hw_dbg("NVM Write Error while updating checksum compatibility bit.\n"); in igb_update_nvm_checksum_82580()
2627 hw_dbg("LPI Clock Stop Bit should not be set!\n"); in igb_set_eee_i350()