Lines Matching refs:MLXSW_ITEM32
77 MLXSW_ITEM32(pci, wqe, c, 0x00, 31, 1);
89 MLXSW_ITEM32(pci, wqe, lp, 0x00, 30, 1);
94 MLXSW_ITEM32(pci, wqe, type, 0x00, 23, 4);
146 MLXSW_ITEM32(pci, cqe0, lag, 0x00, 23, 1);
147 MLXSW_ITEM32(pci, cqe12, lag, 0x00, 24, 1);
156 MLXSW_ITEM32(pci, cqe, system_port, 0x00, 0, 16);
157 MLXSW_ITEM32(pci, cqe0, lag_id, 0x00, 4, 12);
158 MLXSW_ITEM32(pci, cqe12, lag_id, 0x00, 0, 16);
160 MLXSW_ITEM32(pci, cqe0, lag_subport, 0x00, 0, 4);
161 MLXSW_ITEM32(pci, cqe12, lag_subport, 0x00, 16, 8);
167 MLXSW_ITEM32(pci, cqe, wqe_counter, 0x04, 16, 16);
174 MLXSW_ITEM32(pci, cqe, byte_count, 0x04, 0, 14);
183 MLXSW_ITEM32(pci, cqe2, mirror_cong_high, 0x08, 16, 4);
188 MLXSW_ITEM32(pci, cqe, trap_id, 0x08, 0, 10);
194 MLXSW_ITEM32(pci, cqe0, crc, 0x0C, 8, 1);
195 MLXSW_ITEM32(pci, cqe12, crc, 0x0C, 9, 1);
201 MLXSW_ITEM32(pci, cqe0, e, 0x0C, 7, 1);
202 MLXSW_ITEM32(pci, cqe12, e, 0x00, 27, 1);
209 MLXSW_ITEM32(pci, cqe0, sr, 0x0C, 6, 1);
210 MLXSW_ITEM32(pci, cqe12, sr, 0x00, 26, 1);
216 MLXSW_ITEM32(pci, cqe0, dqn, 0x0C, 1, 5);
217 MLXSW_ITEM32(pci, cqe12, dqn, 0x0C, 1, 6);
226 MLXSW_ITEM32(pci, cqe2, mirror_tclass, 0x10, 27, 5);
231 MLXSW_ITEM32(pci, cqe2, tx_lag, 0x10, 24, 1);
237 MLXSW_ITEM32(pci, cqe2, tx_lag_subport, 0x10, 16, 8);
247 MLXSW_ITEM32(pci, cqe2, tx_lag_id, 0x10, 0, 16);
254 MLXSW_ITEM32(pci, cqe2, tx_system_port, 0x10, 0, 16);
261 MLXSW_ITEM32(pci, cqe2, mirror_cong_low, 0x14, 20, 12);
276 MLXSW_ITEM32(pci, cqe2, user_def_val_orig_pkt_len, 0x14, 0, 20);
281 MLXSW_ITEM32(pci, cqe2, mirror_reason, 0x18, 24, 8);
290 MLXSW_ITEM32(pci, cqe2, mirror_latency, 0x1C, 8, 24);
295 MLXSW_ITEM32(pci, cqe01, owner, 0x0C, 0, 1);
296 MLXSW_ITEM32(pci, cqe2, owner, 0x1C, 0, 1);
302 MLXSW_ITEM32(pci, eqe, event_type, 0x0C, 24, 8);
309 MLXSW_ITEM32(pci, eqe, event_sub_type, 0x0C, 16, 8);
314 MLXSW_ITEM32(pci, eqe, cqn, 0x0C, 8, 7);
319 MLXSW_ITEM32(pci, eqe, owner, 0x0C, 0, 1);
324 MLXSW_ITEM32(pci, eqe, cmd_token, 0x00, 16, 16);
329 MLXSW_ITEM32(pci, eqe, cmd_status, 0x00, 0, 8);
334 MLXSW_ITEM32(pci, eqe, cmd_out_param_h, 0x04, 0, 32);
339 MLXSW_ITEM32(pci, eqe, cmd_out_param_l, 0x08, 0, 32);