Lines Matching refs:ECON1
202 if (addr >= EIE && addr <= ECON1) in enc28j60_set_bank()
208 spi_write_op(priv, ENC28J60_BIT_FIELD_SET, ECON1, in enc28j60_set_bank()
211 spi_write_op(priv, ENC28J60_BIT_FIELD_CLR, ECON1, in enc28j60_set_bank()
216 spi_write_op(priv, ENC28J60_BIT_FIELD_SET, ECON1, in enc28j60_set_bank()
219 spi_write_op(priv, ENC28J60_BIT_FIELD_CLR, ECON1, in enc28j60_set_bank()
545 nolock_regb_read(priv, ECON1), nolock_regb_read(priv, ECON2), in enc28j60_dump_regs()
636 nolock_reg_bfclr(priv, ECON1, ECON1_RXEN); in enc28j60_lowpower()
638 poll_ready(priv, ECON1, ECON1_TXRTS, 0); in enc28j60_lowpower()
662 spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, ECON1, 0x00); in enc28j60_hw_init()
762 nolock_reg_bfset(priv, ECON1, ECON1_RXEN); in enc28j60_hw_enable()
772 nolock_reg_bfclr(priv, ECON1, ECON1_RXEN); in enc28j60_hw_disable()
922 nolock_reg_bfclr(priv, ECON1, ECON1_RXEN); in enc28j60_hw_rx()
923 nolock_reg_bfset(priv, ECON1, ECON1_RXRST); in enc28j60_hw_rx()
924 nolock_reg_bfclr(priv, ECON1, ECON1_RXRST); in enc28j60_hw_rx()
927 nolock_reg_bfset(priv, ECON1, ECON1_RXEN); in enc28j60_hw_rx()
1086 locked_reg_bfclr(priv, ECON1, ECON1_TXRTS); in enc28j60_tx_clear()
1182 locked_reg_bfclr(priv, ECON1, ECON1_TXRTS); in enc28j60_irq_work_handler()
1188 nolock_reg_bfset(priv, ECON1, ECON1_TXRST); in enc28j60_irq_work_handler()
1189 nolock_reg_bfclr(priv, ECON1, ECON1_TXRST); in enc28j60_irq_work_handler()
1199 locked_reg_bfset(priv, ECON1, in enc28j60_irq_work_handler()
1278 locked_reg_bfset(priv, ECON1, ECON1_TXRTS); in enc28j60_hw_tx()