Lines Matching defs:x
60 #define ANA_AC_RAM_INIT_RAM_INIT_SET(x)\ argument
62 #define ANA_AC_RAM_INIT_RAM_INIT_GET(x)\ argument
66 #define ANA_AC_RAM_INIT_RAM_CFG_HOOK_SET(x)\ argument
68 #define ANA_AC_RAM_INIT_RAM_CFG_HOOK_GET(x)\ argument
75 #define ANA_AC_OWN_UPSID_OWN_UPSID_SET(x)\ argument
77 #define ANA_AC_OWN_UPSID_OWN_UPSID_GET(x)\ argument
90 #define ANA_AC_SRC_CFG2_PORT_MASK2_SET(x)\ argument
92 #define ANA_AC_SRC_CFG2_PORT_MASK2_GET(x)\ argument
105 #define ANA_AC_PGID_CFG2_PORT_MASK2_SET(x)\ argument
107 #define ANA_AC_PGID_CFG2_PORT_MASK2_GET(x)\ argument
114 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_QU_SET(x)\ argument
116 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_QU_GET(x)\ argument
120 #define ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA_SET(x)\ argument
122 #define ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA_GET(x)\ argument
126 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_SET(x)\ argument
128 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_GET(x)\ argument
135 #define ANA_AC_PORT_SGE_CFG_MASK_SET(x)\ argument
137 #define ANA_AC_PORT_SGE_CFG_MASK_GET(x)\ argument
144 #define ANA_AC_STAT_RESET_RESET_SET(x)\ argument
146 #define ANA_AC_STAT_RESET_RESET_GET(x)\ argument
153 #define ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK_SET(x)\ argument
155 #define ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK_GET(x)\ argument
159 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE_SET(x)\ argument
161 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE_GET(x)\ argument
165 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE_SET(x)\ argument
167 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE_GET(x)\ argument
177 #define ANA_ACL_OWN_UPSID_OWN_UPSID_SET(x)\ argument
179 #define ANA_ACL_OWN_UPSID_OWN_UPSID_GET(x)\ argument
186 #define ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT_SET(x)\ argument
188 #define ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT_GET(x)\ argument
195 #define ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS_SET(x)\ argument
197 #define ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS_GET(x)\ argument
201 #define ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT_SET(x)\ argument
203 #define ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT_GET(x)\ argument
207 #define ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA_SET(x)\ argument
209 #define ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA_GET(x)\ argument
213 #define ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA_SET(x)\ argument
215 #define ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA_GET(x)\ argument
222 #define ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS_SET(x)\ argument
224 #define ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS_GET(x)\ argument
228 #define ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT_SET(x)\ argument
230 #define ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT_GET(x)\ argument
234 #define ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA_SET(x)\ argument
236 #define ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA_GET(x)\ argument
240 #define ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA_SET(x)\ argument
242 #define ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA_GET(x)\ argument
249 #define ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS_SET(x)\ argument
251 #define ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS_GET(x)\ argument
255 #define ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS_SET(x)\ argument
257 #define ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS_GET(x)\ argument
261 #define ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA_SET(x)\ argument
263 #define ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA_GET(x)\ argument
270 #define ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA_SET(x)\ argument
272 #define ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA_GET(x)\ argument
276 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS_SET(x)\ argument
278 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS_GET(x)\ argument
282 #define ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS_SET(x)\ argument
284 #define ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS_GET(x)\ argument
288 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS_SET(x)\ argument
290 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS_GET(x)\ argument
294 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS_SET(x)\ argument
296 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS_GET(x)\ argument
300 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS_SET(x)\ argument
302 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS_GET(x)\ argument
306 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS_SET(x)\ argument
308 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS_GET(x)\ argument
312 #define ANA_CL_VLAN_FILTER_CTRL_STAG_DIS_SET(x)\ argument
314 #define ANA_CL_VLAN_FILTER_CTRL_STAG_DIS_GET(x)\ argument
318 #define ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS_SET(x)\ argument
320 #define ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS_GET(x)\ argument
324 #define ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS_SET(x)\ argument
326 #define ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS_GET(x)\ argument
330 #define ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS_SET(x)\ argument
332 #define ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS_GET(x)\ argument
339 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA_SET(x)\ argument
341 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA_GET(x)\ argument
345 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS_SET(x)\ argument
347 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS_GET(x)\ argument
354 #define ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS_SET(x)\ argument
356 #define ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS_GET(x)\ argument
360 #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP_SET(x)\ argument
362 #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP_GET(x)\ argument
366 #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI_SET(x)\ argument
368 #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI_GET(x)\ argument
372 #define ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA_SET(x)\ argument
374 #define ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA_GET(x)\ argument
378 #define ANA_CL_VLAN_CTRL_VLAN_TAG_SEL_SET(x)\ argument
380 #define ANA_CL_VLAN_CTRL_VLAN_TAG_SEL_GET(x)\ argument
384 #define ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA_SET(x)\ argument
386 #define ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA_GET(x)\ argument
390 #define ANA_CL_VLAN_CTRL_VLAN_POP_CNT_SET(x)\ argument
392 #define ANA_CL_VLAN_CTRL_VLAN_POP_CNT_GET(x)\ argument
396 #define ANA_CL_VLAN_CTRL_PORT_TAG_TYPE_SET(x)\ argument
398 #define ANA_CL_VLAN_CTRL_PORT_TAG_TYPE_GET(x)\ argument
402 #define ANA_CL_VLAN_CTRL_PORT_PCP_SET(x)\ argument
404 #define ANA_CL_VLAN_CTRL_PORT_PCP_GET(x)\ argument
408 #define ANA_CL_VLAN_CTRL_PORT_DEI_SET(x)\ argument
410 #define ANA_CL_VLAN_CTRL_PORT_DEI_GET(x)\ argument
414 #define ANA_CL_VLAN_CTRL_PORT_VID_SET(x)\ argument
416 #define ANA_CL_VLAN_CTRL_PORT_VID_GET(x)\ argument
423 #define ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT_SET(x)\ argument
425 #define ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT_GET(x)\ argument
435 #define ANA_CL_OWN_UPSID_OWN_UPSID_SET(x)\ argument
437 #define ANA_CL_OWN_UPSID_OWN_UPSID_GET(x)\ argument
450 #define ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2_SET(x)\ argument
452 #define ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2_GET(x)\ argument
459 #define ANA_L2_OWN_UPSID_OWN_UPSID_SET(x)\ argument
461 #define ANA_L2_OWN_UPSID_OWN_UPSID_GET(x)\ argument
468 #define ANA_L3_VLAN_CTRL_VLAN_ENA_SET(x)\ argument
470 #define ANA_L3_VLAN_CTRL_VLAN_ENA_GET(x)\ argument
477 #define ANA_L3_VLAN_CFG_VLAN_MSTP_PTR_SET(x)\ argument
479 #define ANA_L3_VLAN_CFG_VLAN_MSTP_PTR_GET(x)\ argument
483 #define ANA_L3_VLAN_CFG_VLAN_FID_SET(x)\ argument
485 #define ANA_L3_VLAN_CFG_VLAN_FID_GET(x)\ argument
489 #define ANA_L3_VLAN_CFG_VLAN_IGR_FILTER_ENA_SET(x)\ argument
491 #define ANA_L3_VLAN_CFG_VLAN_IGR_FILTER_ENA_GET(x)\ argument
495 #define ANA_L3_VLAN_CFG_VLAN_SEC_FWD_ENA_SET(x)\ argument
497 #define ANA_L3_VLAN_CFG_VLAN_SEC_FWD_ENA_GET(x)\ argument
501 #define ANA_L3_VLAN_CFG_VLAN_FLOOD_DIS_SET(x)\ argument
503 #define ANA_L3_VLAN_CFG_VLAN_FLOOD_DIS_GET(x)\ argument
507 #define ANA_L3_VLAN_CFG_VLAN_LRN_DIS_SET(x)\ argument
509 #define ANA_L3_VLAN_CFG_VLAN_LRN_DIS_GET(x)\ argument
513 #define ANA_L3_VLAN_CFG_VLAN_RLEG_ENA_SET(x)\ argument
515 #define ANA_L3_VLAN_CFG_VLAN_RLEG_ENA_GET(x)\ argument
519 #define ANA_L3_VLAN_CFG_VLAN_PRIVATE_ENA_SET(x)\ argument
521 #define ANA_L3_VLAN_CFG_VLAN_PRIVATE_ENA_GET(x)\ argument
525 #define ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA_SET(x)\ argument
527 #define ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA_GET(x)\ argument
540 #define ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2_SET(x)\ argument
542 #define ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2_GET(x)\ argument
816 #define ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_SET(x)\ argument
818 #define ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_GET(x)\ argument
825 #define ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_SET(x)\ argument
827 #define ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_GET(x)\ argument
834 #define ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_SET(x)\ argument
836 #define ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_GET(x)\ argument
843 #define ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_SET(x)\ argument
845 #define ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_GET(x)\ argument
852 #define ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_SET(x)\ argument
854 #define ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_GET(x)\ argument
861 #define ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_SET(x)\ argument
863 #define ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_GET(x)\ argument
870 #define ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_SET(x)\ argument
872 #define ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_GET(x)\ argument
879 #define ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_SET(x)\ argument
881 #define ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_GET(x)\ argument
891 #define ASM_STAT_CFG_STAT_CNT_CLR_SHOT_SET(x)\ argument
893 #define ASM_STAT_CFG_STAT_CNT_CLR_SHOT_GET(x)\ argument
900 #define ASM_PORT_CFG_CSC_STAT_DIS_SET(x)\ argument
902 #define ASM_PORT_CFG_CSC_STAT_DIS_GET(x)\ argument
906 #define ASM_PORT_CFG_HIH_AFTER_PREAMBLE_ENA_SET(x)\ argument
908 #define ASM_PORT_CFG_HIH_AFTER_PREAMBLE_ENA_GET(x)\ argument
912 #define ASM_PORT_CFG_IGN_TAXI_ABORT_ENA_SET(x)\ argument
914 #define ASM_PORT_CFG_IGN_TAXI_ABORT_ENA_GET(x)\ argument
918 #define ASM_PORT_CFG_NO_PREAMBLE_ENA_SET(x)\ argument
920 #define ASM_PORT_CFG_NO_PREAMBLE_ENA_GET(x)\ argument
924 #define ASM_PORT_CFG_SKIP_PREAMBLE_ENA_SET(x)\ argument
926 #define ASM_PORT_CFG_SKIP_PREAMBLE_ENA_GET(x)\ argument
930 #define ASM_PORT_CFG_FRM_AGING_DIS_SET(x)\ argument
932 #define ASM_PORT_CFG_FRM_AGING_DIS_GET(x)\ argument
936 #define ASM_PORT_CFG_PAD_ENA_SET(x)\ argument
938 #define ASM_PORT_CFG_PAD_ENA_GET(x)\ argument
942 #define ASM_PORT_CFG_INJ_DISCARD_CFG_SET(x)\ argument
944 #define ASM_PORT_CFG_INJ_DISCARD_CFG_GET(x)\ argument
948 #define ASM_PORT_CFG_INJ_FORMAT_CFG_SET(x)\ argument
950 #define ASM_PORT_CFG_INJ_FORMAT_CFG_GET(x)\ argument
954 #define ASM_PORT_CFG_VSTAX2_AWR_ENA_SET(x)\ argument
956 #define ASM_PORT_CFG_VSTAX2_AWR_ENA_GET(x)\ argument
960 #define ASM_PORT_CFG_PFRM_FLUSH_SET(x)\ argument
962 #define ASM_PORT_CFG_PFRM_FLUSH_GET(x)\ argument
969 #define ASM_RAM_INIT_RAM_INIT_SET(x)\ argument
971 #define ASM_RAM_INIT_RAM_INIT_GET(x)\ argument
975 #define ASM_RAM_INIT_RAM_CFG_HOOK_SET(x)\ argument
977 #define ASM_RAM_INIT_RAM_CFG_HOOK_GET(x)\ argument
984 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV_SET(x)\ argument
986 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV_GET(x)\ argument
990 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV_SET(x)\ argument
992 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV_GET(x)\ argument
996 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR_SET(x)\ argument
998 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR_GET(x)\ argument
1002 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL_SET(x)\ argument
1004 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL_GET(x)\ argument
1008 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA_SET(x)\ argument
1010 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA_GET(x)\ argument
1014 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA_SET(x)\ argument
1016 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA_GET(x)\ argument
1023 #define CPU_PROC_CTRL_AARCH64_MODE_ENA_SET(x)\ argument
1025 #define CPU_PROC_CTRL_AARCH64_MODE_ENA_GET(x)\ argument
1029 #define CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS_SET(x)\ argument
1031 #define CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS_GET(x)\ argument
1035 #define CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS_SET(x)\ argument
1037 #define CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS_GET(x)\ argument
1041 #define CPU_PROC_CTRL_BE_EXCEP_MODE_SET(x)\ argument
1043 #define CPU_PROC_CTRL_BE_EXCEP_MODE_GET(x)\ argument
1047 #define CPU_PROC_CTRL_VINITHI_SET(x)\ argument
1049 #define CPU_PROC_CTRL_VINITHI_GET(x)\ argument
1053 #define CPU_PROC_CTRL_CFGTE_SET(x)\ argument
1055 #define CPU_PROC_CTRL_CFGTE_GET(x)\ argument
1059 #define CPU_PROC_CTRL_CP15S_DISABLE_SET(x)\ argument
1061 #define CPU_PROC_CTRL_CP15S_DISABLE_GET(x)\ argument
1065 #define CPU_PROC_CTRL_PROC_CRYPTO_DISABLE_SET(x)\ argument
1067 #define CPU_PROC_CTRL_PROC_CRYPTO_DISABLE_GET(x)\ argument
1071 #define CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA_SET(x)\ argument
1073 #define CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA_GET(x)\ argument
1077 #define CPU_PROC_CTRL_ACP_AWCACHE_SET(x)\ argument
1079 #define CPU_PROC_CTRL_ACP_AWCACHE_GET(x)\ argument
1083 #define CPU_PROC_CTRL_ACP_ARCACHE_SET(x)\ argument
1085 #define CPU_PROC_CTRL_ACP_ARCACHE_GET(x)\ argument
1089 #define CPU_PROC_CTRL_L2_FLUSH_REQ_SET(x)\ argument
1091 #define CPU_PROC_CTRL_L2_FLUSH_REQ_GET(x)\ argument
1095 #define CPU_PROC_CTRL_ACP_DISABLE_SET(x)\ argument
1097 #define CPU_PROC_CTRL_ACP_DISABLE_GET(x)\ argument
1104 #define DEV10G_MAC_ENA_CFG_RX_ENA_SET(x)\ argument
1106 #define DEV10G_MAC_ENA_CFG_RX_ENA_GET(x)\ argument
1110 #define DEV10G_MAC_ENA_CFG_TX_ENA_SET(x)\ argument
1112 #define DEV10G_MAC_ENA_CFG_TX_ENA_GET(x)\ argument
1119 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_SET(x)\ argument
1121 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_GET(x)\ argument
1125 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\ argument
1127 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\ argument
1134 #define DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS_SET(x)\ argument
1136 #define DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS_GET(x)\ argument
1143 #define DEV10G_MAC_TAGS_CFG_TAG_ID_SET(x)\ argument
1145 #define DEV10G_MAC_TAGS_CFG_TAG_ID_GET(x)\ argument
1149 #define DEV10G_MAC_TAGS_CFG_TAG_ENA_SET(x)\ argument
1151 #define DEV10G_MAC_TAGS_CFG_TAG_ENA_GET(x)\ argument
1158 #define DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_SET(x)\ argument
1160 #define DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_GET(x)\ argument
1164 #define DEV10G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_SET(x)\ argument
1166 #define DEV10G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_GET(x)\ argument
1170 #define DEV10G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_SET(x)\ argument
1172 #define DEV10G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_GET(x)\ argument
1176 #define DEV10G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_SET(x)\ argument
1178 #define DEV10G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_GET(x)\ argument
1182 #define DEV10G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_SET(x)\ argument
1184 #define DEV10G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_GET(x)\ argument
1188 #define DEV10G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_SET(x)\ argument
1190 #define DEV10G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_GET(x)\ argument
1194 #define DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA_SET(x)\ argument
1196 #define DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA_GET(x)\ argument
1203 #define DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY_SET(x)\ argument
1205 #define DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY_GET(x)\ argument
1209 #define DEV10G_MAC_TX_MONITOR_STICKY_REMOTE_ERR_STATE_STICKY_SET(x)\ argument
1211 #define DEV10G_MAC_TX_MONITOR_STICKY_REMOTE_ERR_STATE_STICKY_GET(x)\ argument
1215 #define DEV10G_MAC_TX_MONITOR_STICKY_LINK_INTERRUPTION_STATE_STICKY_SET(x)\ argument
1217 #define DEV10G_MAC_TX_MONITOR_STICKY_LINK_INTERRUPTION_STATE_STICKY_GET(x)\ argument
1221 #define DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY_SET(x)\ argument
1223 #define DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY_GET(x)\ argument
1227 #define DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY_SET(x)\ argument
1229 #define DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY_GET(x)\ argument
1236 #define DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA_SET(x)\ argument
1238 #define DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA_GET(x)\ argument
1242 #define DEV10G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_SET(x)\ argument
1244 #define DEV10G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_GET(x)\ argument
1248 #define DEV10G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_SET(x)\ argument
1250 #define DEV10G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_GET(x)\ argument
1254 #define DEV10G_DEV_RST_CTRL_SERDES_SPEED_SEL_SET(x)\ argument
1256 #define DEV10G_DEV_RST_CTRL_SERDES_SPEED_SEL_GET(x)\ argument
1260 #define DEV10G_DEV_RST_CTRL_SPEED_SEL_SET(x)\ argument
1262 #define DEV10G_DEV_RST_CTRL_SPEED_SEL_GET(x)\ argument
1266 #define DEV10G_DEV_RST_CTRL_PCS_TX_RST_SET(x)\ argument
1268 #define DEV10G_DEV_RST_CTRL_PCS_TX_RST_GET(x)\ argument
1272 #define DEV10G_DEV_RST_CTRL_PCS_RX_RST_SET(x)\ argument
1274 #define DEV10G_DEV_RST_CTRL_PCS_RX_RST_GET(x)\ argument
1278 #define DEV10G_DEV_RST_CTRL_MAC_TX_RST_SET(x)\ argument
1280 #define DEV10G_DEV_RST_CTRL_MAC_TX_RST_GET(x)\ argument
1284 #define DEV10G_DEV_RST_CTRL_MAC_RX_RST_SET(x)\ argument
1286 #define DEV10G_DEV_RST_CTRL_MAC_RX_RST_GET(x)\ argument
1293 #define DEV10G_PCS25G_CFG_PCS25G_ENA_SET(x)\ argument
1295 #define DEV10G_PCS25G_CFG_PCS25G_ENA_GET(x)\ argument
1302 #define DEV25G_MAC_ENA_CFG_RX_ENA_SET(x)\ argument
1304 #define DEV25G_MAC_ENA_CFG_RX_ENA_GET(x)\ argument
1308 #define DEV25G_MAC_ENA_CFG_TX_ENA_SET(x)\ argument
1310 #define DEV25G_MAC_ENA_CFG_TX_ENA_GET(x)\ argument
1317 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_SET(x)\ argument
1319 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_GET(x)\ argument
1323 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\ argument
1325 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\ argument
1332 #define DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_SET(x)\ argument
1334 #define DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_GET(x)\ argument
1338 #define DEV25G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_SET(x)\ argument
1340 #define DEV25G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_GET(x)\ argument
1344 #define DEV25G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_SET(x)\ argument
1346 #define DEV25G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_GET(x)\ argument
1350 #define DEV25G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_SET(x)\ argument
1352 #define DEV25G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_GET(x)\ argument
1356 #define DEV25G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_SET(x)\ argument
1358 #define DEV25G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_GET(x)\ argument
1362 #define DEV25G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_SET(x)\ argument
1364 #define DEV25G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_GET(x)\ argument
1368 #define DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA_SET(x)\ argument
1370 #define DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA_GET(x)\ argument
1377 #define DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA_SET(x)\ argument
1379 #define DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA_GET(x)\ argument
1383 #define DEV25G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_SET(x)\ argument
1385 #define DEV25G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_GET(x)\ argument
1389 #define DEV25G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_SET(x)\ argument
1391 #define DEV25G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_GET(x)\ argument
1395 #define DEV25G_DEV_RST_CTRL_SERDES_SPEED_SEL_SET(x)\ argument
1397 #define DEV25G_DEV_RST_CTRL_SERDES_SPEED_SEL_GET(x)\ argument
1401 #define DEV25G_DEV_RST_CTRL_SPEED_SEL_SET(x)\ argument
1403 #define DEV25G_DEV_RST_CTRL_SPEED_SEL_GET(x)\ argument
1407 #define DEV25G_DEV_RST_CTRL_PCS_TX_RST_SET(x)\ argument
1409 #define DEV25G_DEV_RST_CTRL_PCS_TX_RST_GET(x)\ argument
1413 #define DEV25G_DEV_RST_CTRL_PCS_RX_RST_SET(x)\ argument
1415 #define DEV25G_DEV_RST_CTRL_PCS_RX_RST_GET(x)\ argument
1419 #define DEV25G_DEV_RST_CTRL_MAC_TX_RST_SET(x)\ argument
1421 #define DEV25G_DEV_RST_CTRL_MAC_TX_RST_GET(x)\ argument
1425 #define DEV25G_DEV_RST_CTRL_MAC_RX_RST_SET(x)\ argument
1427 #define DEV25G_DEV_RST_CTRL_MAC_RX_RST_GET(x)\ argument
1434 #define DEV25G_PCS25G_CFG_PCS25G_ENA_SET(x)\ argument
1436 #define DEV25G_PCS25G_CFG_PCS25G_ENA_GET(x)\ argument
1443 #define DEV25G_PCS25G_SD_CFG_SD_SEL_SET(x)\ argument
1445 #define DEV25G_PCS25G_SD_CFG_SD_SEL_GET(x)\ argument
1449 #define DEV25G_PCS25G_SD_CFG_SD_POL_SET(x)\ argument
1451 #define DEV25G_PCS25G_SD_CFG_SD_POL_GET(x)\ argument
1455 #define DEV25G_PCS25G_SD_CFG_SD_ENA_SET(x)\ argument
1457 #define DEV25G_PCS25G_SD_CFG_SD_ENA_GET(x)\ argument
1464 #define DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_SET(x)\ argument
1466 #define DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_GET(x)\ argument
1470 #define DEV2G5_DEV_RST_CTRL_SPEED_SEL_SET(x)\ argument
1472 #define DEV2G5_DEV_RST_CTRL_SPEED_SEL_GET(x)\ argument
1476 #define DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST_SET(x)\ argument
1478 #define DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST_GET(x)\ argument
1482 #define DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST_SET(x)\ argument
1484 #define DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST_GET(x)\ argument
1488 #define DEV2G5_DEV_RST_CTRL_PCS_TX_RST_SET(x)\ argument
1490 #define DEV2G5_DEV_RST_CTRL_PCS_TX_RST_GET(x)\ argument
1494 #define DEV2G5_DEV_RST_CTRL_PCS_RX_RST_SET(x)\ argument
1496 #define DEV2G5_DEV_RST_CTRL_PCS_RX_RST_GET(x)\ argument
1500 #define DEV2G5_DEV_RST_CTRL_MAC_TX_RST_SET(x)\ argument
1502 #define DEV2G5_DEV_RST_CTRL_MAC_TX_RST_GET(x)\ argument
1506 #define DEV2G5_DEV_RST_CTRL_MAC_RX_RST_SET(x)\ argument
1508 #define DEV2G5_DEV_RST_CTRL_MAC_RX_RST_GET(x)\ argument
1515 #define DEV2G5_MAC_ENA_CFG_RX_ENA_SET(x)\ argument
1517 #define DEV2G5_MAC_ENA_CFG_RX_ENA_GET(x)\ argument
1521 #define DEV2G5_MAC_ENA_CFG_TX_ENA_SET(x)\ argument
1523 #define DEV2G5_MAC_ENA_CFG_TX_ENA_GET(x)\ argument
1530 #define DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA_SET(x)\ argument
1532 #define DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA_GET(x)\ argument
1536 #define DEV2G5_MAC_MODE_CFG_GIGA_MODE_ENA_SET(x)\ argument
1538 #define DEV2G5_MAC_MODE_CFG_GIGA_MODE_ENA_GET(x)\ argument
1542 #define DEV2G5_MAC_MODE_CFG_FDX_ENA_SET(x)\ argument
1544 #define DEV2G5_MAC_MODE_CFG_FDX_ENA_GET(x)\ argument
1551 #define DEV2G5_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\ argument
1553 #define DEV2G5_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\ argument
1560 #define DEV2G5_MAC_TAGS_CFG_TAG_ID_SET(x)\ argument
1562 #define DEV2G5_MAC_TAGS_CFG_TAG_ID_GET(x)\ argument
1566 #define DEV2G5_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA_SET(x)\ argument
1568 #define DEV2G5_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA_GET(x)\ argument
1572 #define DEV2G5_MAC_TAGS_CFG_PB_ENA_SET(x)\ argument
1574 #define DEV2G5_MAC_TAGS_CFG_PB_ENA_GET(x)\ argument
1578 #define DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA_SET(x)\ argument
1580 #define DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA_GET(x)\ argument
1587 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID3_SET(x)\ argument
1589 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID3_GET(x)\ argument
1593 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID2_SET(x)\ argument
1595 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID2_GET(x)\ argument
1602 #define DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA_SET(x)\ argument
1604 #define DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA_GET(x)\ argument
1611 #define DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK_SET(x)\ argument
1613 #define DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK_GET(x)\ argument
1617 #define DEV2G5_MAC_IFG_CFG_TX_IFG_SET(x)\ argument
1619 #define DEV2G5_MAC_IFG_CFG_TX_IFG_GET(x)\ argument
1623 #define DEV2G5_MAC_IFG_CFG_RX_IFG2_SET(x)\ argument
1625 #define DEV2G5_MAC_IFG_CFG_RX_IFG2_GET(x)\ argument
1629 #define DEV2G5_MAC_IFG_CFG_RX_IFG1_SET(x)\ argument
1631 #define DEV2G5_MAC_IFG_CFG_RX_IFG1_GET(x)\ argument
1638 #define DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC_SET(x)\ argument
1640 #define DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC_GET(x)\ argument
1644 #define DEV2G5_MAC_HDX_CFG_SEED_SET(x)\ argument
1646 #define DEV2G5_MAC_HDX_CFG_SEED_GET(x)\ argument
1650 #define DEV2G5_MAC_HDX_CFG_SEED_LOAD_SET(x)\ argument
1652 #define DEV2G5_MAC_HDX_CFG_SEED_LOAD_GET(x)\ argument
1656 #define DEV2G5_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA_SET(x)\ argument
1658 #define DEV2G5_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA_GET(x)\ argument
1662 #define DEV2G5_MAC_HDX_CFG_LATE_COL_POS_SET(x)\ argument
1664 #define DEV2G5_MAC_HDX_CFG_LATE_COL_POS_GET(x)\ argument
1671 #define DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE_SET(x)\ argument
1673 #define DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE_GET(x)\ argument
1677 #define DEV2G5_PCS1G_CFG_AN_LINK_CTRL_ENA_SET(x)\ argument
1679 #define DEV2G5_PCS1G_CFG_AN_LINK_CTRL_ENA_GET(x)\ argument
1683 #define DEV2G5_PCS1G_CFG_PCS_ENA_SET(x)\ argument
1685 #define DEV2G5_PCS1G_CFG_PCS_ENA_GET(x)\ argument
1692 #define DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA_SET(x)\ argument
1694 #define DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA_GET(x)\ argument
1698 #define DEV2G5_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA_SET(x)\ argument
1700 #define DEV2G5_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA_GET(x)\ argument
1704 #define DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA_SET(x)\ argument
1706 #define DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA_GET(x)\ argument
1713 #define DEV2G5_PCS1G_SD_CFG_SD_SEL_SET(x)\ argument
1715 #define DEV2G5_PCS1G_SD_CFG_SD_SEL_GET(x)\ argument
1719 #define DEV2G5_PCS1G_SD_CFG_SD_POL_SET(x)\ argument
1721 #define DEV2G5_PCS1G_SD_CFG_SD_POL_GET(x)\ argument
1725 #define DEV2G5_PCS1G_SD_CFG_SD_ENA_SET(x)\ argument
1727 #define DEV2G5_PCS1G_SD_CFG_SD_ENA_GET(x)\ argument
1734 #define DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY_SET(x)\ argument
1736 #define DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY_GET(x)\ argument
1740 #define DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA_SET(x)\ argument
1742 #define DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA_GET(x)\ argument
1746 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT_SET(x)\ argument
1748 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT_GET(x)\ argument
1752 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA_SET(x)\ argument
1754 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA_GET(x)\ argument
1761 #define DEV2G5_PCS1G_LB_CFG_RA_ENA_SET(x)\ argument
1763 #define DEV2G5_PCS1G_LB_CFG_RA_ENA_GET(x)\ argument
1767 #define DEV2G5_PCS1G_LB_CFG_GMII_PHY_LB_ENA_SET(x)\ argument
1769 #define DEV2G5_PCS1G_LB_CFG_GMII_PHY_LB_ENA_GET(x)\ argument
1773 #define DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA_SET(x)\ argument
1775 #define DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA_GET(x)\ argument
1782 #define DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY_SET(x)\ argument
1784 #define DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY_GET(x)\ argument
1788 #define DEV2G5_PCS1G_ANEG_STATUS_PR_SET(x)\ argument
1790 #define DEV2G5_PCS1G_ANEG_STATUS_PR_GET(x)\ argument
1794 #define DEV2G5_PCS1G_ANEG_STATUS_PAGE_RX_STICKY_SET(x)\ argument
1796 #define DEV2G5_PCS1G_ANEG_STATUS_PAGE_RX_STICKY_GET(x)\ argument
1800 #define DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE_SET(x)\ argument
1802 #define DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE_GET(x)\ argument
1809 #define DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR_SET(x)\ argument
1811 #define DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR_GET(x)\ argument
1815 #define DEV2G5_PCS1G_LINK_STATUS_SIGNAL_DETECT_SET(x)\ argument
1817 #define DEV2G5_PCS1G_LINK_STATUS_SIGNAL_DETECT_GET(x)\ argument
1821 #define DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS_SET(x)\ argument
1823 #define DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS_GET(x)\ argument
1827 #define DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS_SET(x)\ argument
1829 #define DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS_GET(x)\ argument
1836 #define DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY_SET(x)\ argument
1838 #define DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY_GET(x)\ argument
1842 #define DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY_SET(x)\ argument
1844 #define DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY_GET(x)\ argument
1851 #define DEV2G5_PCS_FX100_CFG_SD_SEL_SET(x)\ argument
1853 #define DEV2G5_PCS_FX100_CFG_SD_SEL_GET(x)\ argument
1857 #define DEV2G5_PCS_FX100_CFG_SD_POL_SET(x)\ argument
1859 #define DEV2G5_PCS_FX100_CFG_SD_POL_GET(x)\ argument
1863 #define DEV2G5_PCS_FX100_CFG_SD_ENA_SET(x)\ argument
1865 #define DEV2G5_PCS_FX100_CFG_SD_ENA_GET(x)\ argument
1869 #define DEV2G5_PCS_FX100_CFG_LOOPBACK_ENA_SET(x)\ argument
1871 #define DEV2G5_PCS_FX100_CFG_LOOPBACK_ENA_GET(x)\ argument
1875 #define DEV2G5_PCS_FX100_CFG_SWAP_MII_ENA_SET(x)\ argument
1877 #define DEV2G5_PCS_FX100_CFG_SWAP_MII_ENA_GET(x)\ argument
1881 #define DEV2G5_PCS_FX100_CFG_RXBITSEL_SET(x)\ argument
1883 #define DEV2G5_PCS_FX100_CFG_RXBITSEL_GET(x)\ argument
1887 #define DEV2G5_PCS_FX100_CFG_SIGDET_CFG_SET(x)\ argument
1889 #define DEV2G5_PCS_FX100_CFG_SIGDET_CFG_GET(x)\ argument
1893 #define DEV2G5_PCS_FX100_CFG_LINKHYST_TM_ENA_SET(x)\ argument
1895 #define DEV2G5_PCS_FX100_CFG_LINKHYST_TM_ENA_GET(x)\ argument
1899 #define DEV2G5_PCS_FX100_CFG_LINKHYSTTIMER_SET(x)\ argument
1901 #define DEV2G5_PCS_FX100_CFG_LINKHYSTTIMER_GET(x)\ argument
1905 #define DEV2G5_PCS_FX100_CFG_UNIDIR_MODE_ENA_SET(x)\ argument
1907 #define DEV2G5_PCS_FX100_CFG_UNIDIR_MODE_ENA_GET(x)\ argument
1911 #define DEV2G5_PCS_FX100_CFG_FEFCHK_ENA_SET(x)\ argument
1913 #define DEV2G5_PCS_FX100_CFG_FEFCHK_ENA_GET(x)\ argument
1917 #define DEV2G5_PCS_FX100_CFG_FEFGEN_ENA_SET(x)\ argument
1919 #define DEV2G5_PCS_FX100_CFG_FEFGEN_ENA_GET(x)\ argument
1923 #define DEV2G5_PCS_FX100_CFG_PCS_ENA_SET(x)\ argument
1925 #define DEV2G5_PCS_FX100_CFG_PCS_ENA_GET(x)\ argument
1932 #define DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP_SET(x)\ argument
1934 #define DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP_GET(x)\ argument
1938 #define DEV2G5_PCS_FX100_STATUS_PCS_ERROR_STICKY_SET(x)\ argument
1940 #define DEV2G5_PCS_FX100_STATUS_PCS_ERROR_STICKY_GET(x)\ argument
1944 #define DEV2G5_PCS_FX100_STATUS_FEF_FOUND_STICKY_SET(x)\ argument
1946 #define DEV2G5_PCS_FX100_STATUS_FEF_FOUND_STICKY_GET(x)\ argument
1950 #define DEV2G5_PCS_FX100_STATUS_SSD_ERROR_STICKY_SET(x)\ argument
1952 #define DEV2G5_PCS_FX100_STATUS_SSD_ERROR_STICKY_GET(x)\ argument
1956 #define DEV2G5_PCS_FX100_STATUS_SYNC_LOST_STICKY_SET(x)\ argument
1958 #define DEV2G5_PCS_FX100_STATUS_SYNC_LOST_STICKY_GET(x)\ argument
1962 #define DEV2G5_PCS_FX100_STATUS_FEF_STATUS_SET(x)\ argument
1964 #define DEV2G5_PCS_FX100_STATUS_FEF_STATUS_GET(x)\ argument
1968 #define DEV2G5_PCS_FX100_STATUS_SIGNAL_DETECT_SET(x)\ argument
1970 #define DEV2G5_PCS_FX100_STATUS_SIGNAL_DETECT_GET(x)\ argument
1974 #define DEV2G5_PCS_FX100_STATUS_SYNC_STATUS_SET(x)\ argument
1976 #define DEV2G5_PCS_FX100_STATUS_SYNC_STATUS_GET(x)\ argument
1983 #define DEV5G_MAC_ENA_CFG_RX_ENA_SET(x)\ argument
1985 #define DEV5G_MAC_ENA_CFG_RX_ENA_GET(x)\ argument
1989 #define DEV5G_MAC_ENA_CFG_TX_ENA_SET(x)\ argument
1991 #define DEV5G_MAC_ENA_CFG_TX_ENA_GET(x)\ argument
1998 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_SET(x)\ argument
2000 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_GET(x)\ argument
2004 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\ argument
2006 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\ argument
2013 #define DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_SET(x)\ argument
2015 #define DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_GET(x)\ argument
2019 #define DEV5G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_SET(x)\ argument
2021 #define DEV5G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_GET(x)\ argument
2025 #define DEV5G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_SET(x)\ argument
2027 #define DEV5G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_GET(x)\ argument
2031 #define DEV5G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_SET(x)\ argument
2033 #define DEV5G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_GET(x)\ argument
2037 #define DEV5G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_SET(x)\ argument
2039 #define DEV5G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_GET(x)\ argument
2043 #define DEV5G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_SET(x)\ argument
2045 #define DEV5G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_GET(x)\ argument
2049 #define DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA_SET(x)\ argument
2051 #define DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA_GET(x)\ argument
2297 #define DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_SET(x)\ argument
2299 #define DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_GET(x)\ argument
2309 #define DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_SET(x)\ argument
2311 #define DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_GET(x)\ argument
2321 #define DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_SET(x)\ argument
2323 #define DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_GET(x)\ argument
2333 #define DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_SET(x)\ argument
2335 #define DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_GET(x)\ argument
2345 #define DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_SET(x)\ argument
2347 #define DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_GET(x)\ argument
2357 #define DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_SET(x)\ argument
2359 #define DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_GET(x)\ argument
2369 #define DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_SET(x)\ argument
2371 #define DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_GET(x)\ argument
2381 #define DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_SET(x)\ argument
2383 #define DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_GET(x)\ argument
2390 #define DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA_SET(x)\ argument
2392 #define DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA_GET(x)\ argument
2396 #define DEV5G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_SET(x)\ argument
2398 #define DEV5G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_GET(x)\ argument
2402 #define DEV5G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_SET(x)\ argument
2404 #define DEV5G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_GET(x)\ argument
2408 #define DEV5G_DEV_RST_CTRL_SERDES_SPEED_SEL_SET(x)\ argument
2410 #define DEV5G_DEV_RST_CTRL_SERDES_SPEED_SEL_GET(x)\ argument
2414 #define DEV5G_DEV_RST_CTRL_SPEED_SEL_SET(x)\ argument
2416 #define DEV5G_DEV_RST_CTRL_SPEED_SEL_GET(x)\ argument
2420 #define DEV5G_DEV_RST_CTRL_PCS_TX_RST_SET(x)\ argument
2422 #define DEV5G_DEV_RST_CTRL_PCS_TX_RST_GET(x)\ argument
2426 #define DEV5G_DEV_RST_CTRL_PCS_RX_RST_SET(x)\ argument
2428 #define DEV5G_DEV_RST_CTRL_PCS_RX_RST_GET(x)\ argument
2432 #define DEV5G_DEV_RST_CTRL_MAC_TX_RST_SET(x)\ argument
2434 #define DEV5G_DEV_RST_CTRL_MAC_TX_RST_GET(x)\ argument
2438 #define DEV5G_DEV_RST_CTRL_MAC_RX_RST_SET(x)\ argument
2440 #define DEV5G_DEV_RST_CTRL_MAC_RX_RST_GET(x)\ argument
2447 #define DSM_RAM_INIT_RAM_INIT_SET(x)\ argument
2449 #define DSM_RAM_INIT_RAM_INIT_GET(x)\ argument
2453 #define DSM_RAM_INIT_RAM_CFG_HOOK_SET(x)\ argument
2455 #define DSM_RAM_INIT_RAM_CFG_HOOK_GET(x)\ argument
2462 #define DSM_BUF_CFG_CSC_STAT_DIS_SET(x)\ argument
2464 #define DSM_BUF_CFG_CSC_STAT_DIS_GET(x)\ argument
2468 #define DSM_BUF_CFG_AGING_ENA_SET(x)\ argument
2470 #define DSM_BUF_CFG_AGING_ENA_GET(x)\ argument
2474 #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS_SET(x)\ argument
2476 #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS_GET(x)\ argument
2480 #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT_SET(x)\ argument
2482 #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT_GET(x)\ argument
2489 #define DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA_SET(x)\ argument
2491 #define DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA_GET(x)\ argument
2495 #define DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA_SET(x)\ argument
2497 #define DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA_GET(x)\ argument
2501 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM_SET(x)\ argument
2503 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM_GET(x)\ argument
2507 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR_SET(x)\ argument
2509 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR_GET(x)\ argument
2516 #define DSM_RX_PAUSE_CFG_RX_PAUSE_EN_SET(x)\ argument
2518 #define DSM_RX_PAUSE_CFG_RX_PAUSE_EN_GET(x)\ argument
2522 #define DSM_RX_PAUSE_CFG_FC_OBEY_LOCAL_SET(x)\ argument
2524 #define DSM_RX_PAUSE_CFG_FC_OBEY_LOCAL_GET(x)\ argument
2531 #define DSM_MAC_CFG_TX_PAUSE_VAL_SET(x)\ argument
2533 #define DSM_MAC_CFG_TX_PAUSE_VAL_GET(x)\ argument
2537 #define DSM_MAC_CFG_HDX_BACKPREASSURE_SET(x)\ argument
2539 #define DSM_MAC_CFG_HDX_BACKPREASSURE_GET(x)\ argument
2543 #define DSM_MAC_CFG_SEND_PAUSE_FRM_TWICE_SET(x)\ argument
2545 #define DSM_MAC_CFG_SEND_PAUSE_FRM_TWICE_GET(x)\ argument
2549 #define DSM_MAC_CFG_TX_PAUSE_XON_XOFF_SET(x)\ argument
2551 #define DSM_MAC_CFG_TX_PAUSE_XON_XOFF_GET(x)\ argument
2558 #define DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH_SET(x)\ argument
2560 #define DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH_GET(x)\ argument
2567 #define DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW_SET(x)\ argument
2569 #define DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW_GET(x)\ argument
2576 #define DSM_TAXI_CAL_CFG_CAL_IDX_SET(x)\ argument
2578 #define DSM_TAXI_CAL_CFG_CAL_IDX_GET(x)\ argument
2582 #define DSM_TAXI_CAL_CFG_CAL_CUR_LEN_SET(x)\ argument
2584 #define DSM_TAXI_CAL_CFG_CAL_CUR_LEN_GET(x)\ argument
2588 #define DSM_TAXI_CAL_CFG_CAL_CUR_VAL_SET(x)\ argument
2590 #define DSM_TAXI_CAL_CFG_CAL_CUR_VAL_GET(x)\ argument
2594 #define DSM_TAXI_CAL_CFG_CAL_PGM_VAL_SET(x)\ argument
2596 #define DSM_TAXI_CAL_CFG_CAL_PGM_VAL_GET(x)\ argument
2600 #define DSM_TAXI_CAL_CFG_CAL_PGM_ENA_SET(x)\ argument
2602 #define DSM_TAXI_CAL_CFG_CAL_PGM_ENA_GET(x)\ argument
2609 #define EACL_POL_EACL_CFG_EACL_CNT_MARKED_AS_DROPPED_SET(x)\ argument
2611 #define EACL_POL_EACL_CFG_EACL_CNT_MARKED_AS_DROPPED_GET(x)\ argument
2615 #define EACL_POL_EACL_CFG_EACL_ALLOW_FP_COPY_SET(x)\ argument
2617 #define EACL_POL_EACL_CFG_EACL_ALLOW_FP_COPY_GET(x)\ argument
2621 #define EACL_POL_EACL_CFG_EACL_ALLOW_CPU_COPY_SET(x)\ argument
2623 #define EACL_POL_EACL_CFG_EACL_ALLOW_CPU_COPY_GET(x)\ argument
2627 #define EACL_POL_EACL_CFG_EACL_FORCE_CLOSE_SET(x)\ argument
2629 #define EACL_POL_EACL_CFG_EACL_FORCE_CLOSE_GET(x)\ argument
2633 #define EACL_POL_EACL_CFG_EACL_FORCE_OPEN_SET(x)\ argument
2635 #define EACL_POL_EACL_CFG_EACL_FORCE_OPEN_GET(x)\ argument
2639 #define EACL_POL_EACL_CFG_EACL_FORCE_INIT_SET(x)\ argument
2641 #define EACL_POL_EACL_CFG_EACL_FORCE_INIT_GET(x)\ argument
2648 #define EACL_RAM_INIT_RAM_INIT_SET(x)\ argument
2650 #define EACL_RAM_INIT_RAM_INIT_GET(x)\ argument
2654 #define EACL_RAM_INIT_RAM_CFG_HOOK_SET(x)\ argument
2656 #define EACL_RAM_INIT_RAM_CFG_HOOK_GET(x)\ argument
2663 #define FDMA_CH_ACTIVATE_CH_ACTIVATE_SET(x)\ argument
2665 #define FDMA_CH_ACTIVATE_CH_ACTIVATE_GET(x)\ argument
2672 #define FDMA_CH_RELOAD_CH_RELOAD_SET(x)\ argument
2674 #define FDMA_CH_RELOAD_CH_RELOAD_GET(x)\ argument
2681 #define FDMA_CH_DISABLE_CH_DISABLE_SET(x)\ argument
2683 #define FDMA_CH_DISABLE_CH_DISABLE_GET(x)\ argument
2702 #define FDMA_CH_CFG_CH_XTR_STATUS_MODE_SET(x)\ argument
2704 #define FDMA_CH_CFG_CH_XTR_STATUS_MODE_GET(x)\ argument
2708 #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_SET(x)\ argument
2710 #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_GET(x)\ argument
2714 #define FDMA_CH_CFG_CH_INJ_PORT_SET(x)\ argument
2716 #define FDMA_CH_CFG_CH_INJ_PORT_GET(x)\ argument
2720 #define FDMA_CH_CFG_CH_DCB_DB_CNT_SET(x)\ argument
2722 #define FDMA_CH_CFG_CH_DCB_DB_CNT_GET(x)\ argument
2726 #define FDMA_CH_CFG_CH_MEM_SET(x)\ argument
2728 #define FDMA_CH_CFG_CH_MEM_GET(x)\ argument
2735 #define FDMA_CH_TRANSLATE_OFFSET_SET(x)\ argument
2737 #define FDMA_CH_TRANSLATE_OFFSET_GET(x)\ argument
2744 #define FDMA_XTR_CFG_XTR_FIFO_WM_SET(x)\ argument
2746 #define FDMA_XTR_CFG_XTR_FIFO_WM_GET(x)\ argument
2750 #define FDMA_XTR_CFG_XTR_ARB_SAT_SET(x)\ argument
2752 #define FDMA_XTR_CFG_XTR_ARB_SAT_GET(x)\ argument
2759 #define FDMA_PORT_CTRL_INJ_STOP_SET(x)\ argument
2761 #define FDMA_PORT_CTRL_INJ_STOP_GET(x)\ argument
2765 #define FDMA_PORT_CTRL_INJ_STOP_FORCE_SET(x)\ argument
2767 #define FDMA_PORT_CTRL_INJ_STOP_FORCE_GET(x)\ argument
2771 #define FDMA_PORT_CTRL_XTR_STOP_SET(x)\ argument
2773 #define FDMA_PORT_CTRL_XTR_STOP_GET(x)\ argument
2777 #define FDMA_PORT_CTRL_XTR_BUF_IS_EMPTY_SET(x)\ argument
2779 #define FDMA_PORT_CTRL_XTR_BUF_IS_EMPTY_GET(x)\ argument
2783 #define FDMA_PORT_CTRL_XTR_BUF_RST_SET(x)\ argument
2785 #define FDMA_PORT_CTRL_XTR_BUF_RST_GET(x)\ argument
2792 #define FDMA_INTR_DCB_INTR_DCB_SET(x)\ argument
2794 #define FDMA_INTR_DCB_INTR_DCB_GET(x)\ argument
2801 #define FDMA_INTR_DCB_ENA_INTR_DCB_ENA_SET(x)\ argument
2803 #define FDMA_INTR_DCB_ENA_INTR_DCB_ENA_GET(x)\ argument
2810 #define FDMA_INTR_DB_INTR_DB_SET(x)\ argument
2812 #define FDMA_INTR_DB_INTR_DB_GET(x)\ argument
2819 #define FDMA_INTR_DB_ENA_INTR_DB_ENA_SET(x)\ argument
2821 #define FDMA_INTR_DB_ENA_INTR_DB_ENA_GET(x)\ argument
2828 #define FDMA_INTR_ERR_INTR_PORT_ERR_SET(x)\ argument
2830 #define FDMA_INTR_ERR_INTR_PORT_ERR_GET(x)\ argument
2834 #define FDMA_INTR_ERR_INTR_CH_ERR_SET(x)\ argument
2836 #define FDMA_INTR_ERR_INTR_CH_ERR_GET(x)\ argument
2843 #define FDMA_ERRORS_ERR_XTR_WR_SET(x)\ argument
2845 #define FDMA_ERRORS_ERR_XTR_WR_GET(x)\ argument
2849 #define FDMA_ERRORS_ERR_XTR_OVF_SET(x)\ argument
2851 #define FDMA_ERRORS_ERR_XTR_OVF_GET(x)\ argument
2855 #define FDMA_ERRORS_ERR_XTR_TAXI32_OVF_SET(x)\ argument
2857 #define FDMA_ERRORS_ERR_XTR_TAXI32_OVF_GET(x)\ argument
2861 #define FDMA_ERRORS_ERR_DCB_XTR_DATAL_SET(x)\ argument
2863 #define FDMA_ERRORS_ERR_DCB_XTR_DATAL_GET(x)\ argument
2867 #define FDMA_ERRORS_ERR_DCB_RD_SET(x)\ argument
2869 #define FDMA_ERRORS_ERR_DCB_RD_GET(x)\ argument
2873 #define FDMA_ERRORS_ERR_INJ_RD_SET(x)\ argument
2875 #define FDMA_ERRORS_ERR_INJ_RD_GET(x)\ argument
2879 #define FDMA_ERRORS_ERR_INJ_OUT_OF_SYNC_SET(x)\ argument
2881 #define FDMA_ERRORS_ERR_INJ_OUT_OF_SYNC_GET(x)\ argument
2885 #define FDMA_ERRORS_ERR_CH_WR_SET(x)\ argument
2887 #define FDMA_ERRORS_ERR_CH_WR_GET(x)\ argument
2894 #define FDMA_ERRORS_2_ERR_XTR_FRAG_SET(x)\ argument
2896 #define FDMA_ERRORS_2_ERR_XTR_FRAG_GET(x)\ argument
2903 #define FDMA_CTRL_NRESET_SET(x)\ argument
2905 #define FDMA_CTRL_NRESET_GET(x)\ argument
2912 #define GCB_CHIP_ID_REV_ID_SET(x)\ argument
2914 #define GCB_CHIP_ID_REV_ID_GET(x)\ argument
2918 #define GCB_CHIP_ID_PART_ID_SET(x)\ argument
2920 #define GCB_CHIP_ID_PART_ID_GET(x)\ argument
2924 #define GCB_CHIP_ID_MFG_ID_SET(x)\ argument
2926 #define GCB_CHIP_ID_MFG_ID_GET(x)\ argument
2930 #define GCB_CHIP_ID_ONE_SET(x)\ argument
2932 #define GCB_CHIP_ID_ONE_GET(x)\ argument
2939 #define GCB_SOFT_RST_SOFT_NON_CFG_RST_SET(x)\ argument
2941 #define GCB_SOFT_RST_SOFT_NON_CFG_RST_GET(x)\ argument
2945 #define GCB_SOFT_RST_SOFT_SWC_RST_SET(x)\ argument
2947 #define GCB_SOFT_RST_SOFT_SWC_RST_GET(x)\ argument
2951 #define GCB_SOFT_RST_SOFT_CHIP_RST_SET(x)\ argument
2953 #define GCB_SOFT_RST_SOFT_CHIP_RST_GET(x)\ argument
2960 #define GCB_HW_SGPIO_SD_CFG_SD_HIGH_ENA_SET(x)\ argument
2962 #define GCB_HW_SGPIO_SD_CFG_SD_HIGH_ENA_GET(x)\ argument
2966 #define GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL_SET(x)\ argument
2968 #define GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL_GET(x)\ argument
2975 #define GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL_SET(x)\ argument
2977 #define GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL_GET(x)\ argument
2984 #define GCB_SIO_CLOCK_SIO_CLK_FREQ_SET(x)\ argument
2986 #define GCB_SIO_CLOCK_SIO_CLK_FREQ_GET(x)\ argument
2990 #define GCB_SIO_CLOCK_SYS_CLK_PERIOD_SET(x)\ argument
2992 #define GCB_SIO_CLOCK_SYS_CLK_PERIOD_GET(x)\ argument
2999 #define HSCH_SYS_CLK_PER_SYS_CLK_PER_100PS_SET(x)\ argument
3001 #define HSCH_SYS_CLK_PER_SYS_CLK_PER_100PS_GET(x)\ argument
3008 #define HSCH_FLUSH_CTRL_FLUSH_ENA_SET(x)\ argument
3010 #define HSCH_FLUSH_CTRL_FLUSH_ENA_GET(x)\ argument
3014 #define HSCH_FLUSH_CTRL_FLUSH_SRC_SET(x)\ argument
3016 #define HSCH_FLUSH_CTRL_FLUSH_SRC_GET(x)\ argument
3020 #define HSCH_FLUSH_CTRL_FLUSH_DST_SET(x)\ argument
3022 #define HSCH_FLUSH_CTRL_FLUSH_DST_GET(x)\ argument
3026 #define HSCH_FLUSH_CTRL_FLUSH_PORT_SET(x)\ argument
3028 #define HSCH_FLUSH_CTRL_FLUSH_PORT_GET(x)\ argument
3032 #define HSCH_FLUSH_CTRL_FLUSH_QUEUE_SET(x)\ argument
3034 #define HSCH_FLUSH_CTRL_FLUSH_QUEUE_GET(x)\ argument
3038 #define HSCH_FLUSH_CTRL_FLUSH_SE_SET(x)\ argument
3040 #define HSCH_FLUSH_CTRL_FLUSH_SE_GET(x)\ argument
3044 #define HSCH_FLUSH_CTRL_FLUSH_HIER_SET(x)\ argument
3046 #define HSCH_FLUSH_CTRL_FLUSH_HIER_GET(x)\ argument
3053 #define HSCH_PORT_MODE_DEQUEUE_DIS_SET(x)\ argument
3055 #define HSCH_PORT_MODE_DEQUEUE_DIS_GET(x)\ argument
3059 #define HSCH_PORT_MODE_AGE_DIS_SET(x)\ argument
3061 #define HSCH_PORT_MODE_AGE_DIS_GET(x)\ argument
3065 #define HSCH_PORT_MODE_TRUNC_ENA_SET(x)\ argument
3067 #define HSCH_PORT_MODE_TRUNC_ENA_GET(x)\ argument
3071 #define HSCH_PORT_MODE_EIR_REMARK_ENA_SET(x)\ argument
3073 #define HSCH_PORT_MODE_EIR_REMARK_ENA_GET(x)\ argument
3077 #define HSCH_PORT_MODE_CPU_PRIO_MODE_SET(x)\ argument
3079 #define HSCH_PORT_MODE_CPU_PRIO_MODE_GET(x)\ argument
3086 #define HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA_SET(x)\ argument
3088 #define HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA_GET(x)\ argument
3095 #define HSCH_RESET_CFG_CORE_ENA_SET(x)\ argument
3097 #define HSCH_RESET_CFG_CORE_ENA_GET(x)\ argument
3104 #define HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY_SET(x)\ argument
3106 #define HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY_GET(x)\ argument
3113 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_COL_SET(x)\ argument
3115 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_COL_GET(x)\ argument
3119 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_TYPE_SET(x)\ argument
3121 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_TYPE_GET(x)\ argument
3125 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW_SET(x)\ argument
3127 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW_GET(x)\ argument
3131 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD_SET(x)\ argument
3133 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD_GET(x)\ argument
3137 #define LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT_SET(x)\ argument
3139 #define LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT_GET(x)\ argument
3146 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_FID_SET(x)\ argument
3148 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_FID_GET(x)\ argument
3152 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_MAC_MSB_SET(x)\ argument
3154 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_MAC_MSB_GET(x)\ argument
3164 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_SRC_KILL_FWD_SET(x)\ argument
3166 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_SRC_KILL_FWD_GET(x)\ argument
3170 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_NXT_LRN_ALL_SET(x)\ argument
3172 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_NXT_LRN_ALL_GET(x)\ argument
3176 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU_SET(x)\ argument
3178 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU_GET(x)\ argument
3182 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY_SET(x)\ argument
3184 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY_GET(x)\ argument
3188 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLAN_IGNORE_SET(x)\ argument
3190 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLAN_IGNORE_GET(x)\ argument
3194 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_MIRROR_SET(x)\ argument
3196 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_MIRROR_GET(x)\ argument
3200 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_FLAG_SET(x)\ argument
3202 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_FLAG_GET(x)\ argument
3206 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_INTERVAL_SET(x)\ argument
3208 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_INTERVAL_GET(x)\ argument
3212 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED_SET(x)\ argument
3214 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED_GET(x)\ argument
3218 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD_SET(x)\ argument
3220 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD_GET(x)\ argument
3224 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE_SET(x)\ argument
3226 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE_GET(x)\ argument
3230 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_SET(x)\ argument
3232 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_GET(x)\ argument
3239 #define LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX_SET(x)\ argument
3241 #define LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX_GET(x)\ argument
3248 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FLAG_UPDATE_SEL_SET(x)\ argument
3250 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FLAG_UPDATE_SEL_GET(x)\ argument
3254 #define LRN_SCAN_NEXT_CFG_SCAN_NXT_LRN_ALL_UPDATE_SEL_SET(x)\ argument
3256 #define LRN_SCAN_NEXT_CFG_SCAN_NXT_LRN_ALL_UPDATE_SEL_GET(x)\ argument
3260 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FILTER_SEL_SET(x)\ argument
3262 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FILTER_SEL_GET(x)\ argument
3266 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_MOVE_FOUND_ENA_SET(x)\ argument
3268 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_MOVE_FOUND_ENA_GET(x)\ argument
3272 #define LRN_SCAN_NEXT_CFG_NXT_LRN_ALL_FILTER_ENA_SET(x)\ argument
3274 #define LRN_SCAN_NEXT_CFG_NXT_LRN_ALL_FILTER_ENA_GET(x)\ argument
3278 #define LRN_SCAN_NEXT_CFG_SCAN_USE_PORT_FILTER_ENA_SET(x)\ argument
3280 #define LRN_SCAN_NEXT_CFG_SCAN_USE_PORT_FILTER_ENA_GET(x)\ argument
3284 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_REMOVE_FOUND_ENA_SET(x)\ argument
3286 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_REMOVE_FOUND_ENA_GET(x)\ argument
3290 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA_SET(x)\ argument
3292 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA_GET(x)\ argument
3296 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_INC_AGE_BITS_ENA_SET(x)\ argument
3298 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_INC_AGE_BITS_ENA_GET(x)\ argument
3302 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_AGED_ONLY_ENA_SET(x)\ argument
3304 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_AGED_ONLY_ENA_GET(x)\ argument
3308 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA_SET(x)\ argument
3310 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA_GET(x)\ argument
3314 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_INTERVAL_MASK_SET(x)\ argument
3316 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_INTERVAL_MASK_GET(x)\ argument
3320 #define LRN_SCAN_NEXT_CFG_ISDX_LIMIT_IDX_FILTER_ENA_SET(x)\ argument
3322 #define LRN_SCAN_NEXT_CFG_ISDX_LIMIT_IDX_FILTER_ENA_GET(x)\ argument
3326 #define LRN_SCAN_NEXT_CFG_FID_FILTER_ENA_SET(x)\ argument
3328 #define LRN_SCAN_NEXT_CFG_FID_FILTER_ENA_GET(x)\ argument
3332 #define LRN_SCAN_NEXT_CFG_ADDR_FILTER_ENA_SET(x)\ argument
3334 #define LRN_SCAN_NEXT_CFG_ADDR_FILTER_ENA_GET(x)\ argument
3341 #define LRN_SCAN_NEXT_CFG_1_PORT_MOVE_NEW_ADDR_SET(x)\ argument
3343 #define LRN_SCAN_NEXT_CFG_1_PORT_MOVE_NEW_ADDR_GET(x)\ argument
3347 #define LRN_SCAN_NEXT_CFG_1_SCAN_ENTRY_ADDR_MASK_SET(x)\ argument
3349 #define LRN_SCAN_NEXT_CFG_1_SCAN_ENTRY_ADDR_MASK_GET(x)\ argument
3356 #define LRN_AUTOAGE_CFG_UNIT_SIZE_SET(x)\ argument
3358 #define LRN_AUTOAGE_CFG_UNIT_SIZE_GET(x)\ argument
3362 #define LRN_AUTOAGE_CFG_PERIOD_VAL_SET(x)\ argument
3364 #define LRN_AUTOAGE_CFG_PERIOD_VAL_GET(x)\ argument
3371 #define LRN_AUTOAGE_CFG_1_PAUSE_AUTO_AGE_ENA_SET(x)\ argument
3373 #define LRN_AUTOAGE_CFG_1_PAUSE_AUTO_AGE_ENA_GET(x)\ argument
3377 #define LRN_AUTOAGE_CFG_1_CELLS_BETWEEN_ENTRY_SCAN_SET(x)\ argument
3379 #define LRN_AUTOAGE_CFG_1_CELLS_BETWEEN_ENTRY_SCAN_GET(x)\ argument
3383 #define LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS_SET(x)\ argument
3385 #define LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS_GET(x)\ argument
3389 #define LRN_AUTOAGE_CFG_1_USE_PORT_FILTER_ENA_SET(x)\ argument
3391 #define LRN_AUTOAGE_CFG_1_USE_PORT_FILTER_ENA_GET(x)\ argument
3395 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_SHOT_SET(x)\ argument
3397 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_SHOT_GET(x)\ argument
3401 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_STOP_SHOT_SET(x)\ argument
3403 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_STOP_SHOT_GET(x)\ argument
3407 #define LRN_AUTOAGE_CFG_1_FORCE_IDLE_ENA_SET(x)\ argument
3409 #define LRN_AUTOAGE_CFG_1_FORCE_IDLE_ENA_GET(x)\ argument
3416 #define LRN_AUTOAGE_CFG_2_NEXT_ROW_SET(x)\ argument
3418 #define LRN_AUTOAGE_CFG_2_NEXT_ROW_GET(x)\ argument
3422 #define LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS_SET(x)\ argument
3424 #define LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS_GET(x)\ argument
3431 #define PCEP_RCTRL_2_OUT_0_MSG_CODE_SET(x)\ argument
3433 #define PCEP_RCTRL_2_OUT_0_MSG_CODE_GET(x)\ argument
3437 #define PCEP_RCTRL_2_OUT_0_TAG_SET(x)\ argument
3439 #define PCEP_RCTRL_2_OUT_0_TAG_GET(x)\ argument
3443 #define PCEP_RCTRL_2_OUT_0_TAG_SUBSTITUTE_EN_SET(x)\ argument
3445 #define PCEP_RCTRL_2_OUT_0_TAG_SUBSTITUTE_EN_GET(x)\ argument
3449 #define PCEP_RCTRL_2_OUT_0_FUNC_BYPASS_SET(x)\ argument
3451 #define PCEP_RCTRL_2_OUT_0_FUNC_BYPASS_GET(x)\ argument
3455 #define PCEP_RCTRL_2_OUT_0_SNP_SET(x)\ argument
3457 #define PCEP_RCTRL_2_OUT_0_SNP_GET(x)\ argument
3461 #define PCEP_RCTRL_2_OUT_0_INHIBIT_PAYLOAD_SET(x)\ argument
3463 #define PCEP_RCTRL_2_OUT_0_INHIBIT_PAYLOAD_GET(x)\ argument
3467 #define PCEP_RCTRL_2_OUT_0_HEADER_SUBSTITUTE_EN_SET(x)\ argument
3469 #define PCEP_RCTRL_2_OUT_0_HEADER_SUBSTITUTE_EN_GET(x)\ argument
3473 #define PCEP_RCTRL_2_OUT_0_CFG_SHIFT_MODE_SET(x)\ argument
3475 #define PCEP_RCTRL_2_OUT_0_CFG_SHIFT_MODE_GET(x)\ argument
3479 #define PCEP_RCTRL_2_OUT_0_INVERT_MODE_SET(x)\ argument
3481 #define PCEP_RCTRL_2_OUT_0_INVERT_MODE_GET(x)\ argument
3485 #define PCEP_RCTRL_2_OUT_0_REGION_EN_SET(x)\ argument
3487 #define PCEP_RCTRL_2_OUT_0_REGION_EN_GET(x)\ argument
3494 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_HW_SET(x)\ argument
3496 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_HW_GET(x)\ argument
3500 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_RW_SET(x)\ argument
3502 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_RW_GET(x)\ argument
3512 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_HW_SET(x)\ argument
3514 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_HW_GET(x)\ argument
3518 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_RW_SET(x)\ argument
3520 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_RW_GET(x)\ argument
3533 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW_SET(x)\ argument
3535 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW_GET(x)\ argument
3539 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_HW_SET(x)\ argument
3541 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_HW_GET(x)\ argument
3548 #define PCS10G_BR_PCS_CFG_PCS_ENA_SET(x)\ argument
3550 #define PCS10G_BR_PCS_CFG_PCS_ENA_GET(x)\ argument
3554 #define PCS10G_BR_PCS_CFG_PMA_LOOPBACK_ENA_SET(x)\ argument
3556 #define PCS10G_BR_PCS_CFG_PMA_LOOPBACK_ENA_GET(x)\ argument
3560 #define PCS10G_BR_PCS_CFG_SH_CNT_MAX_SET(x)\ argument
3562 #define PCS10G_BR_PCS_CFG_SH_CNT_MAX_GET(x)\ argument
3566 #define PCS10G_BR_PCS_CFG_RX_DATA_FLIP_SET(x)\ argument
3568 #define PCS10G_BR_PCS_CFG_RX_DATA_FLIP_GET(x)\ argument
3572 #define PCS10G_BR_PCS_CFG_RESYNC_ENA_SET(x)\ argument
3574 #define PCS10G_BR_PCS_CFG_RESYNC_ENA_GET(x)\ argument
3578 #define PCS10G_BR_PCS_CFG_LF_GEN_DIS_SET(x)\ argument
3580 #define PCS10G_BR_PCS_CFG_LF_GEN_DIS_GET(x)\ argument
3584 #define PCS10G_BR_PCS_CFG_RX_TEST_MODE_SET(x)\ argument
3586 #define PCS10G_BR_PCS_CFG_RX_TEST_MODE_GET(x)\ argument
3590 #define PCS10G_BR_PCS_CFG_RX_SCR_DISABLE_SET(x)\ argument
3592 #define PCS10G_BR_PCS_CFG_RX_SCR_DISABLE_GET(x)\ argument
3596 #define PCS10G_BR_PCS_CFG_TX_DATA_FLIP_SET(x)\ argument
3598 #define PCS10G_BR_PCS_CFG_TX_DATA_FLIP_GET(x)\ argument
3602 #define PCS10G_BR_PCS_CFG_AN_LINK_CTRL_ENA_SET(x)\ argument
3604 #define PCS10G_BR_PCS_CFG_AN_LINK_CTRL_ENA_GET(x)\ argument
3608 #define PCS10G_BR_PCS_CFG_TX_TEST_MODE_SET(x)\ argument
3610 #define PCS10G_BR_PCS_CFG_TX_TEST_MODE_GET(x)\ argument
3614 #define PCS10G_BR_PCS_CFG_TX_SCR_DISABLE_SET(x)\ argument
3616 #define PCS10G_BR_PCS_CFG_TX_SCR_DISABLE_GET(x)\ argument
3623 #define PCS10G_BR_PCS_SD_CFG_SD_SEL_SET(x)\ argument
3625 #define PCS10G_BR_PCS_SD_CFG_SD_SEL_GET(x)\ argument
3629 #define PCS10G_BR_PCS_SD_CFG_SD_POL_SET(x)\ argument
3631 #define PCS10G_BR_PCS_SD_CFG_SD_POL_GET(x)\ argument
3635 #define PCS10G_BR_PCS_SD_CFG_SD_ENA_SET(x)\ argument
3637 #define PCS10G_BR_PCS_SD_CFG_SD_ENA_GET(x)\ argument
3644 #define PCS25G_BR_PCS_CFG_PCS_ENA_SET(x)\ argument
3646 #define PCS25G_BR_PCS_CFG_PCS_ENA_GET(x)\ argument
3650 #define PCS25G_BR_PCS_CFG_PMA_LOOPBACK_ENA_SET(x)\ argument
3652 #define PCS25G_BR_PCS_CFG_PMA_LOOPBACK_ENA_GET(x)\ argument
3656 #define PCS25G_BR_PCS_CFG_SH_CNT_MAX_SET(x)\ argument
3658 #define PCS25G_BR_PCS_CFG_SH_CNT_MAX_GET(x)\ argument
3662 #define PCS25G_BR_PCS_CFG_RX_DATA_FLIP_SET(x)\ argument
3664 #define PCS25G_BR_PCS_CFG_RX_DATA_FLIP_GET(x)\ argument
3668 #define PCS25G_BR_PCS_CFG_RESYNC_ENA_SET(x)\ argument
3670 #define PCS25G_BR_PCS_CFG_RESYNC_ENA_GET(x)\ argument
3674 #define PCS25G_BR_PCS_CFG_LF_GEN_DIS_SET(x)\ argument
3676 #define PCS25G_BR_PCS_CFG_LF_GEN_DIS_GET(x)\ argument
3680 #define PCS25G_BR_PCS_CFG_RX_TEST_MODE_SET(x)\ argument
3682 #define PCS25G_BR_PCS_CFG_RX_TEST_MODE_GET(x)\ argument
3686 #define PCS25G_BR_PCS_CFG_RX_SCR_DISABLE_SET(x)\ argument
3688 #define PCS25G_BR_PCS_CFG_RX_SCR_DISABLE_GET(x)\ argument
3692 #define PCS25G_BR_PCS_CFG_TX_DATA_FLIP_SET(x)\ argument
3694 #define PCS25G_BR_PCS_CFG_TX_DATA_FLIP_GET(x)\ argument
3698 #define PCS25G_BR_PCS_CFG_AN_LINK_CTRL_ENA_SET(x)\ argument
3700 #define PCS25G_BR_PCS_CFG_AN_LINK_CTRL_ENA_GET(x)\ argument
3704 #define PCS25G_BR_PCS_CFG_TX_TEST_MODE_SET(x)\ argument
3706 #define PCS25G_BR_PCS_CFG_TX_TEST_MODE_GET(x)\ argument
3710 #define PCS25G_BR_PCS_CFG_TX_SCR_DISABLE_SET(x)\ argument
3712 #define PCS25G_BR_PCS_CFG_TX_SCR_DISABLE_GET(x)\ argument
3719 #define PCS25G_BR_PCS_SD_CFG_SD_SEL_SET(x)\ argument
3721 #define PCS25G_BR_PCS_SD_CFG_SD_SEL_GET(x)\ argument
3725 #define PCS25G_BR_PCS_SD_CFG_SD_POL_SET(x)\ argument
3727 #define PCS25G_BR_PCS_SD_CFG_SD_POL_GET(x)\ argument
3731 #define PCS25G_BR_PCS_SD_CFG_SD_ENA_SET(x)\ argument
3733 #define PCS25G_BR_PCS_SD_CFG_SD_ENA_GET(x)\ argument
3740 #define PCS5G_BR_PCS_CFG_PCS_ENA_SET(x)\ argument
3742 #define PCS5G_BR_PCS_CFG_PCS_ENA_GET(x)\ argument
3746 #define PCS5G_BR_PCS_CFG_PMA_LOOPBACK_ENA_SET(x)\ argument
3748 #define PCS5G_BR_PCS_CFG_PMA_LOOPBACK_ENA_GET(x)\ argument
3752 #define PCS5G_BR_PCS_CFG_SH_CNT_MAX_SET(x)\ argument
3754 #define PCS5G_BR_PCS_CFG_SH_CNT_MAX_GET(x)\ argument
3758 #define PCS5G_BR_PCS_CFG_RX_DATA_FLIP_SET(x)\ argument
3760 #define PCS5G_BR_PCS_CFG_RX_DATA_FLIP_GET(x)\ argument
3764 #define PCS5G_BR_PCS_CFG_RESYNC_ENA_SET(x)\ argument
3766 #define PCS5G_BR_PCS_CFG_RESYNC_ENA_GET(x)\ argument
3770 #define PCS5G_BR_PCS_CFG_LF_GEN_DIS_SET(x)\ argument
3772 #define PCS5G_BR_PCS_CFG_LF_GEN_DIS_GET(x)\ argument
3776 #define PCS5G_BR_PCS_CFG_RX_TEST_MODE_SET(x)\ argument
3778 #define PCS5G_BR_PCS_CFG_RX_TEST_MODE_GET(x)\ argument
3782 #define PCS5G_BR_PCS_CFG_RX_SCR_DISABLE_SET(x)\ argument
3784 #define PCS5G_BR_PCS_CFG_RX_SCR_DISABLE_GET(x)\ argument
3788 #define PCS5G_BR_PCS_CFG_TX_DATA_FLIP_SET(x)\ argument
3790 #define PCS5G_BR_PCS_CFG_TX_DATA_FLIP_GET(x)\ argument
3794 #define PCS5G_BR_PCS_CFG_AN_LINK_CTRL_ENA_SET(x)\ argument
3796 #define PCS5G_BR_PCS_CFG_AN_LINK_CTRL_ENA_GET(x)\ argument
3800 #define PCS5G_BR_PCS_CFG_TX_TEST_MODE_SET(x)\ argument
3802 #define PCS5G_BR_PCS_CFG_TX_TEST_MODE_GET(x)\ argument
3806 #define PCS5G_BR_PCS_CFG_TX_SCR_DISABLE_SET(x)\ argument
3808 #define PCS5G_BR_PCS_CFG_TX_SCR_DISABLE_GET(x)\ argument
3815 #define PCS5G_BR_PCS_SD_CFG_SD_SEL_SET(x)\ argument
3817 #define PCS5G_BR_PCS_SD_CFG_SD_SEL_GET(x)\ argument
3821 #define PCS5G_BR_PCS_SD_CFG_SD_POL_SET(x)\ argument
3823 #define PCS5G_BR_PCS_SD_CFG_SD_POL_GET(x)\ argument
3827 #define PCS5G_BR_PCS_SD_CFG_SD_ENA_SET(x)\ argument
3829 #define PCS5G_BR_PCS_SD_CFG_SD_ENA_GET(x)\ argument
3836 #define PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE_SET(x)\ argument
3838 #define PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE_GET(x)\ argument
3842 #define PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE_SET(x)\ argument
3844 #define PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE_GET(x)\ argument
3848 #define PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE_SET(x)\ argument
3850 #define PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE_GET(x)\ argument
3854 #define PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE_SET(x)\ argument
3856 #define PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE_GET(x)\ argument
3860 #define PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE_SET(x)\ argument
3862 #define PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE_GET(x)\ argument
3866 #define PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE_SET(x)\ argument
3868 #define PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE_GET(x)\ argument
3872 #define PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE_SET(x)\ argument
3874 #define PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE_GET(x)\ argument
3878 #define PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE_SET(x)\ argument
3880 #define PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE_GET(x)\ argument
3884 #define PORT_CONF_DEV5G_MODES_DEV5G_D8_MODE_SET(x)\ argument
3886 #define PORT_CONF_DEV5G_MODES_DEV5G_D8_MODE_GET(x)\ argument
3890 #define PORT_CONF_DEV5G_MODES_DEV5G_D9_MODE_SET(x)\ argument
3892 #define PORT_CONF_DEV5G_MODES_DEV5G_D9_MODE_GET(x)\ argument
3896 #define PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE_SET(x)\ argument
3898 #define PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE_GET(x)\ argument
3902 #define PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE_SET(x)\ argument
3904 #define PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE_GET(x)\ argument
3908 #define PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE_SET(x)\ argument
3910 #define PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE_GET(x)\ argument
3917 #define PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE_SET(x)\ argument
3919 #define PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE_GET(x)\ argument
3923 #define PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE_SET(x)\ argument
3925 #define PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE_GET(x)\ argument
3929 #define PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE_SET(x)\ argument
3931 #define PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE_GET(x)\ argument
3935 #define PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE_SET(x)\ argument
3937 #define PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE_GET(x)\ argument
3941 #define PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE_SET(x)\ argument
3943 #define PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE_GET(x)\ argument
3947 #define PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE_SET(x)\ argument
3949 #define PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE_GET(x)\ argument
3953 #define PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE_SET(x)\ argument
3955 #define PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE_GET(x)\ argument
3959 #define PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE_SET(x)\ argument
3961 #define PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE_GET(x)\ argument
3965 #define PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE_SET(x)\ argument
3967 #define PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE_GET(x)\ argument
3971 #define PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE_SET(x)\ argument
3973 #define PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE_GET(x)\ argument
3977 #define PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE_SET(x)\ argument
3979 #define PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE_GET(x)\ argument
3983 #define PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE_SET(x)\ argument
3985 #define PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE_GET(x)\ argument
3992 #define PORT_CONF_DEV25G_MODES_DEV25G_D56_MODE_SET(x)\ argument
3994 #define PORT_CONF_DEV25G_MODES_DEV25G_D56_MODE_GET(x)\ argument
3998 #define PORT_CONF_DEV25G_MODES_DEV25G_D57_MODE_SET(x)\ argument
4000 #define PORT_CONF_DEV25G_MODES_DEV25G_D57_MODE_GET(x)\ argument
4004 #define PORT_CONF_DEV25G_MODES_DEV25G_D58_MODE_SET(x)\ argument
4006 #define PORT_CONF_DEV25G_MODES_DEV25G_D58_MODE_GET(x)\ argument
4010 #define PORT_CONF_DEV25G_MODES_DEV25G_D59_MODE_SET(x)\ argument
4012 #define PORT_CONF_DEV25G_MODES_DEV25G_D59_MODE_GET(x)\ argument
4016 #define PORT_CONF_DEV25G_MODES_DEV25G_D60_MODE_SET(x)\ argument
4018 #define PORT_CONF_DEV25G_MODES_DEV25G_D60_MODE_GET(x)\ argument
4022 #define PORT_CONF_DEV25G_MODES_DEV25G_D61_MODE_SET(x)\ argument
4024 #define PORT_CONF_DEV25G_MODES_DEV25G_D61_MODE_GET(x)\ argument
4028 #define PORT_CONF_DEV25G_MODES_DEV25G_D62_MODE_SET(x)\ argument
4030 #define PORT_CONF_DEV25G_MODES_DEV25G_D62_MODE_GET(x)\ argument
4034 #define PORT_CONF_DEV25G_MODES_DEV25G_D63_MODE_SET(x)\ argument
4036 #define PORT_CONF_DEV25G_MODES_DEV25G_D63_MODE_GET(x)\ argument
4043 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_0_SET(x)\ argument
4045 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_0_GET(x)\ argument
4049 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_1_SET(x)\ argument
4051 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_1_GET(x)\ argument
4055 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_2_SET(x)\ argument
4057 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_2_GET(x)\ argument
4061 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_3_SET(x)\ argument
4063 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_3_GET(x)\ argument
4067 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_4_SET(x)\ argument
4069 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_4_GET(x)\ argument
4073 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_5_SET(x)\ argument
4075 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_5_GET(x)\ argument
4079 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_6_SET(x)\ argument
4081 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_6_GET(x)\ argument
4085 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_7_SET(x)\ argument
4087 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_7_GET(x)\ argument
4091 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_8_SET(x)\ argument
4093 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_8_GET(x)\ argument
4097 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_9_SET(x)\ argument
4099 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_9_GET(x)\ argument
4103 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_10_SET(x)\ argument
4105 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_10_GET(x)\ argument
4109 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_11_SET(x)\ argument
4111 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_11_GET(x)\ argument
4118 #define PORT_CONF_USGMII_CFG_BYPASS_SCRAM_SET(x)\ argument
4120 #define PORT_CONF_USGMII_CFG_BYPASS_SCRAM_GET(x)\ argument
4124 #define PORT_CONF_USGMII_CFG_BYPASS_DESCRAM_SET(x)\ argument
4126 #define PORT_CONF_USGMII_CFG_BYPASS_DESCRAM_GET(x)\ argument
4130 #define PORT_CONF_USGMII_CFG_FLIP_LANES_SET(x)\ argument
4132 #define PORT_CONF_USGMII_CFG_FLIP_LANES_GET(x)\ argument
4136 #define PORT_CONF_USGMII_CFG_SHYST_DIS_SET(x)\ argument
4138 #define PORT_CONF_USGMII_CFG_SHYST_DIS_GET(x)\ argument
4142 #define PORT_CONF_USGMII_CFG_E_DET_ENA_SET(x)\ argument
4144 #define PORT_CONF_USGMII_CFG_E_DET_ENA_GET(x)\ argument
4148 #define PORT_CONF_USGMII_CFG_USE_I1_ENA_SET(x)\ argument
4150 #define PORT_CONF_USGMII_CFG_USE_I1_ENA_GET(x)\ argument
4154 #define PORT_CONF_USGMII_CFG_QUAD_MODE_SET(x)\ argument
4156 #define PORT_CONF_USGMII_CFG_QUAD_MODE_GET(x)\ argument
4163 #define QFWD_SWITCH_PORT_MODE_PORT_ENA_SET(x)\ argument
4165 #define QFWD_SWITCH_PORT_MODE_PORT_ENA_GET(x)\ argument
4169 #define QFWD_SWITCH_PORT_MODE_FWD_URGENCY_SET(x)\ argument
4171 #define QFWD_SWITCH_PORT_MODE_FWD_URGENCY_GET(x)\ argument
4175 #define QFWD_SWITCH_PORT_MODE_YEL_RSRVD_SET(x)\ argument
4177 #define QFWD_SWITCH_PORT_MODE_YEL_RSRVD_GET(x)\ argument
4181 #define QFWD_SWITCH_PORT_MODE_INGRESS_DROP_MODE_SET(x)\ argument
4183 #define QFWD_SWITCH_PORT_MODE_INGRESS_DROP_MODE_GET(x)\ argument
4187 #define QFWD_SWITCH_PORT_MODE_IGR_NO_SHARING_SET(x)\ argument
4189 #define QFWD_SWITCH_PORT_MODE_IGR_NO_SHARING_GET(x)\ argument
4193 #define QFWD_SWITCH_PORT_MODE_EGR_NO_SHARING_SET(x)\ argument
4195 #define QFWD_SWITCH_PORT_MODE_EGR_NO_SHARING_GET(x)\ argument
4199 #define QFWD_SWITCH_PORT_MODE_EGRESS_DROP_MODE_SET(x)\ argument
4201 #define QFWD_SWITCH_PORT_MODE_EGRESS_DROP_MODE_GET(x)\ argument
4205 #define QFWD_SWITCH_PORT_MODE_EGRESS_RSRV_DIS_SET(x)\ argument
4207 #define QFWD_SWITCH_PORT_MODE_EGRESS_RSRV_DIS_GET(x)\ argument
4211 #define QFWD_SWITCH_PORT_MODE_LEARNALL_MORE_SET(x)\ argument
4213 #define QFWD_SWITCH_PORT_MODE_LEARNALL_MORE_GET(x)\ argument
4220 #define QRES_RES_CFG_WM_HIGH_SET(x)\ argument
4222 #define QRES_RES_CFG_WM_HIGH_GET(x)\ argument
4229 #define QRES_RES_STAT_MAXUSE_SET(x)\ argument
4231 #define QRES_RES_STAT_MAXUSE_GET(x)\ argument
4238 #define QRES_RES_STAT_CUR_INUSE_SET(x)\ argument
4240 #define QRES_RES_STAT_CUR_INUSE_GET(x)\ argument
4247 #define QS_XTR_GRP_CFG_MODE_SET(x)\ argument
4249 #define QS_XTR_GRP_CFG_MODE_GET(x)\ argument
4253 #define QS_XTR_GRP_CFG_STATUS_WORD_POS_SET(x)\ argument
4255 #define QS_XTR_GRP_CFG_STATUS_WORD_POS_GET(x)\ argument
4259 #define QS_XTR_GRP_CFG_BYTE_SWAP_SET(x)\ argument
4261 #define QS_XTR_GRP_CFG_BYTE_SWAP_GET(x)\ argument
4271 #define QS_XTR_FLUSH_FLUSH_SET(x)\ argument
4273 #define QS_XTR_FLUSH_FLUSH_GET(x)\ argument
4280 #define QS_XTR_DATA_PRESENT_DATA_PRESENT_SET(x)\ argument
4282 #define QS_XTR_DATA_PRESENT_DATA_PRESENT_GET(x)\ argument
4289 #define QS_INJ_GRP_CFG_MODE_SET(x)\ argument
4291 #define QS_INJ_GRP_CFG_MODE_GET(x)\ argument
4295 #define QS_INJ_GRP_CFG_BYTE_SWAP_SET(x)\ argument
4297 #define QS_INJ_GRP_CFG_BYTE_SWAP_GET(x)\ argument
4307 #define QS_INJ_CTRL_GAP_SIZE_SET(x)\ argument
4309 #define QS_INJ_CTRL_GAP_SIZE_GET(x)\ argument
4313 #define QS_INJ_CTRL_ABORT_SET(x)\ argument
4315 #define QS_INJ_CTRL_ABORT_GET(x)\ argument
4319 #define QS_INJ_CTRL_EOF_SET(x)\ argument
4321 #define QS_INJ_CTRL_EOF_GET(x)\ argument
4325 #define QS_INJ_CTRL_SOF_SET(x)\ argument
4327 #define QS_INJ_CTRL_SOF_GET(x)\ argument
4331 #define QS_INJ_CTRL_VLD_BYTES_SET(x)\ argument
4333 #define QS_INJ_CTRL_VLD_BYTES_GET(x)\ argument
4340 #define QS_INJ_STATUS_WMARK_REACHED_SET(x)\ argument
4342 #define QS_INJ_STATUS_WMARK_REACHED_GET(x)\ argument
4346 #define QS_INJ_STATUS_FIFO_RDY_SET(x)\ argument
4348 #define QS_INJ_STATUS_FIFO_RDY_GET(x)\ argument
4352 #define QS_INJ_STATUS_INJ_IN_PROGRESS_SET(x)\ argument
4354 #define QS_INJ_STATUS_INJ_IN_PROGRESS_GET(x)\ argument
4361 #define QSYS_PAUSE_CFG_PAUSE_START_SET(x)\ argument
4363 #define QSYS_PAUSE_CFG_PAUSE_START_GET(x)\ argument
4367 #define QSYS_PAUSE_CFG_PAUSE_STOP_SET(x)\ argument
4369 #define QSYS_PAUSE_CFG_PAUSE_STOP_GET(x)\ argument
4373 #define QSYS_PAUSE_CFG_PAUSE_ENA_SET(x)\ argument
4375 #define QSYS_PAUSE_CFG_PAUSE_ENA_GET(x)\ argument
4379 #define QSYS_PAUSE_CFG_AGGRESSIVE_TAILDROP_ENA_SET(x)\ argument
4381 #define QSYS_PAUSE_CFG_AGGRESSIVE_TAILDROP_ENA_GET(x)\ argument
4388 #define QSYS_ATOP_ATOP_SET(x)\ argument
4390 #define QSYS_ATOP_ATOP_GET(x)\ argument
4397 #define QSYS_FWD_PRESSURE_FWD_PRESSURE_SET(x)\ argument
4399 #define QSYS_FWD_PRESSURE_FWD_PRESSURE_GET(x)\ argument
4403 #define QSYS_FWD_PRESSURE_FWD_PRESSURE_DIS_SET(x)\ argument
4405 #define QSYS_FWD_PRESSURE_FWD_PRESSURE_DIS_GET(x)\ argument
4412 #define QSYS_ATOP_TOT_CFG_ATOP_TOT_SET(x)\ argument
4414 #define QSYS_ATOP_TOT_CFG_ATOP_TOT_GET(x)\ argument
4421 #define QSYS_CAL_AUTO_CAL_AUTO_SET(x)\ argument
4423 #define QSYS_CAL_AUTO_CAL_AUTO_GET(x)\ argument
4430 #define QSYS_CAL_CTRL_CAL_MODE_SET(x)\ argument
4432 #define QSYS_CAL_CTRL_CAL_MODE_GET(x)\ argument
4436 #define QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE_SET(x)\ argument
4438 #define QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE_GET(x)\ argument
4442 #define QSYS_CAL_CTRL_CAL_AUTO_ERROR_SET(x)\ argument
4444 #define QSYS_CAL_CTRL_CAL_AUTO_ERROR_GET(x)\ argument
4451 #define QSYS_RAM_INIT_RAM_INIT_SET(x)\ argument
4453 #define QSYS_RAM_INIT_RAM_INIT_GET(x)\ argument
4457 #define QSYS_RAM_INIT_RAM_CFG_HOOK_SET(x)\ argument
4459 #define QSYS_RAM_INIT_RAM_CFG_HOOK_GET(x)\ argument
4466 #define REW_OWN_UPSID_OWN_UPSID_SET(x)\ argument
4468 #define REW_OWN_UPSID_OWN_UPSID_GET(x)\ argument
4475 #define REW_PORT_VLAN_CFG_PORT_PCP_SET(x)\ argument
4477 #define REW_PORT_VLAN_CFG_PORT_PCP_GET(x)\ argument
4481 #define REW_PORT_VLAN_CFG_PORT_DEI_SET(x)\ argument
4483 #define REW_PORT_VLAN_CFG_PORT_DEI_GET(x)\ argument
4487 #define REW_PORT_VLAN_CFG_PORT_VID_SET(x)\ argument
4489 #define REW_PORT_VLAN_CFG_PORT_VID_GET(x)\ argument
4496 #define REW_TAG_CTRL_TAG_CFG_OBEY_WAS_TAGGED_SET(x)\ argument
4498 #define REW_TAG_CTRL_TAG_CFG_OBEY_WAS_TAGGED_GET(x)\ argument
4502 #define REW_TAG_CTRL_TAG_CFG_SET(x)\ argument
4504 #define REW_TAG_CTRL_TAG_CFG_GET(x)\ argument
4508 #define REW_TAG_CTRL_TAG_TPID_CFG_SET(x)\ argument
4510 #define REW_TAG_CTRL_TAG_TPID_CFG_GET(x)\ argument
4514 #define REW_TAG_CTRL_TAG_VID_CFG_SET(x)\ argument
4516 #define REW_TAG_CTRL_TAG_VID_CFG_GET(x)\ argument
4520 #define REW_TAG_CTRL_TAG_PCP_CFG_SET(x)\ argument
4522 #define REW_TAG_CTRL_TAG_PCP_CFG_GET(x)\ argument
4526 #define REW_TAG_CTRL_TAG_DEI_CFG_SET(x)\ argument
4528 #define REW_TAG_CTRL_TAG_DEI_CFG_GET(x)\ argument
4535 #define REW_RAM_INIT_RAM_INIT_SET(x)\ argument
4537 #define REW_RAM_INIT_RAM_INIT_GET(x)\ argument
4541 #define REW_RAM_INIT_RAM_CFG_HOOK_SET(x)\ argument
4543 #define REW_RAM_INIT_RAM_CFG_HOOK_GET(x)\ argument
4550 #define VCAP_SUPER_RAM_INIT_RAM_INIT_SET(x)\ argument
4552 #define VCAP_SUPER_RAM_INIT_RAM_INIT_GET(x)\ argument
4556 #define VCAP_SUPER_RAM_INIT_RAM_CFG_HOOK_SET(x)\ argument
4558 #define VCAP_SUPER_RAM_INIT_RAM_CFG_HOOK_GET(x)\ argument
4565 #define VOP_RAM_INIT_RAM_INIT_SET(x)\ argument
4567 #define VOP_RAM_INIT_RAM_INIT_GET(x)\ argument
4571 #define VOP_RAM_INIT_RAM_CFG_HOOK_SET(x)\ argument
4573 #define VOP_RAM_INIT_RAM_CFG_HOOK_GET(x)\ argument
4580 #define XQS_STAT_CFG_STAT_CLEAR_SHOT_SET(x)\ argument
4582 #define XQS_STAT_CFG_STAT_CLEAR_SHOT_GET(x)\ argument
4586 #define XQS_STAT_CFG_STAT_VIEW_SET(x)\ argument
4588 #define XQS_STAT_CFG_STAT_VIEW_GET(x)\ argument
4592 #define XQS_STAT_CFG_STAT_SRV_PKT_ONLY_SET(x)\ argument
4594 #define XQS_STAT_CFG_STAT_SRV_PKT_ONLY_GET(x)\ argument
4598 #define XQS_STAT_CFG_STAT_WRAP_DIS_SET(x)\ argument
4600 #define XQS_STAT_CFG_STAT_WRAP_DIS_GET(x)\ argument
4607 #define XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP_SET(x)\ argument
4609 #define XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP_GET(x)\ argument
4616 #define XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP_SET(x)\ argument
4618 #define XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP_GET(x)\ argument
4625 #define XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP_SET(x)\ argument
4627 #define XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP_GET(x)\ argument
4634 #define XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM_SET(x)\ argument
4636 #define XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM_GET(x)\ argument