Lines Matching refs:writeq
40 writeq(val64, &vp_reg->rxmac_vcfg0); in vxge_hw_vpath_set_zero_rx_frm_len()
172 writeq(*data0, &vp_reg->rts_access_steer_data0); in vxge_hw_vpath_fw_api()
173 writeq(*data1, &vp_reg->rts_access_steer_data1); in vxge_hw_vpath_fw_api()
529 writeq(VXGE_HW_SWAPPER_READ_BYTE_SWAP_ENABLE, in __vxge_hw_legacy_swapper_set()
531 writeq(VXGE_HW_SWAPPER_READ_BIT_FLAP_ENABLE, in __vxge_hw_legacy_swapper_set()
533 writeq(VXGE_HW_SWAPPER_WRITE_BYTE_SWAP_ENABLE, in __vxge_hw_legacy_swapper_set()
535 writeq(VXGE_HW_SWAPPER_WRITE_BIT_FLAP_ENABLE, in __vxge_hw_legacy_swapper_set()
540 writeq(VXGE_HW_SWAPPER_READ_BYTE_SWAP_ENABLE, in __vxge_hw_legacy_swapper_set()
542 writeq(VXGE_HW_SWAPPER_WRITE_BYTE_SWAP_ENABLE, in __vxge_hw_legacy_swapper_set()
547 writeq(VXGE_HW_SWAPPER_READ_BIT_FLAP_ENABLE, in __vxge_hw_legacy_swapper_set()
549 writeq(VXGE_HW_SWAPPER_WRITE_BIT_FLAP_ENABLE, in __vxge_hw_legacy_swapper_set()
1051 writeq(0, &mrpcim_reg->xgmac_gen_fw_memo_mask); in vxge_hw_device_hw_info_get()
1971 writeq(val64, &hldev->mrpcim_reg->rxmac_pause_cfg_port[port]); in vxge_hw_device_setpause_data()
3064 writeq(val64, &vpath_reg->vpath_general_cfg1); in __vxge_hw_vpath_swapper_set()
3090 writeq(val64, &vpath_reg->kdfcctl_cfg0); in __vxge_hw_kdfc_swapper_set()
3244 writeq(value, (void __iomem *)hldev->legacy_reg + offset); in vxge_hw_mgmt_reg_write()
3251 writeq(value, (void __iomem *)hldev->toc_reg + offset); in vxge_hw_mgmt_reg_write()
3258 writeq(value, (void __iomem *)hldev->common_reg + offset); in vxge_hw_mgmt_reg_write()
3270 writeq(value, (void __iomem *)hldev->mrpcim_reg + offset); in vxge_hw_mgmt_reg_write()
3286 writeq(value, (void __iomem *)hldev->srpcim_reg[index] + in vxge_hw_mgmt_reg_write()
3300 writeq(value, (void __iomem *)hldev->vpmgmt_reg[index] + in vxge_hw_mgmt_reg_write()
3313 writeq(value, (void __iomem *)hldev->vpath_reg[index] + in vxge_hw_mgmt_reg_write()
3571 writeq(val64, &vp_reg->pci_config_access_cfg1); in __vxge_hw_vpath_pci_read()
3573 writeq(VXGE_HW_PCI_CONFIG_ACCESS_CFG2_REQ, in __vxge_hw_vpath_pci_read()
4077 writeq(val64, &vp_reg->prc_cfg1); in __vxge_hw_vpath_prc_configure()
4081 writeq(val64, &vpath->vp_reg->prc_cfg6); in __vxge_hw_vpath_prc_configure()
4106 writeq(val64, &vp_reg->prc_cfg7); in __vxge_hw_vpath_prc_configure()
4108 writeq(VXGE_HW_PRC_CFG5_RXD0_ADD( in __vxge_hw_vpath_prc_configure()
4124 writeq(val64, &vp_reg->prc_cfg4); in __vxge_hw_vpath_prc_configure()
4170 writeq(val64, &vp_reg->kdfc_fifo_trpl_partition); in __vxge_hw_vpath_kdfc_configure()
4172 writeq(VXGE_HW_KDFC_FIFO_TRPL_CTRL_TRIPLET_ENABLE, in __vxge_hw_vpath_kdfc_configure()
4187 writeq(val64, &vp_reg->kdfc_trpl_fifo_0_ctrl); in __vxge_hw_vpath_kdfc_configure()
4188 writeq((u64)0, &vp_reg->kdfc_trpl_fifo_0_wb_address); in __vxge_hw_vpath_kdfc_configure()
4217 writeq(VXGE_HW_XMAC_VSPORT_CHOICE_VSPORT_NUMBER( in __vxge_hw_vpath_mac_configure()
4232 writeq(val64, &vp_reg->xmac_rpa_vcfg); in __vxge_hw_vpath_mac_configure()
4248 writeq(val64, &vp_reg->rxmac_vcfg0); in __vxge_hw_vpath_mac_configure()
4262 writeq(val64, &vp_reg->rxmac_vcfg1); in __vxge_hw_vpath_mac_configure()
4284 writeq(0, &vp_reg->tim_dest_addr); in __vxge_hw_vpath_tim_configure()
4285 writeq(0, &vp_reg->tim_vpath_map); in __vxge_hw_vpath_tim_configure()
4286 writeq(0, &vp_reg->tim_bitmap); in __vxge_hw_vpath_tim_configure()
4287 writeq(0, &vp_reg->tim_remap); in __vxge_hw_vpath_tim_configure()
4290 writeq(VXGE_HW_TIM_RING_ASSN_INT_NUM( in __vxge_hw_vpath_tim_configure()
4296 writeq(val64, &vp_reg->tim_pci_cfg); in __vxge_hw_vpath_tim_configure()
4343 writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_TX]); in __vxge_hw_vpath_tim_configure()
4372 writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_TX]); in __vxge_hw_vpath_tim_configure()
4401 writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_TX]); in __vxge_hw_vpath_tim_configure()
4450 writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_RX]); in __vxge_hw_vpath_tim_configure()
4479 writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_RX]); in __vxge_hw_vpath_tim_configure()
4508 writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_RX]); in __vxge_hw_vpath_tim_configure()
4513 writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_EINTA]); in __vxge_hw_vpath_tim_configure()
4514 writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_EINTA]); in __vxge_hw_vpath_tim_configure()
4515 writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_EINTA]); in __vxge_hw_vpath_tim_configure()
4516 writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_BMAP]); in __vxge_hw_vpath_tim_configure()
4517 writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_BMAP]); in __vxge_hw_vpath_tim_configure()
4518 writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_BMAP]); in __vxge_hw_vpath_tim_configure()
4523 writeq(val64, &vp_reg->tim_wrkld_clc); in __vxge_hw_vpath_tim_configure()
4586 writeq(val64, &vp_reg->rtdma_rd_optimization_ctrl); in __vxge_hw_vpath_initialize()
4717 writeq(val64, &vpath->vp_reg->rxmac_vcfg0); in vxge_hw_vpath_mtu_set()
4855 writeq(vpath->stats_block->dma_addr, &vpath->vp_reg->stats_cfg); in vxge_hw_vpath_open()
4910 writeq(VXGE_HW_PRC_RXD_DOORBELL_NEW_QW_CNT(val164), in vxge_hw_vpath_rx_doorbell_init()
5072 writeq(vpath->stats_block->dma_addr, in vxge_hw_vpath_recover_from_reset()