Lines Matching refs:IRO
86 (IRO[IRO_CORE_LL2_PSTORM_PER_QUEUE_STAT].base \
87 + ((core_tx_stats_id) * IRO[IRO_CORE_LL2_PSTORM_PER_QUEUE_STAT].m1))
89 (IRO[IRO_CORE_LL2_PSTORM_PER_QUEUE_STAT].size)
93 (IRO[IRO_CORE_LL2_TSTORM_PER_QUEUE_STAT].base \
94 + ((core_rx_queue_id) * IRO[IRO_CORE_LL2_TSTORM_PER_QUEUE_STAT].m1))
96 (IRO[IRO_CORE_LL2_TSTORM_PER_QUEUE_STAT].size)
100 (IRO[IRO_CORE_LL2_USTORM_PER_QUEUE_STAT].base \
101 + ((core_rx_queue_id) * IRO[IRO_CORE_LL2_USTORM_PER_QUEUE_STAT].m1))
103 (IRO[IRO_CORE_LL2_USTORM_PER_QUEUE_STAT].size)
107 (IRO[IRO_ETH_RX_RATE_LIMIT].base \
108 + ((pf_id) * IRO[IRO_ETH_RX_RATE_LIMIT].m1))
109 #define ETH_RX_RATE_LIMIT_SIZE (IRO[IRO_ETH_RX_RATE_LIMIT].size)
113 (IRO[IRO_MSTORM_ETH_PF_PRODS_GTT].base \
114 + ((queue_id) * IRO[IRO_MSTORM_ETH_PF_PRODS_GTT].m1))
115 #define MSTORM_ETH_PF_PRODS_GTT_SIZE (IRO[IRO_MSTORM_ETH_PF_PRODS_GTT].size)
119 (IRO[IRO_MSTORM_ETH_PF_STAT].base \
120 + ((pf_id) * IRO[IRO_MSTORM_ETH_PF_STAT].m1))
121 #define MSTORM_ETH_PF_STAT_SIZE (IRO[IRO_MSTORM_ETH_PF_STAT].size)
127 (IRO[IRO_MSTORM_ETH_VF_PRODS].base \
128 + ((vf_id) * IRO[IRO_MSTORM_ETH_VF_PRODS].m1) \
129 + ((vf_queue_id) * IRO[IRO_MSTORM_ETH_VF_PRODS].m2))
130 #define MSTORM_ETH_VF_PRODS_SIZE (IRO[IRO_MSTORM_ETH_VF_PRODS].size)
133 #define MSTORM_INTEG_TEST_DATA_OFFSET (IRO[IRO_MSTORM_INTEG_TEST_DATA].base)
134 #define MSTORM_INTEG_TEST_DATA_SIZE (IRO[IRO_MSTORM_INTEG_TEST_DATA].size)
138 (IRO[IRO_MSTORM_ISCSI_RX_STATS].base \
139 + ((storage_func_id) * IRO[IRO_MSTORM_ISCSI_RX_STATS].m1))
140 #define MSTORM_ISCSI_RX_STATS_SIZE (IRO[IRO_MSTORM_ISCSI_RX_STATS].size)
143 #define MSTORM_OVERLAY_BUF_ADDR_OFFSET (IRO[IRO_MSTORM_OVERLAY_BUF_ADDR].base)
144 #define MSTORM_OVERLAY_BUF_ADDR_SIZE (IRO[IRO_MSTORM_OVERLAY_BUF_ADDR].size)
148 (IRO[IRO_MSTORM_QUEUE_STAT].base \
149 + ((stat_counter_id) * IRO[IRO_MSTORM_QUEUE_STAT].m1))
150 #define MSTORM_QUEUE_STAT_SIZ (IRO[IRO_MSTORM_QUEUE_STAT].size)
154 (IRO[IRO_MSTORM_RDMA_ASSERT_LEVEL].base \
155 + ((pf_id) * IRO[IRO_MSTORM_RDMA_ASSERT_LEVEL].m1))
156 #define MSTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[IRO_MSTORM_RDMA_ASSERT_LEVEL].size)
160 (IRO[IRO_MSTORM_SCSI_BDQ_EXT_PROD_GTT].base \
161 + ((storage_func_id) * IRO[IRO_MSTORM_SCSI_BDQ_EXT_PROD_GTT].m1) \
162 + ((bdq_id) * IRO[IRO_MSTORM_SCSI_BDQ_EXT_PROD_GTT].m2))
164 (IRO[IRO_MSTORM_SCSI_BDQ_EXT_PROD_GTT].size)
167 #define MSTORM_TPA_TIMEOUT_US_OFFSET (IRO[IRO_MSTORM_TPA_TIMEOUT_US].base)
168 #define MSTORM_TPA_TIMEOUT_US_SIZE (IRO[IRO_MSTORM_TPA_TIMEOUT_US].size)
172 (IRO[IRO_PSTORM_CTL_FRAME_ETHTYPE_GTT].base \
173 + ((ethtype_id) * IRO[IRO_PSTORM_CTL_FRAME_ETHTYPE_GTT].m1))
175 (IRO[IRO_PSTORM_CTL_FRAME_ETHTYPE_GTT].size)
179 (IRO[IRO_PSTORM_ETH_PF_STAT].base \
180 + ((pf_id) * IRO[IRO_PSTORM_ETH_PF_STAT].m1))
181 #define PSTORM_ETH_PF_STAT_SIZE (IRO[IRO_PSTORM_ETH_PF_STAT].size)
185 (IRO[IRO_PSTORM_FCOE_TX_STATS].base \
186 + ((pf_id) * IRO[IRO_PSTORM_FCOE_TX_STATS].m1))
187 #define PSTORM_FCOE_TX_STATS_SIZE (IRO[IRO_PSTORM_FCOE_TX_STATS].size)
190 #define PSTORM_INTEG_TEST_DATA_OFFSET (IRO[IRO_PSTORM_INTEG_TEST_DATA].base)
191 #define PSTORM_INTEG_TEST_DATA_SIZE (IRO[IRO_PSTORM_INTEG_TEST_DATA].size)
195 (IRO[IRO_PSTORM_ISCSI_TX_STATS].base \
196 + ((storage_func_id) * IRO[IRO_PSTORM_ISCSI_TX_STATS].m1))
197 #define PSTORM_ISCSI_TX_STATS_SIZE (IRO[IRO_PSTORM_ISCSI_TX_STATS].size)
200 #define PSTORM_OVERLAY_BUF_ADDR_OFFSET (IRO[IRO_PSTORM_OVERLAY_BUF_ADDR].base)
201 #define PSTORM_OVERLAY_BUF_ADDR_SIZE (IRO[IRO_PSTORM_OVERLAY_BUF_ADDR].size)
207 (IRO[IRO_PSTORM_PKT_DUPLICATION_CFG].base \
208 + ((pf_id) * IRO[IRO_PSTORM_PKT_DUPLICATION_CFG].m1))
210 (IRO[IRO_PSTORM_PKT_DUPLICATION_CFG].size)
214 (IRO[IRO_PSTORM_QUEUE_STAT].base \
215 + ((stat_counter_id) * IRO[IRO_PSTORM_QUEUE_STAT].m1))
216 #define PSTORM_QUEUE_STAT_SIZE (IRO[IRO_PSTORM_QUEUE_STAT].size)
220 (IRO[IRO_PSTORM_RDMA_ASSERT_LEVEL].base \
221 + ((pf_id) * IRO[IRO_PSTORM_RDMA_ASSERT_LEVEL].m1))
222 #define PSTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[IRO_PSTORM_RDMA_ASSERT_LEVEL].size)
226 (IRO[IRO_PSTORM_RDMA_QUEUE_STAT].base \
227 + ((rdma_stat_counter_id) * IRO[IRO_PSTORM_RDMA_QUEUE_STAT].m1))
228 #define PSTORM_RDMA_QUEUE_STAT_SIZE (IRO[IRO_PSTORM_RDMA_QUEUE_STAT].size)
232 (IRO[IRO_PSTORM_ROCE_DCQCN_SENT_STATS].base \
233 + ((roce_pf_id) * IRO[IRO_PSTORM_ROCE_DCQCN_SENT_STATS].m1))
235 (IRO[IRO_PSTORM_ROCE_DCQCN_SENT_STATS].size)
238 #define TSTORM_ETH_PRS_INPUT_OFFSET (IRO[IRO_TSTORM_ETH_PRS_INPUT].base)
239 #define TSTORM_ETH_PRS_INPUT_SIZE (IRO[IRO_TSTORM_ETH_PRS_INPUT].size)
245 (IRO[IRO_TSTORM_ETH_RSS_UPDATE_GTT].base \
246 + ((pf_id) * IRO[IRO_TSTORM_ETH_RSS_UPDATE_GTT].m1))
248 (IRO[IRO_TSTORM_ETH_RSS_UPDATE_GTT].size)
252 (IRO[IRO_TSTORM_FCOE_RX_STATS].base \
253 + ((pf_id) * IRO[IRO_TSTORM_FCOE_RX_STATS].m1))
254 #define TSTORM_FCOE_RX_STATS_SIZE (IRO[IRO_TSTORM_FCOE_RX_STATS].size)
257 #define TSTORM_INTEG_TEST_DATA_OFFSET (IRO[IRO_TSTORM_INTEG_TEST_DATA].base)
258 #define TSTORM_INTEG_TEST_DATA_SIZE (IRO[IRO_TSTORM_INTEG_TEST_DATA].size)
262 (IRO[IRO_TSTORM_ISCSI_RX_STATS].base \
263 + ((storage_func_id) * IRO[IRO_TSTORM_ISCSI_RX_STATS].m1))
264 #define TSTORM_ISCSI_RX_STATS_SIZE (IRO[IRO_TSTORM_ISCSI_RX_STATS].size)
268 (IRO[IRO_TSTORM_LL2_PORT_STAT].base \
269 + ((port_id) * IRO[IRO_TSTORM_LL2_PORT_STAT].m1))
270 #define TSTORM_LL2_PORT_STAT_SIZE (IRO[IRO_TSTORM_LL2_PORT_STAT].size)
274 (IRO[IRO_TSTORM_LL2_RX_PRODS_GTT].base \
275 + ((core_rx_queue_id) * IRO[IRO_TSTORM_LL2_RX_PRODS_GTT].m1))
276 #define TSTORM_LL2_RX_PRODS_GTT_SIZE (IRO[IRO_TSTORM_LL2_RX_PRODS_GTT].size)
279 #define TSTORM_OVERLAY_BUF_ADDR_OFFSET (IRO[IRO_TSTORM_OVERLAY_BUF_ADDR].base)
281 #define TSTORM_OVERLAY_BUF_ADDR_SIZE (IRO[IRO_TSTORM_OVERLAY_BUF_ADDR].size)
287 (IRO[IRO_TSTORM_PKT_DUPLICATION_CFG].base \
288 + ((pf_id) * IRO[IRO_TSTORM_PKT_DUPLICATION_CFG].m1))
290 (IRO[IRO_TSTORM_PKT_DUPLICATION_CFG].size)
294 (IRO[IRO_TSTORM_PORT_STAT].base \
295 + ((port_id) * IRO[IRO_TSTORM_PORT_STAT].m1))
296 #define TSTORM_PORT_STAT_SIZE (IRO[IRO_TSTORM_PORT_STAT].size)
300 (IRO[IRO_TSTORM_RDMA_ASSERT_LEVEL].base \
301 + ((pf_id) * IRO[IRO_TSTORM_RDMA_ASSERT_LEVEL].m1))
302 #define TSTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[IRO_TSTORM_RDMA_ASSERT_LEVEL].size)
306 (IRO[IRO_TSTORM_RDMA_QUEUE_STAT].base \
307 + ((rdma_stat_counter_id) * IRO[IRO_TSTORM_RDMA_QUEUE_STAT].m1))
308 #define TSTORM_RDMA_QUEUE_STAT_SIZE (IRO[IRO_TSTORM_RDMA_QUEUE_STAT].size)
312 (IRO[IRO_TSTORM_ROCE_EVENTS_STAT].base \
313 + ((roce_pf_id) * IRO[IRO_TSTORM_ROCE_EVENTS_STAT].m1))
314 #define TSTORM_ROCE_EVENTS_STAT_SIZE (IRO[IRO_TSTORM_ROCE_EVENTS_STAT].size)
320 (IRO[IRO_TSTORM_SCSI_BDQ_EXT_PROD_GTT].base \
321 + ((storage_func_id) * IRO[IRO_TSTORM_SCSI_BDQ_EXT_PROD_GTT].m1) \
322 + ((bdq_id) * IRO[IRO_TSTORM_SCSI_BDQ_EXT_PROD_GTT].m2))
324 (IRO[IRO_TSTORM_SCSI_BDQ_EXT_PROD_GTT].size)
328 (IRO[IRO_TSTORM_SCSI_CMDQ_CONS_GTT].base \
329 + ((cmdq_queue_id) * IRO[IRO_TSTORM_SCSI_CMDQ_CONS_GTT].m1))
331 (IRO[IRO_TSTORM_SCSI_CMDQ_CONS_GTT].size)
335 (IRO[IRO_USTORM_COMMON_QUEUE_CONS_GTT].base \
336 + ((queue_zone_id) * IRO[IRO_USTORM_COMMON_QUEUE_CONS_GTT].m1))
338 (IRO[IRO_USTORM_COMMON_QUEUE_CONS_GTT].size)
342 (IRO[IRO_USTORM_EQE_CONS_GTT].base \
343 + ((pf_id) * IRO[IRO_USTORM_EQE_CONS_GTT].m1))
344 #define USTORM_EQE_CONS_GTT_SIZE (IRO[IRO_USTORM_EQE_CONS_GTT].size)
348 (IRO[IRO_USTORM_ETH_PF_STAT].base \
349 + ((pf_id) * IRO[IRO_USTORM_ETH_PF_STAT].m1))
350 #define USTORM_ETH_PF_STAT_SIZE (IRO[IRO_USTORM_ETH_PF_STAT].size)
354 (IRO[IRO_USTORM_ETH_QUEUE_ZONE_GTT].base \
355 + ((queue_zone_id) * IRO[IRO_USTORM_ETH_QUEUE_ZONE_GTT].m1))
356 #define USTORM_ETH_QUEUE_ZONE_GTT_SIZE (IRO[IRO_USTORM_ETH_QUEUE_ZONE_GTT].size)
360 (IRO[IRO_USTORM_FLR_FINAL_ACK_GTT].base \
361 + ((pf_id) * IRO[IRO_USTORM_FLR_FINAL_ACK_GTT].m1))
362 #define USTORM_FLR_FINAL_ACK_GTT_SIZE (IRO[IRO_USTORM_FLR_FINAL_ACK_GTT].size)
365 #define USTORM_INTEG_TEST_DATA_OFFSET (IRO[IRO_USTORM_INTEG_TEST_DATA].base)
366 #define USTORM_INTEG_TEST_DATA_SIZE (IRO[IRO_USTORM_INTEG_TEST_DATA].size)
370 (IRO[IRO_USTORM_ISCSI_RX_STATS].base \
371 + ((storage_func_id) * IRO[IRO_USTORM_ISCSI_RX_STATS].m1))
372 #define USTORM_ISCSI_RX_STATS_SIZE (IRO[IRO_USTORM_ISCSI_RX_STATS].size)
375 #define USTORM_OVERLAY_BUF_ADDR_OFFSET (IRO[IRO_USTORM_OVERLAY_BUF_ADDR].base)
376 #define USTORM_OVERLAY_BUF_ADDR_SIZE (IRO[IRO_USTORM_OVERLAY_BUF_ADDR].size)
380 (IRO[IRO_USTORM_QUEUE_STAT].base \
381 + ((stat_counter_id) * IRO[IRO_USTORM_QUEUE_STAT].m1))
382 #define USTORM_QUEUE_STAT_SIZE (IRO[IRO_USTORM_QUEUE_STAT].size)
386 (IRO[IRO_USTORM_RDMA_ASSERT_LEVEL].base \
387 + ((pf_id) * IRO[IRO_USTORM_RDMA_ASSERT_LEVEL].m1))
388 #define USTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[IRO_USTORM_RDMA_ASSERT_LEVEL].size)
392 (IRO[IRO_USTORM_ROCE_CQE_STATS].base \
393 + ((roce_pf_id) * IRO[IRO_USTORM_ROCE_CQE_STATS].m1))
394 #define USTORM_ROCE_CQE_STATS_SIZE (IRO[IRO_USTORM_ROCE_CQE_STATS].size)
398 (IRO[IRO_USTORM_TOE_CQ_PROD].base \
399 + ((rss_id) * IRO[IRO_USTORM_TOE_CQ_PROD].m1))
400 #define USTORM_TOE_CQ_PROD_SIZE (IRO[IRO_USTORM_TOE_CQ_PROD].size)
404 (IRO[IRO_USTORM_TOE_GRQ_PROD].base \
405 + ((pf_id) * IRO[IRO_USTORM_TOE_GRQ_PROD].m1))
406 #define USTORM_TOE_GRQ_PROD_SIZE (IRO[IRO_USTORM_TOE_GRQ_PROD].size)
410 (IRO[IRO_USTORM_VF_PF_CHANNEL_READY_GTT].base \
411 + ((vf_id) * IRO[IRO_USTORM_VF_PF_CHANNEL_READY_GTT].m1))
413 (IRO[IRO_USTORM_VF_PF_CHANNEL_READY_GTT].size)
417 (IRO[IRO_XSTORM_ETH_QUEUE_ZONE_GTT].base \
418 + ((queue_id) * IRO[IRO_XSTORM_ETH_QUEUE_ZONE_GTT].m1))
419 #define XSTORM_ETH_QUEUE_ZONE_GTT_SIZE (IRO[IRO_XSTORM_ETH_QUEUE_ZONE_GTT].size)
422 #define XSTORM_INTEG_TEST_DATA_OFFSET (IRO[IRO_XSTORM_INTEG_TEST_DATA].base)
423 #define XSTORM_INTEG_TEST_DATA_SIZE (IRO[IRO_XSTORM_INTEG_TEST_DATA].size)
427 (IRO[IRO_XSTORM_ISCSI_TX_STATS].base \
428 + ((storage_func_id) * IRO[IRO_XSTORM_ISCSI_TX_STATS].m1))
429 #define XSTORM_ISCSI_TX_STATS_SIZE (IRO[IRO_XSTORM_ISCSI_TX_STATS].size)
433 (IRO[IRO_XSTORM_IWARP_RXMIT_STATS].base \
434 + ((pf_id) * IRO[IRO_XSTORM_IWARP_RXMIT_STATS].m1))
435 #define XSTORM_IWARP_RXMIT_STATS_SIZE (IRO[IRO_XSTORM_IWARP_RXMIT_STATS].size)
438 #define XSTORM_OVERLAY_BUF_ADDR_OFFSET (IRO[IRO_XSTORM_OVERLAY_BUF_ADDR].base)
439 #define XSTORM_OVERLAY_BUF_ADDR_SIZE (IRO[IRO_XSTORM_OVERLAY_BUF_ADDR].size)
443 (IRO[IRO_XSTORM_PQ_INFO].base \
444 + ((pq_id) * IRO[IRO_XSTORM_PQ_INFO].m1))
445 #define XSTORM_PQ_INFO_SIZE (IRO[IRO_XSTORM_PQ_INFO].size)
449 (IRO[IRO_XSTORM_RDMA_ASSERT_LEVEL].base \
450 + ((pf_id) * IRO[IRO_XSTORM_RDMA_ASSERT_LEVEL].m1))
451 #define XSTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[IRO_XSTORM_RDMA_ASSERT_LEVEL].size)
455 (IRO[IRO_YSTORM_FLOW_CONTROL_MODE_GTT].base)
457 (IRO[IRO_YSTORM_FLOW_CONTROL_MODE_GTT].size)
460 #define YSTORM_INTEG_TEST_DATA_OFFSET (IRO[IRO_YSTORM_INTEG_TEST_DATA].base)
461 #define YSTORM_INTEG_TEST_DATA_SIZE (IRO[IRO_YSTORM_INTEG_TEST_DATA].size)
465 (IRO[IRO_YSTORM_ISCSI_TX_STATS].base \
466 + ((storage_func_id) * IRO[IRO_YSTORM_ISCSI_TX_STATS].m1))
467 #define YSTORM_ISCSI_TX_STATS_SIZE (IRO[IRO_YSTORM_ISCSI_TX_STATS].size)
470 #define YSTORM_OVERLAY_BUF_ADDR_OFFSET (IRO[IRO_YSTORM_OVERLAY_BUF_ADDR].base)
471 #define YSTORM_OVERLAY_BUF_ADDR_SIZE (IRO[IRO_YSTORM_OVERLAY_BUF_ADDR].size)
475 (IRO[IRO_YSTORM_RDMA_ASSERT_LEVEL].base \
476 + ((pf_id) * IRO[IRO_YSTORM_RDMA_ASSERT_LEVEL].m1))
477 #define YSTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[IRO_YSTORM_RDMA_ASSERT_LEVEL].size)
481 (IRO[IRO_YSTORM_ROCE_DCQCN_RECEIVED_STATS].base \
482 + ((roce_pf_id) * IRO[IRO_YSTORM_ROCE_DCQCN_RECEIVED_STATS].m1))
484 (IRO[IRO_YSTORM_ROCE_DCQCN_RECEIVED_STATS].size)
488 (IRO[IRO_YSTORM_ROCE_ERROR_STATS].base \
489 + ((roce_pf_id) * IRO[IRO_YSTORM_ROCE_ERROR_STATS].m1))
490 #define YSTORM_ROCE_ERROR_STATS_SIZE (IRO[IRO_YSTORM_ROCE_ERROR_STATS].size)
494 (IRO[IRO_YSTORM_TOE_CQ_PROD].base \
495 + ((rss_id) * IRO[IRO_YSTORM_TOE_CQ_PROD].m1))
496 #define YSTORM_TOE_CQ_PROD_SIZE (IRO[IRO_YSTORM_TOE_CQ_PROD].size)