Lines Matching refs:writel
38 writel(reg_val, ioaddr + SXGBE_DMA_SYSBUS_MODE_REG); in sxgbe_dma_init()
54 writel(reg_val, ioaddr + SXGBE_DMA_CHA_CTL_REG(cha_num)); in sxgbe_dma_channel_init()
58 writel(reg_val, ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cha_num)); in sxgbe_dma_channel_init()
62 writel(reg_val, ioaddr + SXGBE_DMA_CHA_RXCTL_REG(cha_num)); in sxgbe_dma_channel_init()
66 writel(upper_32_bits(dma_tx), in sxgbe_dma_channel_init()
68 writel(lower_32_bits(dma_tx), in sxgbe_dma_channel_init()
71 writel(upper_32_bits(dma_rx), in sxgbe_dma_channel_init()
73 writel(lower_32_bits(dma_rx), in sxgbe_dma_channel_init()
81 writel(lower_32_bits(dma_addr), in sxgbe_dma_channel_init()
85 writel(lower_32_bits(dma_addr), in sxgbe_dma_channel_init()
88 writel(t_rsize - 1, ioaddr + SXGBE_DMA_CHA_TXDESC_RINGLEN_REG(cha_num)); in sxgbe_dma_channel_init()
89 writel(r_rsize - 1, ioaddr + SXGBE_DMA_CHA_RXDESC_RINGLEN_REG(cha_num)); in sxgbe_dma_channel_init()
92 writel(SXGBE_DMA_ENA_INT, in sxgbe_dma_channel_init()
102 writel(tx_config, ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cha_num)); in sxgbe_enable_dma_transmission()
108 writel(SXGBE_DMA_ENA_INT, in sxgbe_enable_dma_irq()
115 writel(0, ioaddr + SXGBE_DMA_CHA_INT_ENABLE_REG(dma_cnum)); in sxgbe_disable_dma_irq()
126 writel(tx_ctl_reg, in sxgbe_dma_start_tx()
137 writel(tx_ctl_reg, ioaddr + SXGBE_DMA_CHA_TXCTL_REG(dma_cnum)); in sxgbe_dma_start_tx_queue()
146 writel(tx_ctl_reg, ioaddr + SXGBE_DMA_CHA_TXCTL_REG(dma_cnum)); in sxgbe_dma_stop_tx_queue()
157 writel(tx_ctl_reg, ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cnum)); in sxgbe_dma_stop_tx()
169 writel(rx_ctl_reg, in sxgbe_dma_start_rx()
182 writel(rx_ctl_reg, ioaddr + SXGBE_DMA_CHA_RXCTL_REG(cnum)); in sxgbe_dma_stop_rx()
253 writel(clear_val, ioaddr + SXGBE_DMA_CHA_STATUS_REG(channel_no)); in sxgbe_tx_dma_int_status()
319 writel(clear_val, ioaddr + SXGBE_DMA_CHA_STATUS_REG(channel_no)); in sxgbe_rx_dma_int_status()
330 writel(riwt, in sxgbe_dma_rx_watchdog()
341 writel(ctrl, ioaddr + SXGBE_DMA_CHA_TXCTL_REG(chan_num)); in sxgbe_enable_tso()