Lines Matching refs:tx_queues_cfg
436 plat->tx_queues_cfg[0].use_prio = false; in common_default_data()
483 plat->tx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB; in intel_mgbe_common_data()
486 plat->tx_queues_cfg[i].use_prio = false; in intel_mgbe_common_data()
489 plat->tx_queues_cfg[i].tbs_en = 1; in intel_mgbe_common_data()
497 plat->tx_queues_cfg[0].weight = 0x09; in intel_mgbe_common_data()
498 plat->tx_queues_cfg[1].weight = 0x0A; in intel_mgbe_common_data()
499 plat->tx_queues_cfg[2].weight = 0x0B; in intel_mgbe_common_data()
500 plat->tx_queues_cfg[3].weight = 0x0C; in intel_mgbe_common_data()
501 plat->tx_queues_cfg[4].weight = 0x0D; in intel_mgbe_common_data()
502 plat->tx_queues_cfg[5].weight = 0x0E; in intel_mgbe_common_data()
503 plat->tx_queues_cfg[6].weight = 0x0F; in intel_mgbe_common_data()
504 plat->tx_queues_cfg[7].weight = 0x10; in intel_mgbe_common_data()