Lines Matching refs:writel
16 writel(value | XGMAC_SWR, ioaddr + XGMAC_DMA_MODE); in dwxgmac2_dma_reset()
33 writel(value, ioaddr + XGMAC_DMA_SYSBUS_MODE); in dwxgmac2_dma_init()
44 writel(value, ioaddr + XGMAC_DMA_CH_CONTROL(chan)); in dwxgmac2_dma_init_chan()
45 writel(XGMAC_DMA_INT_DEFAULT_EN, ioaddr + XGMAC_DMA_CH_INT_EN(chan)); in dwxgmac2_dma_init_chan()
58 writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); in dwxgmac2_dma_init_rx_chan()
60 writel(upper_32_bits(phy), ioaddr + XGMAC_DMA_CH_RxDESC_HADDR(chan)); in dwxgmac2_dma_init_rx_chan()
61 writel(lower_32_bits(phy), ioaddr + XGMAC_DMA_CH_RxDESC_LADDR(chan)); in dwxgmac2_dma_init_rx_chan()
75 writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); in dwxgmac2_dma_init_tx_chan()
77 writel(upper_32_bits(phy), ioaddr + XGMAC_DMA_CH_TxDESC_HADDR(chan)); in dwxgmac2_dma_init_tx_chan()
78 writel(lower_32_bits(phy), ioaddr + XGMAC_DMA_CH_TxDESC_LADDR(chan)); in dwxgmac2_dma_init_tx_chan()
129 writel(value, ioaddr + XGMAC_DMA_SYSBUS_MODE); in dwxgmac2_dma_axi()
130 writel(XGMAC_TDPS, ioaddr + XGMAC_TX_EDMA_CTRL); in dwxgmac2_dma_axi()
131 writel(XGMAC_RDPS, ioaddr + XGMAC_RX_EDMA_CTRL); in dwxgmac2_dma_axi()
198 writel(flow, ioaddr + XGMAC_MTL_RXQ_FLOW_CONTROL(channel)); in dwxgmac2_dma_rx_mode()
201 writel(value, ioaddr + XGMAC_MTL_RXQ_OPMODE(channel)); in dwxgmac2_dma_rx_mode()
205 writel(value | XGMAC_RXOIE, ioaddr + XGMAC_MTL_QINTEN(channel)); in dwxgmac2_dma_rx_mode()
248 writel(value, ioaddr + XGMAC_MTL_TXQ_OPMODE(channel)); in dwxgmac2_dma_tx_mode()
261 writel(value, ioaddr + XGMAC_DMA_CH_INT_EN(chan)); in dwxgmac2_enable_dma_irq()
274 writel(value, ioaddr + XGMAC_DMA_CH_INT_EN(chan)); in dwxgmac2_disable_dma_irq()
283 writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); in dwxgmac2_dma_start_tx()
287 writel(value, ioaddr + XGMAC_TX_CONFIG); in dwxgmac2_dma_start_tx()
296 writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); in dwxgmac2_dma_stop_tx()
300 writel(value, ioaddr + XGMAC_TX_CONFIG); in dwxgmac2_dma_stop_tx()
309 writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); in dwxgmac2_dma_start_rx()
313 writel(value, ioaddr + XGMAC_RX_CONFIG); in dwxgmac2_dma_start_rx()
322 writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); in dwxgmac2_dma_stop_rx()
369 writel(intr_en & intr_status, ioaddr + XGMAC_DMA_CH_STATUS(chan)); in dwxgmac2_dma_interrupt()
454 writel(riwt & XGMAC_RWT, ioaddr + XGMAC_DMA_CH_Rx_WATCHDOG(queue)); in dwxgmac2_rx_watchdog()
459 writel(len, ioaddr + XGMAC_DMA_CH_RxDESC_RING_LEN(chan)); in dwxgmac2_set_rx_ring_len()
464 writel(len, ioaddr + XGMAC_DMA_CH_TxDESC_RING_LEN(chan)); in dwxgmac2_set_tx_ring_len()
469 writel(ptr, ioaddr + XGMAC_DMA_CH_RxDESC_TAIL_LPTR(chan)); in dwxgmac2_set_rx_tail_ptr()
474 writel(ptr, ioaddr + XGMAC_DMA_CH_TxDESC_TAIL_LPTR(chan)); in dwxgmac2_set_tx_tail_ptr()
486 writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); in dwxgmac2_enable_tso()
497 writel(0, ioaddr + XGMAC_MTL_TCx_ETS_CONTROL(channel)); in dwxgmac2_qmode()
500 writel(flow & (~XGMAC_RFE), ioaddr + XGMAC_RX_FLOW_CTRL); in dwxgmac2_qmode()
503 writel(value, ioaddr + XGMAC_MTL_TXQ_OPMODE(channel)); in dwxgmac2_qmode()
513 writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); in dwxgmac2_set_bfsize()
522 writel(value, ioaddr + XGMAC_RX_CONFIG); in dwxgmac2_enable_sph()
529 writel(value, ioaddr + XGMAC_DMA_CH_CONTROL(chan)); in dwxgmac2_enable_sph()
541 writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); in dwxgmac2_enable_tbs()
547 writel(XGMAC_DEF_FTOS, ioaddr + XGMAC_DMA_TBS_CTRL0); in dwxgmac2_enable_tbs()
548 writel(XGMAC_DEF_FTOS, ioaddr + XGMAC_DMA_TBS_CTRL1); in dwxgmac2_enable_tbs()
549 writel(XGMAC_DEF_FTOS, ioaddr + XGMAC_DMA_TBS_CTRL2); in dwxgmac2_enable_tbs()
550 writel(XGMAC_DEF_FTOS, ioaddr + XGMAC_DMA_TBS_CTRL3); in dwxgmac2_enable_tbs()