Lines Matching refs:priv
212 struct scc_priv priv[2]; member
221 static void write_scc(struct scc_priv *priv, int reg, int val);
222 static void write_scc_data(struct scc_priv *priv, int val, int fast);
223 static int read_scc(struct scc_priv *priv, int reg);
224 static int read_scc_data(struct scc_priv *priv);
233 static inline void tx_on(struct scc_priv *priv);
234 static inline void rx_on(struct scc_priv *priv);
235 static inline void rx_off(struct scc_priv *priv);
236 static void start_timer(struct scc_priv *priv, int t, int r15);
241 static void rx_isr(struct scc_priv *priv);
242 static void special_condition(struct scc_priv *priv, int rc);
244 static void tx_isr(struct scc_priv *priv);
245 static void es_isr(struct scc_priv *priv);
246 static void tm_isr(struct scc_priv *priv);
281 if (info->priv[0].type == TYPE_TWIN) in dmascc_exit()
283 write_scc(&info->priv[0], R9, FHWRES); in dmascc_exit()
285 hw[info->priv[0].type].io_size); in dmascc_exit()
445 struct scc_priv *priv; in setup_adapter() local
478 priv = &info->priv[0]; in setup_adapter()
479 priv->type = type; in setup_adapter()
480 priv->card_base = card_base; in setup_adapter()
481 priv->scc_cmd = scc_base + SCCA_CMD; in setup_adapter()
482 priv->scc_data = scc_base + SCCA_DATA; in setup_adapter()
483 priv->register_lock = &info->register_lock; in setup_adapter()
486 write_scc(priv, R9, FHWRES | MIE | NV); in setup_adapter()
489 write_scc(priv, R15, SHDLCE); in setup_adapter()
490 if (!read_scc(priv, R15)) { in setup_adapter()
495 write_scc_data(priv, 0, 0); in setup_adapter()
496 if (read_scc(priv, R0) & Tx_BUF_EMP) { in setup_adapter()
504 write_scc(priv, R15, 0); in setup_adapter()
517 write_scc(priv, R15, CTSIE); in setup_adapter()
518 write_scc(priv, R0, RES_EXT_INT); in setup_adapter()
519 write_scc(priv, R1, EXT_INT_ENAB); in setup_adapter()
535 write_scc(priv, R1, 0); in setup_adapter()
536 write_scc(priv, R15, 0); in setup_adapter()
537 write_scc(priv, R0, RES_EXT_INT); in setup_adapter()
551 priv = &info->priv[i]; in setup_adapter()
552 priv->type = type; in setup_adapter()
553 priv->chip = chip; in setup_adapter()
554 priv->dev = dev; in setup_adapter()
555 priv->info = info; in setup_adapter()
556 priv->channel = i; in setup_adapter()
557 spin_lock_init(&priv->ring_lock); in setup_adapter()
558 priv->register_lock = &info->register_lock; in setup_adapter()
559 priv->card_base = card_base; in setup_adapter()
560 priv->scc_cmd = scc_base + (i ? SCCB_CMD : SCCA_CMD); in setup_adapter()
561 priv->scc_data = scc_base + (i ? SCCB_DATA : SCCA_DATA); in setup_adapter()
562 priv->tmr_cnt = tmr_base + (i ? TMR_CNT2 : TMR_CNT1); in setup_adapter()
563 priv->tmr_ctrl = tmr_base + TMR_CTRL; in setup_adapter()
564 priv->tmr_mode = i ? 0xb0 : 0x70; in setup_adapter()
565 priv->param.pclk_hz = hw[type].pclk_hz; in setup_adapter()
566 priv->param.brg_tc = -1; in setup_adapter()
567 priv->param.clocks = TCTRxCP | RCRTxCP; in setup_adapter()
568 priv->param.persist = 256; in setup_adapter()
569 priv->param.dma = -1; in setup_adapter()
570 INIT_WORK(&priv->rx_work, rx_bh); in setup_adapter()
571 dev->ml_priv = priv; in setup_adapter()
601 if (info->priv[0].type == TYPE_TWIN) in setup_adapter()
603 write_scc(&info->priv[0], R9, FHWRES); in setup_adapter()
616 static void write_scc(struct scc_priv *priv, int reg, int val) in write_scc() argument
619 switch (priv->type) { in write_scc()
622 outb(reg, priv->scc_cmd); in write_scc()
623 outb(val, priv->scc_cmd); in write_scc()
627 outb_p(reg, priv->scc_cmd); in write_scc()
628 outb_p(val, priv->scc_cmd); in write_scc()
631 spin_lock_irqsave(priv->register_lock, flags); in write_scc()
632 outb_p(0, priv->card_base + PI_DREQ_MASK); in write_scc()
634 outb_p(reg, priv->scc_cmd); in write_scc()
635 outb_p(val, priv->scc_cmd); in write_scc()
636 outb(1, priv->card_base + PI_DREQ_MASK); in write_scc()
637 spin_unlock_irqrestore(priv->register_lock, flags); in write_scc()
643 static void write_scc_data(struct scc_priv *priv, int val, int fast) in write_scc_data() argument
646 switch (priv->type) { in write_scc_data()
648 outb(val, priv->scc_data); in write_scc_data()
651 outb_p(val, priv->scc_data); in write_scc_data()
655 outb_p(val, priv->scc_data); in write_scc_data()
657 spin_lock_irqsave(priv->register_lock, flags); in write_scc_data()
658 outb_p(0, priv->card_base + PI_DREQ_MASK); in write_scc_data()
659 outb_p(val, priv->scc_data); in write_scc_data()
660 outb(1, priv->card_base + PI_DREQ_MASK); in write_scc_data()
661 spin_unlock_irqrestore(priv->register_lock, flags); in write_scc_data()
668 static int read_scc(struct scc_priv *priv, int reg) in read_scc() argument
672 switch (priv->type) { in read_scc()
675 outb(reg, priv->scc_cmd); in read_scc()
676 return inb(priv->scc_cmd); in read_scc()
679 outb_p(reg, priv->scc_cmd); in read_scc()
680 return inb_p(priv->scc_cmd); in read_scc()
682 spin_lock_irqsave(priv->register_lock, flags); in read_scc()
683 outb_p(0, priv->card_base + PI_DREQ_MASK); in read_scc()
685 outb_p(reg, priv->scc_cmd); in read_scc()
686 rc = inb_p(priv->scc_cmd); in read_scc()
687 outb(1, priv->card_base + PI_DREQ_MASK); in read_scc()
688 spin_unlock_irqrestore(priv->register_lock, flags); in read_scc()
694 static int read_scc_data(struct scc_priv *priv) in read_scc_data() argument
698 switch (priv->type) { in read_scc_data()
700 return inb(priv->scc_data); in read_scc_data()
702 return inb_p(priv->scc_data); in read_scc_data()
704 spin_lock_irqsave(priv->register_lock, flags); in read_scc_data()
705 outb_p(0, priv->card_base + PI_DREQ_MASK); in read_scc_data()
706 rc = inb_p(priv->scc_data); in read_scc_data()
707 outb(1, priv->card_base + PI_DREQ_MASK); in read_scc_data()
708 spin_unlock_irqrestore(priv->register_lock, flags); in read_scc_data()
716 struct scc_priv *priv = dev->ml_priv; in scc_open() local
717 struct scc_info *info = priv->info; in scc_open()
718 int card_base = priv->card_base; in scc_open()
729 if (priv->param.dma >= 0) { in scc_open()
730 if (request_dma(priv->param.dma, "dmascc")) { in scc_open()
736 clear_dma_ff(priv->param.dma); in scc_open()
742 priv->rx_ptr = 0; in scc_open()
743 priv->rx_over = 0; in scc_open()
744 priv->rx_head = priv->rx_tail = priv->rx_count = 0; in scc_open()
745 priv->state = IDLE; in scc_open()
746 priv->tx_head = priv->tx_tail = priv->tx_count = 0; in scc_open()
747 priv->tx_ptr = 0; in scc_open()
750 write_scc(priv, R9, (priv->channel ? CHRB : CHRA) | MIE | NV); in scc_open()
752 write_scc(priv, R4, SDLC | X1CLK); in scc_open()
754 write_scc(priv, R1, EXT_INT_ENAB | WT_FN_RDYFN); in scc_open()
756 write_scc(priv, R3, Rx8); in scc_open()
758 write_scc(priv, R5, Tx8); in scc_open()
760 write_scc(priv, R6, 0); in scc_open()
762 write_scc(priv, R7, FLAG); in scc_open()
763 switch (priv->chip) { in scc_open()
766 write_scc(priv, R15, SHDLCE); in scc_open()
768 write_scc(priv, R7, AUTOEOM); in scc_open()
769 write_scc(priv, R15, 0); in scc_open()
773 write_scc(priv, R15, SHDLCE); in scc_open()
793 if (priv->param.dma >= 0) { in scc_open()
794 if (priv->type == TYPE_TWIN) in scc_open()
795 write_scc(priv, R7, AUTOEOM | TXFIFOE); in scc_open()
797 write_scc(priv, R7, AUTOEOM); in scc_open()
799 write_scc(priv, R7, AUTOEOM | RXFIFOH); in scc_open()
801 write_scc(priv, R15, 0); in scc_open()
805 write_scc(priv, R10, CRCPS | (priv->param.nrzi ? NRZI : NRZ)); in scc_open()
808 if (priv->param.brg_tc >= 0) { in scc_open()
810 write_scc(priv, R12, priv->param.brg_tc & 0xFF); in scc_open()
811 write_scc(priv, R13, (priv->param.brg_tc >> 8) & 0xFF); in scc_open()
814 write_scc(priv, R14, SSBR | DTRREQ | BRSRC | BRENABL); in scc_open()
816 write_scc(priv, R14, SEARCH | DTRREQ | BRSRC | BRENABL); in scc_open()
819 write_scc(priv, R14, DTRREQ | BRSRC); in scc_open()
823 if (priv->type == TYPE_TWIN) { in scc_open()
826 ~(priv->channel ? TWIN_EXTCLKB : TWIN_EXTCLKA)), in scc_open()
829 write_scc(priv, R11, priv->param.clocks); in scc_open()
830 if ((priv->type == TYPE_TWIN) && !(priv->param.clocks & TRxCOI)) { in scc_open()
833 (priv->channel ? TWIN_EXTCLKB : TWIN_EXTCLKA)), in scc_open()
838 if (priv->type == TYPE_TWIN) { in scc_open()
841 (priv->channel ? TWIN_DTRB_ON : TWIN_DTRA_ON)), in scc_open()
846 priv->rr0 = read_scc(priv, R0); in scc_open()
848 write_scc(priv, R15, DCDIE); in scc_open()
858 struct scc_priv *priv = dev->ml_priv; in scc_close() local
859 struct scc_info *info = priv->info; in scc_close()
860 int card_base = priv->card_base; in scc_close()
864 if (priv->type == TYPE_TWIN) { in scc_close()
867 (priv->channel ? ~TWIN_DTRB_ON : ~TWIN_DTRA_ON)), in scc_close()
872 write_scc(priv, R9, (priv->channel ? CHRB : CHRA) | MIE | NV); in scc_close()
873 if (priv->param.dma >= 0) { in scc_close()
874 if (priv->type == TYPE_TWIN) in scc_close()
876 free_dma(priv->param.dma); in scc_close()
887 struct scc_priv *priv = dev->ml_priv; in scc_siocdevprivate() local
891 if (copy_to_user(data, &priv->param, sizeof(struct scc_param))) in scc_siocdevprivate()
899 if (copy_from_user(&priv->param, data, in scc_siocdevprivate()
911 struct scc_priv *priv = dev->ml_priv; in scc_send_packet() local
922 i = priv->tx_head; in scc_send_packet()
923 skb_copy_from_linear_data_offset(skb, 1, priv->tx_buf[i], skb->len - 1); in scc_send_packet()
924 priv->tx_len[i] = skb->len - 1; in scc_send_packet()
928 spin_lock_irqsave(&priv->ring_lock, flags); in scc_send_packet()
930 priv->tx_head = (i + 1) % NUM_TX_BUF; in scc_send_packet()
931 priv->tx_count++; in scc_send_packet()
936 if (priv->tx_count < NUM_TX_BUF) in scc_send_packet()
940 if (priv->state == IDLE) { in scc_send_packet()
942 priv->state = TX_HEAD; in scc_send_packet()
943 priv->tx_start = jiffies; in scc_send_packet()
944 write_scc(priv, R5, TxCRC_ENAB | RTS | TxENAB | Tx8); in scc_send_packet()
945 write_scc(priv, R15, 0); in scc_send_packet()
946 start_timer(priv, priv->param.txdelay, 0); in scc_send_packet()
950 spin_unlock_irqrestore(&priv->ring_lock, flags); in scc_send_packet()
964 static inline void tx_on(struct scc_priv *priv) in tx_on() argument
969 if (priv->param.dma >= 0) { in tx_on()
970 n = (priv->chip == Z85230) ? 3 : 1; in tx_on()
973 set_dma_mode(priv->param.dma, DMA_MODE_WRITE); in tx_on()
974 set_dma_addr(priv->param.dma, in tx_on()
975 virt_to_bus(priv->tx_buf[priv->tx_tail]) + n); in tx_on()
976 set_dma_count(priv->param.dma, in tx_on()
977 priv->tx_len[priv->tx_tail] - n); in tx_on()
980 write_scc(priv, R15, TxUIE); in tx_on()
982 if (priv->type == TYPE_TWIN) in tx_on()
983 outb((priv->param.dma == in tx_on()
985 priv->card_base + TWIN_DMA_CFG); in tx_on()
987 write_scc(priv, R1, in tx_on()
991 spin_lock_irqsave(priv->register_lock, flags); in tx_on()
993 write_scc_data(priv, in tx_on()
994 priv->tx_buf[priv->tx_tail][i], 1); in tx_on()
995 enable_dma(priv->param.dma); in tx_on()
996 spin_unlock_irqrestore(priv->register_lock, flags); in tx_on()
998 write_scc(priv, R15, TxUIE); in tx_on()
999 write_scc(priv, R1, in tx_on()
1001 tx_isr(priv); in tx_on()
1004 if (priv->chip == Z8530) in tx_on()
1005 write_scc(priv, R0, RES_EOM_L); in tx_on()
1009 static inline void rx_on(struct scc_priv *priv) in rx_on() argument
1014 while (read_scc(priv, R0) & Rx_CH_AV) in rx_on()
1015 read_scc_data(priv); in rx_on()
1016 priv->rx_over = 0; in rx_on()
1017 if (priv->param.dma >= 0) { in rx_on()
1020 set_dma_mode(priv->param.dma, DMA_MODE_READ); in rx_on()
1021 set_dma_addr(priv->param.dma, in rx_on()
1022 virt_to_bus(priv->rx_buf[priv->rx_head])); in rx_on()
1023 set_dma_count(priv->param.dma, BUF_SIZE); in rx_on()
1025 enable_dma(priv->param.dma); in rx_on()
1027 if (priv->type == TYPE_TWIN) { in rx_on()
1028 outb((priv->param.dma == in rx_on()
1030 priv->card_base + TWIN_DMA_CFG); in rx_on()
1033 write_scc(priv, R1, EXT_INT_ENAB | INT_ERR_Rx | in rx_on()
1037 priv->rx_ptr = 0; in rx_on()
1039 write_scc(priv, R1, EXT_INT_ENAB | INT_ALL_Rx | WT_RDY_RT | in rx_on()
1042 write_scc(priv, R0, ERR_RES); in rx_on()
1043 write_scc(priv, R3, RxENABLE | Rx8 | RxCRC_ENAB); in rx_on()
1047 static inline void rx_off(struct scc_priv *priv) in rx_off() argument
1050 write_scc(priv, R3, Rx8); in rx_off()
1052 if (priv->param.dma >= 0 && priv->type == TYPE_TWIN) in rx_off()
1053 outb(0, priv->card_base + TWIN_DMA_CFG); in rx_off()
1055 write_scc(priv, R1, EXT_INT_ENAB | WT_FN_RDYFN); in rx_off()
1057 if (priv->param.dma >= 0) in rx_off()
1058 disable_dma(priv->param.dma); in rx_off()
1062 static void start_timer(struct scc_priv *priv, int t, int r15) in start_timer() argument
1064 outb(priv->tmr_mode, priv->tmr_ctrl); in start_timer()
1066 tm_isr(priv); in start_timer()
1068 outb(t & 0xFF, priv->tmr_cnt); in start_timer()
1069 outb((t >> 8) & 0xFF, priv->tmr_cnt); in start_timer()
1070 if (priv->type != TYPE_TWIN) { in start_timer()
1071 write_scc(priv, R15, r15 | CTSIE); in start_timer()
1072 priv->rr0 |= CTS; in start_timer()
1089 while ((is = read_scc(&info->priv[0], R3)) && i--) { in z8530_isr()
1091 rx_isr(&info->priv[0]); in z8530_isr()
1093 tx_isr(&info->priv[0]); in z8530_isr()
1095 es_isr(&info->priv[0]); in z8530_isr()
1097 rx_isr(&info->priv[1]); in z8530_isr()
1099 tx_isr(&info->priv[1]); in z8530_isr()
1101 es_isr(&info->priv[1]); in z8530_isr()
1103 write_scc(&info->priv[0], R0, RES_H_IUS); in z8530_isr()
1119 spin_lock(info->priv[0].register_lock); in scc_isr()
1132 if (info->priv[0].type == TYPE_TWIN) { in scc_isr()
1133 int is, card_base = info->priv[0].card_base; in scc_isr()
1140 tm_isr(&info->priv[0]); in scc_isr()
1143 tm_isr(&info->priv[1]); in scc_isr()
1148 spin_unlock(info->priv[0].register_lock); in scc_isr()
1153 static void rx_isr(struct scc_priv *priv) in rx_isr() argument
1155 if (priv->param.dma >= 0) { in rx_isr()
1157 special_condition(priv, read_scc(priv, R1)); in rx_isr()
1158 write_scc(priv, R0, ERR_RES); in rx_isr()
1163 while (read_scc(priv, R0) & Rx_CH_AV) { in rx_isr()
1164 rc = read_scc(priv, R1); in rx_isr()
1165 if (priv->rx_ptr < BUF_SIZE) in rx_isr()
1166 priv->rx_buf[priv->rx_head][priv-> in rx_isr()
1168 read_scc_data(priv); in rx_isr()
1170 priv->rx_over = 2; in rx_isr()
1171 read_scc_data(priv); in rx_isr()
1173 special_condition(priv, rc); in rx_isr()
1179 static void special_condition(struct scc_priv *priv, int rc) in special_condition() argument
1188 priv->rx_over = 1; in special_condition()
1189 if (priv->param.dma < 0) in special_condition()
1190 write_scc(priv, R0, ERR_RES); in special_condition()
1193 if (priv->param.dma >= 0) { in special_condition()
1195 cb = BUF_SIZE - get_dma_residue(priv->param.dma) - in special_condition()
1199 cb = priv->rx_ptr - 2; in special_condition()
1201 if (priv->rx_over) { in special_condition()
1203 priv->dev->stats.rx_errors++; in special_condition()
1204 if (priv->rx_over == 2) in special_condition()
1205 priv->dev->stats.rx_length_errors++; in special_condition()
1207 priv->dev->stats.rx_fifo_errors++; in special_condition()
1208 priv->rx_over = 0; in special_condition()
1212 priv->dev->stats.rx_errors++; in special_condition()
1213 priv->dev->stats.rx_crc_errors++; in special_condition()
1217 if (priv->rx_count < NUM_RX_BUF - 1) { in special_condition()
1219 priv->rx_len[priv->rx_head] = cb; in special_condition()
1220 priv->rx_head = in special_condition()
1221 (priv->rx_head + in special_condition()
1223 priv->rx_count++; in special_condition()
1224 schedule_work(&priv->rx_work); in special_condition()
1226 priv->dev->stats.rx_errors++; in special_condition()
1227 priv->dev->stats.rx_over_errors++; in special_condition()
1232 if (priv->param.dma >= 0) { in special_condition()
1234 set_dma_addr(priv->param.dma, in special_condition()
1235 virt_to_bus(priv->rx_buf[priv->rx_head])); in special_condition()
1236 set_dma_count(priv->param.dma, BUF_SIZE); in special_condition()
1239 priv->rx_ptr = 0; in special_condition()
1247 struct scc_priv *priv = container_of(ugli_api, struct scc_priv, rx_work); in rx_bh() local
1248 int i = priv->rx_tail; in rx_bh()
1254 spin_lock_irqsave(&priv->ring_lock, flags); in rx_bh()
1255 while (priv->rx_count) { in rx_bh()
1256 spin_unlock_irqrestore(&priv->ring_lock, flags); in rx_bh()
1257 cb = priv->rx_len[i]; in rx_bh()
1262 priv->dev->stats.rx_dropped++; in rx_bh()
1267 memcpy(&data[1], priv->rx_buf[i], cb); in rx_bh()
1268 skb->protocol = ax25_type_trans(skb, priv->dev); in rx_bh()
1270 priv->dev->stats.rx_packets++; in rx_bh()
1271 priv->dev->stats.rx_bytes += cb; in rx_bh()
1273 spin_lock_irqsave(&priv->ring_lock, flags); in rx_bh()
1275 priv->rx_tail = i = (i + 1) % NUM_RX_BUF; in rx_bh()
1276 priv->rx_count--; in rx_bh()
1278 spin_unlock_irqrestore(&priv->ring_lock, flags); in rx_bh()
1282 static void tx_isr(struct scc_priv *priv) in tx_isr() argument
1284 int i = priv->tx_tail, p = priv->tx_ptr; in tx_isr()
1288 if (p == priv->tx_len[i]) { in tx_isr()
1289 write_scc(priv, R0, RES_Tx_P); in tx_isr()
1294 while ((read_scc(priv, R0) & Tx_BUF_EMP) && p < priv->tx_len[i]) { in tx_isr()
1295 write_scc_data(priv, priv->tx_buf[i][p++], 0); in tx_isr()
1299 if (!priv->tx_ptr && p && priv->chip == Z8530) in tx_isr()
1300 write_scc(priv, R0, RES_EOM_L); in tx_isr()
1302 priv->tx_ptr = p; in tx_isr()
1306 static void es_isr(struct scc_priv *priv) in es_isr() argument
1312 rr0 = read_scc(priv, R0); in es_isr()
1313 write_scc(priv, R0, RES_EXT_INT); in es_isr()
1314 drr0 = priv->rr0 ^ rr0; in es_isr()
1315 priv->rr0 = rr0; in es_isr()
1319 if (priv->state == TX_DATA) { in es_isr()
1321 i = priv->tx_tail; in es_isr()
1322 if (priv->param.dma >= 0) { in es_isr()
1323 disable_dma(priv->param.dma); in es_isr()
1325 res = get_dma_residue(priv->param.dma); in es_isr()
1328 res = priv->tx_len[i] - priv->tx_ptr; in es_isr()
1329 priv->tx_ptr = 0; in es_isr()
1332 if (priv->param.dma >= 0 && priv->type == TYPE_TWIN) in es_isr()
1333 outb(0, priv->card_base + TWIN_DMA_CFG); in es_isr()
1335 write_scc(priv, R1, EXT_INT_ENAB | WT_FN_RDYFN); in es_isr()
1338 priv->dev->stats.tx_errors++; in es_isr()
1339 priv->dev->stats.tx_fifo_errors++; in es_isr()
1341 write_scc(priv, R0, RES_EXT_INT); in es_isr()
1342 write_scc(priv, R0, RES_EXT_INT); in es_isr()
1345 priv->dev->stats.tx_packets++; in es_isr()
1346 priv->dev->stats.tx_bytes += priv->tx_len[i]; in es_isr()
1348 priv->tx_tail = (i + 1) % NUM_TX_BUF; in es_isr()
1349 priv->tx_count--; in es_isr()
1351 netif_wake_queue(priv->dev); in es_isr()
1354 write_scc(priv, R15, 0); in es_isr()
1355 if (priv->tx_count && in es_isr()
1356 (jiffies - priv->tx_start) < priv->param.txtimeout) { in es_isr()
1357 priv->state = TX_PAUSE; in es_isr()
1358 start_timer(priv, priv->param.txpause, 0); in es_isr()
1360 priv->state = TX_TAIL; in es_isr()
1361 start_timer(priv, priv->param.txtail, 0); in es_isr()
1368 switch (priv->state) { in es_isr()
1371 priv->state = DCD_ON; in es_isr()
1372 write_scc(priv, R15, 0); in es_isr()
1373 start_timer(priv, priv->param.dcdon, 0); in es_isr()
1376 switch (priv->state) { in es_isr()
1378 rx_off(priv); in es_isr()
1379 priv->state = DCD_OFF; in es_isr()
1380 write_scc(priv, R15, 0); in es_isr()
1381 start_timer(priv, priv->param.dcdoff, 0); in es_isr()
1387 if ((drr0 & CTS) && (~rr0 & CTS) && priv->type != TYPE_TWIN) in es_isr()
1388 tm_isr(priv); in es_isr()
1393 static void tm_isr(struct scc_priv *priv) in tm_isr() argument
1395 switch (priv->state) { in tm_isr()
1398 tx_on(priv); in tm_isr()
1399 priv->state = TX_DATA; in tm_isr()
1402 write_scc(priv, R5, TxCRC_ENAB | Tx8); in tm_isr()
1403 priv->state = RTS_OFF; in tm_isr()
1404 if (priv->type != TYPE_TWIN) in tm_isr()
1405 write_scc(priv, R15, 0); in tm_isr()
1406 start_timer(priv, priv->param.rtsoff, 0); in tm_isr()
1409 write_scc(priv, R15, DCDIE); in tm_isr()
1410 priv->rr0 = read_scc(priv, R0); in tm_isr()
1411 if (priv->rr0 & DCD) { in tm_isr()
1412 priv->dev->stats.collisions++; in tm_isr()
1413 rx_on(priv); in tm_isr()
1414 priv->state = RX_ON; in tm_isr()
1416 priv->state = WAIT; in tm_isr()
1417 start_timer(priv, priv->param.waittime, DCDIE); in tm_isr()
1421 if (priv->tx_count) { in tm_isr()
1422 priv->state = TX_HEAD; in tm_isr()
1423 priv->tx_start = jiffies; in tm_isr()
1424 write_scc(priv, R5, in tm_isr()
1426 write_scc(priv, R15, 0); in tm_isr()
1427 start_timer(priv, priv->param.txdelay, 0); in tm_isr()
1429 priv->state = IDLE; in tm_isr()
1430 if (priv->type != TYPE_TWIN) in tm_isr()
1431 write_scc(priv, R15, DCDIE); in tm_isr()
1436 write_scc(priv, R15, DCDIE); in tm_isr()
1437 priv->rr0 = read_scc(priv, R0); in tm_isr()
1438 if (priv->rr0 & DCD) { in tm_isr()
1439 rx_on(priv); in tm_isr()
1440 priv->state = RX_ON; in tm_isr()
1442 priv->state = WAIT; in tm_isr()
1443 start_timer(priv, in tm_isr()
1444 random() / priv->param.persist * in tm_isr()
1445 priv->param.slottime, DCDIE); in tm_isr()