Lines Matching refs:phydev
51 static int bcm7xxx_28nm_d0_afe_config_init(struct phy_device *phydev) in bcm7xxx_28nm_d0_afe_config_init() argument
54 bcm_phy_write_misc(phydev, AFE_RXCONFIG_0, 0xeb15); in bcm7xxx_28nm_d0_afe_config_init()
57 bcm_phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9b2f); in bcm7xxx_28nm_d0_afe_config_init()
60 bcm_phy_write_misc(phydev, AFE_RXCONFIG_2, 0x2003); in bcm7xxx_28nm_d0_afe_config_init()
63 bcm_phy_write_misc(phydev, AFE_RX_LP_COUNTER, 0x7fc0); in bcm7xxx_28nm_d0_afe_config_init()
66 bcm_phy_write_misc(phydev, AFE_TX_CONFIG, 0x431); in bcm7xxx_28nm_d0_afe_config_init()
69 bcm_phy_write_misc(phydev, AFE_VDCA_ICTRL_0, 0xa7da); in bcm7xxx_28nm_d0_afe_config_init()
72 bcm_phy_write_misc(phydev, AFE_VDAC_OTHERS_0, 0xa020); in bcm7xxx_28nm_d0_afe_config_init()
77 bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x00e3); in bcm7xxx_28nm_d0_afe_config_init()
80 phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010); in bcm7xxx_28nm_d0_afe_config_init()
83 bcm_phy_write_misc(phydev, DSP_TAP10, 0x011b); in bcm7xxx_28nm_d0_afe_config_init()
86 bcm_phy_r_rc_cal_reset(phydev); in bcm7xxx_28nm_d0_afe_config_init()
91 static int bcm7xxx_28nm_e0_plus_afe_config_init(struct phy_device *phydev) in bcm7xxx_28nm_e0_plus_afe_config_init() argument
94 bcm_phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9b2f); in bcm7xxx_28nm_e0_plus_afe_config_init()
97 bcm_phy_write_misc(phydev, AFE_TX_CONFIG, 0x431); in bcm7xxx_28nm_e0_plus_afe_config_init()
100 bcm_phy_write_misc(phydev, AFE_VDCA_ICTRL_0, 0xa7da); in bcm7xxx_28nm_e0_plus_afe_config_init()
105 bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x00e3); in bcm7xxx_28nm_e0_plus_afe_config_init()
108 phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010); in bcm7xxx_28nm_e0_plus_afe_config_init()
111 bcm_phy_write_misc(phydev, DSP_TAP10, 0x011b); in bcm7xxx_28nm_e0_plus_afe_config_init()
114 bcm_phy_r_rc_cal_reset(phydev); in bcm7xxx_28nm_e0_plus_afe_config_init()
119 static int bcm7xxx_28nm_a0_patch_afe_config_init(struct phy_device *phydev) in bcm7xxx_28nm_a0_patch_afe_config_init() argument
122 bcm_phy_write_misc(phydev, AFE_RXCONFIG_2, 0xd003); in bcm7xxx_28nm_a0_patch_afe_config_init()
125 bcm_phy_write_misc(phydev, DSP_TAP10, 0x791b); in bcm7xxx_28nm_a0_patch_afe_config_init()
128 bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x10e3); in bcm7xxx_28nm_a0_patch_afe_config_init()
131 bcm_phy_write_misc(phydev, 0x21, 0x2, 0x87f6); in bcm7xxx_28nm_a0_patch_afe_config_init()
134 bcm_phy_write_misc(phydev, 0x22, 0x2, 0x017d); in bcm7xxx_28nm_a0_patch_afe_config_init()
137 bcm_phy_write_misc(phydev, 0x26, 0x2, 0x0015); in bcm7xxx_28nm_a0_patch_afe_config_init()
139 bcm_phy_r_rc_cal_reset(phydev); in bcm7xxx_28nm_a0_patch_afe_config_init()
144 static int bcm7xxx_28nm_config_init(struct phy_device *phydev) in bcm7xxx_28nm_config_init() argument
146 u8 rev = PHY_BRCM_7XXX_REV(phydev->dev_flags); in bcm7xxx_28nm_config_init()
147 u8 patch = PHY_BRCM_7XXX_PATCH(phydev->dev_flags); in bcm7xxx_28nm_config_init()
155 rev = phydev->phy_id & ~phydev->drv->phy_id_mask; in bcm7xxx_28nm_config_init()
158 phydev_name(phydev), phydev->drv->name, rev, patch); in bcm7xxx_28nm_config_init()
165 phy_read(phydev, MII_BMSR); in bcm7xxx_28nm_config_init()
170 ret = bcm_phy_28nm_a0b0_afe_config_init(phydev); in bcm7xxx_28nm_config_init()
173 ret = bcm7xxx_28nm_d0_afe_config_init(phydev); in bcm7xxx_28nm_config_init()
179 ret = bcm7xxx_28nm_e0_plus_afe_config_init(phydev); in bcm7xxx_28nm_config_init()
182 ret = bcm7xxx_28nm_a0_patch_afe_config_init(phydev); in bcm7xxx_28nm_config_init()
191 ret = bcm_phy_enable_jumbo(phydev); in bcm7xxx_28nm_config_init()
195 ret = bcm_phy_downshift_get(phydev, &count); in bcm7xxx_28nm_config_init()
200 ret = bcm_phy_set_eee(phydev, count == DOWNSHIFT_DEV_DISABLE); in bcm7xxx_28nm_config_init()
204 return bcm_phy_enable_apd(phydev, true); in bcm7xxx_28nm_config_init()
207 static int bcm7xxx_28nm_resume(struct phy_device *phydev) in bcm7xxx_28nm_resume() argument
212 ret = bcm7xxx_28nm_config_init(phydev); in bcm7xxx_28nm_resume()
221 return genphy_config_aneg(phydev); in bcm7xxx_28nm_resume()
255 static int bcm7xxx_28nm_ephy_01_afe_config_init(struct phy_device *phydev) in bcm7xxx_28nm_ephy_01_afe_config_init() argument
260 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, in bcm7xxx_28nm_ephy_01_afe_config_init()
266 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_BIAS_TRIM, 0x3BE0); in bcm7xxx_28nm_ephy_01_afe_config_init()
271 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, in bcm7xxx_28nm_ephy_01_afe_config_init()
275 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT, in bcm7xxx_28nm_ephy_01_afe_config_init()
281 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, in bcm7xxx_28nm_ephy_01_afe_config_init()
285 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT, in bcm7xxx_28nm_ephy_01_afe_config_init()
292 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0, in bcm7xxx_28nm_ephy_01_afe_config_init()
301 static int bcm7xxx_28nm_ephy_apd_enable(struct phy_device *phydev) in bcm7xxx_28nm_ephy_apd_enable() argument
306 ret = phy_set_clr_bits(phydev, MII_BRCM_FET_BRCMTEST, in bcm7xxx_28nm_ephy_apd_enable()
312 ret = phy_set_clr_bits(phydev, MII_BRCM_FET_SHDW_AUXSTAT2, in bcm7xxx_28nm_ephy_apd_enable()
318 ret = phy_set_clr_bits(phydev, MII_BRCM_FET_BRCMTEST, 0, in bcm7xxx_28nm_ephy_apd_enable()
326 static int bcm7xxx_28nm_ephy_eee_enable(struct phy_device *phydev) in bcm7xxx_28nm_ephy_eee_enable() argument
331 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, in bcm7xxx_28nm_ephy_eee_enable()
337 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, in bcm7xxx_28nm_ephy_eee_enable()
341 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT, in bcm7xxx_28nm_ephy_eee_enable()
347 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, in bcm7xxx_28nm_ephy_eee_enable()
351 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT, in bcm7xxx_28nm_ephy_eee_enable()
356 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, in bcm7xxx_28nm_ephy_eee_enable()
360 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT, in bcm7xxx_28nm_ephy_eee_enable()
366 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, in bcm7xxx_28nm_ephy_eee_enable()
370 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT, in bcm7xxx_28nm_ephy_eee_enable()
377 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0, in bcm7xxx_28nm_ephy_eee_enable()
383 phy_write(phydev, MII_BMCR, in bcm7xxx_28nm_ephy_eee_enable()
389 static int bcm7xxx_28nm_ephy_config_init(struct phy_device *phydev) in bcm7xxx_28nm_ephy_config_init() argument
391 u8 rev = phydev->phy_id & ~phydev->drv->phy_id_mask; in bcm7xxx_28nm_ephy_config_init()
395 phydev_name(phydev), phydev->drv->name, rev); in bcm7xxx_28nm_ephy_config_init()
402 phy_read(phydev, MII_BMSR); in bcm7xxx_28nm_ephy_config_init()
406 ret = bcm7xxx_28nm_ephy_01_afe_config_init(phydev); in bcm7xxx_28nm_ephy_config_init()
411 ret = bcm7xxx_28nm_ephy_eee_enable(phydev); in bcm7xxx_28nm_ephy_config_init()
415 return bcm7xxx_28nm_ephy_apd_enable(phydev); in bcm7xxx_28nm_ephy_config_init()
418 static int bcm7xxx_16nm_ephy_afe_config(struct phy_device *phydev) in bcm7xxx_16nm_ephy_afe_config() argument
423 tmp = genphy_soft_reset(phydev); in bcm7xxx_16nm_ephy_afe_config()
428 bcm_phy_write_exp_sel(phydev, 0x0003, 0x0006); in bcm7xxx_16nm_ephy_afe_config()
430 bcm_phy_write_exp_sel(phydev, 0x0003, 0x0000); in bcm7xxx_16nm_ephy_afe_config()
433 bcm_phy_write_misc(phydev, 0x0030, 0x0001, 0x0000); in bcm7xxx_16nm_ephy_afe_config()
434 bcm_phy_write_misc(phydev, 0x0031, 0x0000, 0x044a); in bcm7xxx_16nm_ephy_afe_config()
437 bcm_phy_write_misc(phydev, 0x0033, 0x0002, 0x71a1); in bcm7xxx_16nm_ephy_afe_config()
439 bcm_phy_write_misc(phydev, 0x0033, 0x0001, 0x8000); in bcm7xxx_16nm_ephy_afe_config()
442 bcm_phy_write_misc(phydev, 0x0031, 0x0001, 0x2f68); in bcm7xxx_16nm_ephy_afe_config()
443 bcm_phy_write_misc(phydev, 0x0031, 0x0002, 0x0000); in bcm7xxx_16nm_ephy_afe_config()
448 bcm_phy_write_misc(phydev, 0x0030, 0x0003, 0xc036); in bcm7xxx_16nm_ephy_afe_config()
451 bcm_phy_write_misc(phydev, 0x0032, 0x0003, 0x0000); in bcm7xxx_16nm_ephy_afe_config()
453 bcm_phy_write_misc(phydev, 0x0033, 0x0000, 0x0002); in bcm7xxx_16nm_ephy_afe_config()
455 bcm_phy_write_misc(phydev, 0x0030, 0x0002, 0x01c0); in bcm7xxx_16nm_ephy_afe_config()
457 bcm_phy_write_misc(phydev, 0x0030, 0x0001, 0x0001); in bcm7xxx_16nm_ephy_afe_config()
460 bcm_phy_write_misc(phydev, 0x0038, 0x0000, 0x0010); in bcm7xxx_16nm_ephy_afe_config()
463 bcm_phy_write_misc(phydev, 0x0039, 0x0003, 0x0038); in bcm7xxx_16nm_ephy_afe_config()
464 bcm_phy_write_misc(phydev, 0x0039, 0x0003, 0x003b); in bcm7xxx_16nm_ephy_afe_config()
466 bcm_phy_write_misc(phydev, 0x0039, 0x0003, 0x003f); in bcm7xxx_16nm_ephy_afe_config()
470 bcm_phy_write_misc(phydev, 0x0039, 0x0001, 0x1c82); in bcm7xxx_16nm_ephy_afe_config()
472 bcm_phy_write_misc(phydev, 0x0039, 0x0001, 0x9e82); in bcm7xxx_16nm_ephy_afe_config()
475 bcm_phy_write_misc(phydev, 0x0039, 0x0001, 0x9f82); in bcm7xxx_16nm_ephy_afe_config()
478 bcm_phy_write_misc(phydev, 0x0039, 0x0001, 0x9e86); in bcm7xxx_16nm_ephy_afe_config()
481 bcm_phy_write_misc(phydev, 0x0039, 0x0001, 0x9f86); in bcm7xxx_16nm_ephy_afe_config()
485 bcm_phy_write_misc(phydev, 0x0038, 0x0001, 0xe7ea); in bcm7xxx_16nm_ephy_afe_config()
487 bcm_phy_write_misc(phydev, 0x0038, 0x0002, 0xede0); in bcm7xxx_16nm_ephy_afe_config()
490 tmp = bcm_phy_read_exp(phydev, 0x00a9); in bcm7xxx_16nm_ephy_afe_config()
505 bcm_phy_write_misc(phydev, 0x0039, 0x0003, tmp); in bcm7xxx_16nm_ephy_afe_config()
507 bcm_phy_write_misc(phydev, 0x0038, 0x0001, 0xe7e4); in bcm7xxx_16nm_ephy_afe_config()
511 bcm_phy_write_misc(phydev, 0x003b, 0x0000, 0x8002); in bcm7xxx_16nm_ephy_afe_config()
513 bcm_phy_write_misc(phydev, 0x003c, 0x0003, 0xf882); in bcm7xxx_16nm_ephy_afe_config()
517 bcm_phy_write_misc(phydev, 0x003d, 0x0000, 0x3201); in bcm7xxx_16nm_ephy_afe_config()
519 bcm_phy_write_misc(phydev, 0x003a, 0x0002, 0x0c00); in bcm7xxx_16nm_ephy_afe_config()
524 bcm_phy_write_misc(phydev, 0x003a, 0x0001, 0x0020); in bcm7xxx_16nm_ephy_afe_config()
527 bcm_phy_write_misc(phydev, 0x003b, 0x0002, 0x0000); in bcm7xxx_16nm_ephy_afe_config()
528 bcm_phy_write_misc(phydev, 0x003b, 0x0003, 0x0000); in bcm7xxx_16nm_ephy_afe_config()
531 bcm_phy_write_misc(phydev, 0x003a, 0x0003, 0x0800); in bcm7xxx_16nm_ephy_afe_config()
537 bcm_phy_write_misc(phydev, 0x003a, 0x0001, 0x0000); in bcm7xxx_16nm_ephy_afe_config()
541 tmp = bcm_phy_read_misc(phydev, 0x003d, 0x0001); in bcm7xxx_16nm_ephy_afe_config()
546 bcm_phy_write_misc(phydev, 0x003d, 0x0001, tmp); in bcm7xxx_16nm_ephy_afe_config()
547 bcm_phy_write_misc(phydev, 0x003d, 0x0002, tmp); in bcm7xxx_16nm_ephy_afe_config()
549 tmp = bcm_phy_read_misc(phydev, 0x003d, 0x0000); in bcm7xxx_16nm_ephy_afe_config()
554 bcm_phy_write_misc(phydev, 0x003d, 0x0000, tmp); in bcm7xxx_16nm_ephy_afe_config()
559 static int bcm7xxx_16nm_ephy_config_init(struct phy_device *phydev) in bcm7xxx_16nm_ephy_config_init() argument
563 ret = bcm7xxx_16nm_ephy_afe_config(phydev); in bcm7xxx_16nm_ephy_config_init()
567 ret = bcm_phy_set_eee(phydev, true); in bcm7xxx_16nm_ephy_config_init()
571 ret = bcm_phy_read_shadow(phydev, BCM54XX_SHD_SCR3); in bcm7xxx_16nm_ephy_config_init()
583 ret = bcm_phy_write_shadow(phydev, BCM54XX_SHD_SCR3, val); in bcm7xxx_16nm_ephy_config_init()
587 return bcm_phy_enable_apd(phydev, true); in bcm7xxx_16nm_ephy_config_init()
590 static int bcm7xxx_16nm_ephy_resume(struct phy_device *phydev) in bcm7xxx_16nm_ephy_resume() argument
595 ret = bcm7xxx_16nm_ephy_config_init(phydev); in bcm7xxx_16nm_ephy_resume()
599 return genphy_config_aneg(phydev); in bcm7xxx_16nm_ephy_resume()
629 static int bcm7xxx_28nm_ephy_read_mmd(struct phy_device *phydev, in bcm7xxx_28nm_ephy_read_mmd() argument
640 ret = __phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, in bcm7xxx_28nm_ephy_read_mmd()
646 ret = __phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, shd); in bcm7xxx_28nm_ephy_read_mmd()
650 ret = __phy_read(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT); in bcm7xxx_28nm_ephy_read_mmd()
654 __phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0, in bcm7xxx_28nm_ephy_read_mmd()
659 static int bcm7xxx_28nm_ephy_write_mmd(struct phy_device *phydev, in bcm7xxx_28nm_ephy_write_mmd() argument
670 ret = __phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, in bcm7xxx_28nm_ephy_write_mmd()
676 ret = __phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, shd); in bcm7xxx_28nm_ephy_write_mmd()
681 __phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT, val); in bcm7xxx_28nm_ephy_write_mmd()
685 return __phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0, in bcm7xxx_28nm_ephy_write_mmd()
689 static int bcm7xxx_28nm_ephy_resume(struct phy_device *phydev) in bcm7xxx_28nm_ephy_resume() argument
694 ret = bcm7xxx_28nm_ephy_config_init(phydev); in bcm7xxx_28nm_ephy_resume()
698 return genphy_config_aneg(phydev); in bcm7xxx_28nm_ephy_resume()
701 static int bcm7xxx_config_init(struct phy_device *phydev) in bcm7xxx_config_init() argument
706 phy_write(phydev, MII_BCM7XXX_AUX_MODE, MII_BCM7XXX_64CLK_MDIO); in bcm7xxx_config_init()
707 phy_read(phydev, MII_BCM7XXX_AUX_MODE); in bcm7xxx_config_init()
710 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, in bcm7xxx_config_init()
716 phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0F00); in bcm7xxx_config_init()
720 phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0C00); in bcm7xxx_config_init()
722 phy_write(phydev, MII_BCM7XXX_100TX_FALSE_CAR, 0x7555); in bcm7xxx_config_init()
725 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0, MII_BCM7XXX_SHD_MODE_2); in bcm7xxx_config_init()
735 static int bcm7xxx_suspend(struct phy_device *phydev) in bcm7xxx_suspend() argument
752 ret = phy_write(phydev, in bcm7xxx_suspend()
762 static int bcm7xxx_28nm_get_tunable(struct phy_device *phydev, in bcm7xxx_28nm_get_tunable() argument
768 return bcm_phy_downshift_get(phydev, (u8 *)data); in bcm7xxx_28nm_get_tunable()
774 static int bcm7xxx_28nm_set_tunable(struct phy_device *phydev, in bcm7xxx_28nm_set_tunable() argument
783 ret = bcm_phy_downshift_set(phydev, count); in bcm7xxx_28nm_set_tunable()
796 ret = bcm_phy_set_eee(phydev, count == DOWNSHIFT_DEV_DISABLE); in bcm7xxx_28nm_set_tunable()
800 return genphy_restart_aneg(phydev); in bcm7xxx_28nm_set_tunable()
803 static void bcm7xxx_28nm_get_phy_stats(struct phy_device *phydev, in bcm7xxx_28nm_get_phy_stats() argument
806 struct bcm7xxx_phy_priv *priv = phydev->priv; in bcm7xxx_28nm_get_phy_stats()
808 bcm_phy_get_stats(phydev, priv->stats, stats, data); in bcm7xxx_28nm_get_phy_stats()
811 static int bcm7xxx_28nm_probe(struct phy_device *phydev) in bcm7xxx_28nm_probe() argument
816 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); in bcm7xxx_28nm_probe()
820 phydev->priv = priv; in bcm7xxx_28nm_probe()
822 priv->stats = devm_kcalloc(&phydev->mdio.dev, in bcm7xxx_28nm_probe()
823 bcm_phy_get_sset_count(phydev), sizeof(u64), in bcm7xxx_28nm_probe()
828 priv->clk = devm_clk_get_optional(&phydev->mdio.dev, NULL); in bcm7xxx_28nm_probe()
842 phy_read(phydev, MII_BMSR); in bcm7xxx_28nm_probe()
847 static void bcm7xxx_28nm_remove(struct phy_device *phydev) in bcm7xxx_28nm_remove() argument
849 struct bcm7xxx_phy_priv *priv = phydev->priv; in bcm7xxx_28nm_remove()