Lines Matching refs:phydev
27 static int phy_ts_base_write(struct phy_device *phydev, u32 regnum, u16 val) in phy_ts_base_write() argument
29 struct vsc8531_private *priv = phydev->priv; in phy_ts_base_write()
31 WARN_ON_ONCE(!mutex_is_locked(&phydev->mdio.bus->mdio_lock)); in phy_ts_base_write()
32 return __mdiobus_write(phydev->mdio.bus, priv->ts_base_addr, regnum, in phy_ts_base_write()
37 static int phy_ts_base_read(struct phy_device *phydev, u32 regnum) in phy_ts_base_read() argument
39 struct vsc8531_private *priv = phydev->priv; in phy_ts_base_read()
41 WARN_ON_ONCE(!mutex_is_locked(&phydev->mdio.bus->mdio_lock)); in phy_ts_base_read()
42 return __mdiobus_read(phydev->mdio.bus, priv->ts_base_addr, regnum); in phy_ts_base_read()
62 static u32 vsc85xx_ts_read_csr(struct phy_device *phydev, enum ts_blk blk, in vsc85xx_ts_read_csr() argument
65 struct vsc8531_private *priv = phydev->priv; in vsc85xx_ts_read_csr()
66 bool base_port = phydev->mdio.addr == priv->ts_base_addr; in vsc85xx_ts_read_csr()
83 phy_lock_mdio_bus(phydev); in vsc85xx_ts_read_csr()
85 phy_ts_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_1588); in vsc85xx_ts_read_csr()
87 phy_ts_base_write(phydev, MSCC_PHY_TS_BIU_ADDR_CNTL, BIU_ADDR_EXE | in vsc85xx_ts_read_csr()
92 val = phy_ts_base_read(phydev, MSCC_PHY_TS_BIU_ADDR_CNTL); in vsc85xx_ts_read_csr()
95 val = phy_ts_base_read(phydev, MSCC_PHY_TS_CSR_DATA_MSB); in vsc85xx_ts_read_csr()
97 val |= phy_ts_base_read(phydev, MSCC_PHY_TS_CSR_DATA_LSB); in vsc85xx_ts_read_csr()
99 phy_ts_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc85xx_ts_read_csr()
101 phy_unlock_mdio_bus(phydev); in vsc85xx_ts_read_csr()
106 static void vsc85xx_ts_write_csr(struct phy_device *phydev, enum ts_blk blk, in vsc85xx_ts_write_csr() argument
109 struct vsc8531_private *priv = phydev->priv; in vsc85xx_ts_write_csr()
110 bool base_port = phydev->mdio.addr == priv->ts_base_addr; in vsc85xx_ts_write_csr()
133 phy_lock_mdio_bus(phydev); in vsc85xx_ts_write_csr()
135 bypass = phy_ts_base_read(phydev, MSCC_PHY_BYPASS_CONTROL); in vsc85xx_ts_write_csr()
137 phy_ts_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_1588); in vsc85xx_ts_write_csr()
140 phy_ts_base_write(phydev, MSCC_PHY_TS_CSR_DATA_MSB, upper); in vsc85xx_ts_write_csr()
142 phy_ts_base_write(phydev, MSCC_PHY_TS_CSR_DATA_LSB, lower); in vsc85xx_ts_write_csr()
144 phy_ts_base_write(phydev, MSCC_PHY_TS_BIU_ADDR_CNTL, BIU_ADDR_EXE | in vsc85xx_ts_write_csr()
149 reg = phy_ts_base_read(phydev, MSCC_PHY_TS_BIU_ADDR_CNTL); in vsc85xx_ts_write_csr()
152 phy_ts_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc85xx_ts_write_csr()
155 phy_ts_base_write(phydev, MSCC_PHY_BYPASS_CONTROL, bypass); in vsc85xx_ts_write_csr()
157 phy_unlock_mdio_bus(phydev); in vsc85xx_ts_write_csr()
166 static int vsc85xx_ts_fsb_init(struct phy_device *phydev) in vsc85xx_ts_fsb_init() argument
195 vsc85xx_ts_write_csr(phydev, EGRESS, MSCC_PHY_ANA_FSB_REG(i), in vsc85xx_ts_fsb_init()
199 vsc85xx_ts_write_csr(phydev, EGRESS, MSCC_PHY_ANA_FSB_REG(3), in vsc85xx_ts_fsb_init()
245 static void vsc85xx_ts_set_latencies(struct phy_device *phydev) in vsc85xx_ts_set_latencies() argument
251 if (!phydev->link) in vsc85xx_ts_set_latencies()
254 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_STALL_LATENCY, in vsc85xx_ts_set_latencies()
255 STALL_EGR_LATENCY(phydev->speed)); in vsc85xx_ts_set_latencies()
257 switch (phydev->speed) { in vsc85xx_ts_set_latencies()
274 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_INGR_LOCAL_LATENCY, in vsc85xx_ts_set_latencies()
277 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in vsc85xx_ts_set_latencies()
280 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_INGR_TSP_CTRL, in vsc85xx_ts_set_latencies()
283 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_LOCAL_LATENCY, in vsc85xx_ts_set_latencies()
286 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_TSP_CTRL); in vsc85xx_ts_set_latencies()
288 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_TSP_CTRL, val); in vsc85xx_ts_set_latencies()
291 static int vsc85xx_ts_disable_flows(struct phy_device *phydev, enum ts_blk blk) in vsc85xx_ts_disable_flows() argument
295 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_NXT_COMP, 0); in vsc85xx_ts_disable_flows()
296 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_UDP_CHKSUM, in vsc85xx_ts_disable_flows()
298 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP2_NXT_PROT_NXT_COMP, 0); in vsc85xx_ts_disable_flows()
299 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP2_NXT_PROT_UDP_CHKSUM, in vsc85xx_ts_disable_flows()
301 vsc85xx_ts_write_csr(phydev, blk, MSCC_PHY_ANA_MPLS_COMP_NXT_COMP, 0); in vsc85xx_ts_disable_flows()
302 vsc85xx_ts_write_csr(phydev, blk, MSCC_PHY_ANA_ETH1_NTX_PROT, 0); in vsc85xx_ts_disable_flows()
303 vsc85xx_ts_write_csr(phydev, blk, MSCC_PHY_ANA_ETH2_NTX_PROT, 0); in vsc85xx_ts_disable_flows()
306 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_ENA(i), in vsc85xx_ts_disable_flows()
308 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP2_FLOW_ENA(i), in vsc85xx_ts_disable_flows()
310 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_ETH1_FLOW_ENA(i), in vsc85xx_ts_disable_flows()
312 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_ETH2_FLOW_ENA(i), in vsc85xx_ts_disable_flows()
314 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_MPLS_FLOW_CTRL(i), in vsc85xx_ts_disable_flows()
320 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_PTP_FLOW_ENA(i), 0); in vsc85xx_ts_disable_flows()
321 vsc85xx_ts_write_csr(phydev, blk, in vsc85xx_ts_disable_flows()
323 vsc85xx_ts_write_csr(phydev, blk, in vsc85xx_ts_disable_flows()
325 vsc85xx_ts_write_csr(phydev, blk, in vsc85xx_ts_disable_flows()
327 vsc85xx_ts_write_csr(phydev, blk, in vsc85xx_ts_disable_flows()
329 vsc85xx_ts_write_csr(phydev, blk, in vsc85xx_ts_disable_flows()
331 vsc85xx_ts_write_csr(phydev, blk, in vsc85xx_ts_disable_flows()
333 vsc85xx_ts_write_csr(phydev, blk, in vsc85xx_ts_disable_flows()
335 vsc85xx_ts_write_csr(phydev, blk, in vsc85xx_ts_disable_flows()
337 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_OAM_PTP_FLOW_ENA(i), in vsc85xx_ts_disable_flows()
344 static int vsc85xx_ts_eth_cmp1_sig(struct phy_device *phydev) in vsc85xx_ts_eth_cmp1_sig() argument
348 val = vsc85xx_ts_read_csr(phydev, EGRESS, MSCC_PHY_ANA_ETH1_NTX_PROT); in vsc85xx_ts_eth_cmp1_sig()
351 vsc85xx_ts_write_csr(phydev, EGRESS, MSCC_PHY_ANA_ETH1_NTX_PROT, val); in vsc85xx_ts_eth_cmp1_sig()
353 val = vsc85xx_ts_read_csr(phydev, EGRESS, MSCC_PHY_ANA_FSB_CFG); in vsc85xx_ts_eth_cmp1_sig()
356 vsc85xx_ts_write_csr(phydev, EGRESS, MSCC_PHY_ANA_FSB_CFG, val); in vsc85xx_ts_eth_cmp1_sig()
440 reg = vsc85xx_ts_read_csr(ptp->phydev, PROCESSOR, in vsc85xx_dequeue_skb()
450 reg = vsc85xx_ts_read_csr(ptp->phydev, PROCESSOR, in vsc85xx_dequeue_skb()
500 reg = vsc85xx_ts_read_csr(ptp->phydev, PROCESSOR, in vsc85xx_get_tx_ts()
505 static int vsc85xx_ptp_cmp_init(struct phy_device *phydev, enum ts_blk blk) in vsc85xx_ptp_cmp_init() argument
507 struct vsc8531_private *vsc8531 = phydev->priv; in vsc85xx_ptp_cmp_init()
508 bool base = phydev->mdio.addr == vsc8531->ts_base_addr; in vsc85xx_ptp_cmp_init()
517 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_PTP_FLOW_ENA(i), in vsc85xx_ptp_cmp_init()
521 val = vsc85xx_ts_read_csr(phydev, blk, in vsc85xx_ptp_cmp_init()
524 vsc85xx_ts_write_csr(phydev, blk, in vsc85xx_ptp_cmp_init()
527 vsc85xx_ts_write_csr(phydev, blk, in vsc85xx_ptp_cmp_init()
531 vsc85xx_ts_write_csr(phydev, blk, in vsc85xx_ptp_cmp_init()
539 static int vsc85xx_eth_cmp1_init(struct phy_device *phydev, enum ts_blk blk) in vsc85xx_eth_cmp1_init() argument
541 struct vsc8531_private *vsc8531 = phydev->priv; in vsc85xx_eth_cmp1_init()
542 bool base = phydev->mdio.addr == vsc8531->ts_base_addr; in vsc85xx_eth_cmp1_init()
545 vsc85xx_ts_write_csr(phydev, blk, MSCC_PHY_ANA_ETH1_NXT_PROT_TAG, 0); in vsc85xx_eth_cmp1_init()
546 vsc85xx_ts_write_csr(phydev, blk, MSCC_PHY_ANA_ETH1_NTX_PROT_VLAN_TPID, in vsc85xx_eth_cmp1_init()
549 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_ETH1_FLOW_ENA(0), in vsc85xx_eth_cmp1_init()
551 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_ETH1_FLOW_MATCH_MODE(0), in vsc85xx_eth_cmp1_init()
553 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_ETH1_FLOW_ADDR_MATCH1(0), 0); in vsc85xx_eth_cmp1_init()
554 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_ETH1_FLOW_ADDR_MATCH2(0), 0); in vsc85xx_eth_cmp1_init()
555 vsc85xx_ts_write_csr(phydev, blk, in vsc85xx_eth_cmp1_init()
557 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_ETH1_FLOW_VLAN_TAG1(0), 0); in vsc85xx_eth_cmp1_init()
558 vsc85xx_ts_write_csr(phydev, blk, in vsc85xx_eth_cmp1_init()
561 val = vsc85xx_ts_read_csr(phydev, blk, in vsc85xx_eth_cmp1_init()
565 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_ETH1_FLOW_MATCH_MODE(0), in vsc85xx_eth_cmp1_init()
571 static int vsc85xx_ip_cmp1_init(struct phy_device *phydev, enum ts_blk blk) in vsc85xx_ip_cmp1_init() argument
573 struct vsc8531_private *vsc8531 = phydev->priv; in vsc85xx_ip_cmp1_init()
574 bool base = phydev->mdio.addr == vsc8531->ts_base_addr; in vsc85xx_ip_cmp1_init()
577 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_MATCH2_UPPER, in vsc85xx_ip_cmp1_init()
580 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_MASK2_UPPER, in vsc85xx_ip_cmp1_init()
582 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_MATCH2_LOWER, in vsc85xx_ip_cmp1_init()
584 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_MASK2_LOWER, 0); in vsc85xx_ip_cmp1_init()
586 val = vsc85xx_ts_read_csr(phydev, blk, MSCC_ANA_IP1_FLOW_ENA(0)); in vsc85xx_ip_cmp1_init()
589 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_ENA(0), val); in vsc85xx_ip_cmp1_init()
592 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_MATCH_UPPER(0), 0); in vsc85xx_ip_cmp1_init()
593 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_MASK_UPPER(0), 0); in vsc85xx_ip_cmp1_init()
594 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_MATCH_UPPER_MID(0), in vsc85xx_ip_cmp1_init()
596 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_MASK_UPPER_MID(0), in vsc85xx_ip_cmp1_init()
598 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_MATCH_LOWER_MID(0), in vsc85xx_ip_cmp1_init()
600 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_MASK_LOWER_MID(0), in vsc85xx_ip_cmp1_init()
602 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_MATCH_LOWER(0), 0); in vsc85xx_ip_cmp1_init()
603 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_MASK_LOWER(0), 0); in vsc85xx_ip_cmp1_init()
605 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_PTP_IP_CHKSUM_SEL, 0); in vsc85xx_ip_cmp1_init()
613 struct phy_device *phydev = ptp->phydev; in vsc85xx_adjfine() local
614 struct vsc8531_private *priv = phydev->priv; in vsc85xx_adjfine()
631 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_AUTO_ADJ, in vsc85xx_adjfine()
635 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_CTRL); in vsc85xx_adjfine()
637 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_CTRL, val); in vsc85xx_adjfine()
647 struct phy_device *phydev = ptp->phydev; in __vsc85xx_gettime() local
649 (struct vsc85xx_shared_private *)phydev->shared->priv; in __vsc85xx_gettime()
650 struct vsc8531_private *priv = phydev->priv; in __vsc85xx_gettime()
653 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_CTRL); in __vsc85xx_gettime()
655 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_CTRL, val); in __vsc85xx_gettime()
663 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in __vsc85xx_gettime()
668 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in __vsc85xx_gettime()
672 ts->tv_nsec = vsc85xx_ts_read_csr(phydev, PROCESSOR, in __vsc85xx_gettime()
684 struct phy_device *phydev = ptp->phydev; in vsc85xx_gettime() local
685 struct vsc8531_private *priv = phydev->priv; in vsc85xx_gettime()
698 struct phy_device *phydev = ptp->phydev; in __vsc85xx_settime() local
700 (struct vsc85xx_shared_private *)phydev->shared->priv; in __vsc85xx_settime()
701 struct vsc8531_private *priv = phydev->priv; in __vsc85xx_settime()
704 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_LOAD_SEC_MSB, in __vsc85xx_settime()
706 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_LOAD_SEC_LSB, in __vsc85xx_settime()
708 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_LOAD_NS, in __vsc85xx_settime()
711 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_CTRL); in __vsc85xx_settime()
713 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_CTRL, val); in __vsc85xx_settime()
722 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_CTRL, val); in __vsc85xx_settime()
734 struct phy_device *phydev = ptp->phydev; in vsc85xx_settime() local
735 struct vsc8531_private *priv = phydev->priv; in vsc85xx_settime()
747 struct phy_device *phydev = ptp->phydev; in vsc85xx_adjtime() local
748 struct vsc8531_private *priv = phydev->priv; in vsc85xx_adjtime()
773 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_OFFSET, val); in vsc85xx_adjtime()
780 static int vsc85xx_eth1_next_comp(struct phy_device *phydev, enum ts_blk blk, in vsc85xx_eth1_next_comp() argument
785 val = vsc85xx_ts_read_csr(phydev, blk, MSCC_PHY_ANA_ETH1_NTX_PROT); in vsc85xx_eth1_next_comp()
788 vsc85xx_ts_write_csr(phydev, blk, MSCC_PHY_ANA_ETH1_NTX_PROT, val); in vsc85xx_eth1_next_comp()
792 vsc85xx_ts_write_csr(phydev, blk, in vsc85xx_eth1_next_comp()
798 static int vsc85xx_ip1_next_comp(struct phy_device *phydev, enum ts_blk blk, in vsc85xx_ip1_next_comp() argument
801 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_NXT_COMP, in vsc85xx_ip1_next_comp()
808 static int vsc85xx_ts_ptp_action_flow(struct phy_device *phydev, enum ts_blk blk, u8 flow, enum ptp… in vsc85xx_ts_ptp_action_flow() argument
814 vsc85xx_ts_write_csr(phydev, blk, in vsc85xx_ts_ptp_action_flow()
826 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_PTP_FLOW_PTP_ACTION(flow), in vsc85xx_ts_ptp_action_flow()
841 vsc85xx_ts_write_csr(phydev, blk, in vsc85xx_ts_ptp_action_flow()
847 static int vsc85xx_ptp_conf(struct phy_device *phydev, enum ts_blk blk, in vsc85xx_ptp_conf() argument
859 vsc85xx_ts_ptp_action_flow(phydev, blk, msgs[i], in vsc85xx_ptp_conf()
863 vsc85xx_ts_ptp_action_flow(phydev, blk, msgs[i], in vsc85xx_ptp_conf()
866 vsc85xx_ts_ptp_action_flow(phydev, blk, msgs[i], in vsc85xx_ptp_conf()
869 val = vsc85xx_ts_read_csr(phydev, blk, in vsc85xx_ptp_conf()
874 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_PTP_FLOW_ENA(i), in vsc85xx_ptp_conf()
881 static int vsc85xx_eth1_conf(struct phy_device *phydev, enum ts_blk blk, in vsc85xx_eth1_conf() argument
884 struct vsc8531_private *vsc8531 = phydev->priv; in vsc85xx_eth1_conf()
893 vsc85xx_ts_write_csr(phydev, blk, in vsc85xx_eth1_conf()
895 vsc85xx_ts_write_csr(phydev, blk, in vsc85xx_eth1_conf()
900 vsc85xx_ts_write_csr(phydev, blk, in vsc85xx_eth1_conf()
902 vsc85xx_ts_write_csr(phydev, blk, in vsc85xx_eth1_conf()
906 val = vsc85xx_ts_read_csr(phydev, blk, MSCC_ANA_ETH1_FLOW_ENA(0)); in vsc85xx_eth1_conf()
910 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_ETH1_FLOW_ENA(0), val); in vsc85xx_eth1_conf()
915 static int vsc85xx_ip1_conf(struct phy_device *phydev, enum ts_blk blk, in vsc85xx_ip1_conf() argument
920 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_IP1_MODE, in vsc85xx_ip1_conf()
928 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_IP_MATCH1, in vsc85xx_ip1_conf()
932 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_OFFSET2, in vsc85xx_ip1_conf()
935 val = vsc85xx_ts_read_csr(phydev, blk, in vsc85xx_ip1_conf()
947 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_UDP_CHKSUM, in vsc85xx_ip1_conf()
950 val = vsc85xx_ts_read_csr(phydev, blk, MSCC_ANA_IP1_FLOW_ENA(0)); in vsc85xx_ip1_conf()
955 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_ENA(0), val); in vsc85xx_ip1_conf()
960 static int vsc85xx_ts_engine_init(struct phy_device *phydev, bool one_step) in vsc85xx_ts_engine_init() argument
962 struct vsc8531_private *vsc8531 = phydev->priv; in vsc85xx_ts_engine_init()
963 bool ptp_l4, base = phydev->mdio.addr == vsc8531->ts_base_addr; in vsc85xx_ts_engine_init()
969 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in vsc85xx_ts_engine_init()
974 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_ANALYZER_MODE, in vsc85xx_ts_engine_init()
978 vsc85xx_eth1_next_comp(phydev, INGRESS, in vsc85xx_ts_engine_init()
980 vsc85xx_eth1_next_comp(phydev, EGRESS, in vsc85xx_ts_engine_init()
983 vsc85xx_eth1_next_comp(phydev, INGRESS, in vsc85xx_ts_engine_init()
986 vsc85xx_eth1_next_comp(phydev, EGRESS, in vsc85xx_ts_engine_init()
990 vsc85xx_ip1_next_comp(phydev, INGRESS, in vsc85xx_ts_engine_init()
992 vsc85xx_ip1_next_comp(phydev, EGRESS, in vsc85xx_ts_engine_init()
996 vsc85xx_eth1_conf(phydev, INGRESS, in vsc85xx_ts_engine_init()
998 vsc85xx_ip1_conf(phydev, INGRESS, in vsc85xx_ts_engine_init()
1000 vsc85xx_ptp_conf(phydev, INGRESS, one_step, in vsc85xx_ts_engine_init()
1003 vsc85xx_eth1_conf(phydev, EGRESS, in vsc85xx_ts_engine_init()
1005 vsc85xx_ip1_conf(phydev, EGRESS, in vsc85xx_ts_engine_init()
1007 vsc85xx_ptp_conf(phydev, EGRESS, one_step, in vsc85xx_ts_engine_init()
1018 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_ANALYZER_MODE, in vsc85xx_ts_engine_init()
1024 void vsc85xx_link_change_notify(struct phy_device *phydev) in vsc85xx_link_change_notify() argument
1026 struct vsc8531_private *priv = phydev->priv; in vsc85xx_link_change_notify()
1029 vsc85xx_ts_set_latencies(phydev); in vsc85xx_link_change_notify()
1033 static void vsc85xx_ts_reset_fifo(struct phy_device *phydev) in vsc85xx_ts_reset_fifo() argument
1037 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in vsc85xx_ts_reset_fifo()
1040 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_TS_FIFO_CTRL, in vsc85xx_ts_reset_fifo()
1044 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_TS_FIFO_CTRL, in vsc85xx_ts_reset_fifo()
1052 struct phy_device *phydev = vsc8531->ptp->phydev; in vsc85xx_hwtstamp() local
1098 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in vsc85xx_hwtstamp()
1101 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_INGR_PREDICTOR, in vsc85xx_hwtstamp()
1103 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in vsc85xx_hwtstamp()
1106 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_PREDICTOR, in vsc85xx_hwtstamp()
1110 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, MSCC_PHY_PTP_IFACE_CTRL); in vsc85xx_hwtstamp()
1116 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_IFACE_CTRL, val); in vsc85xx_hwtstamp()
1119 vsc85xx_ts_reset_fifo(phydev); in vsc85xx_hwtstamp()
1121 vsc85xx_ts_engine_init(phydev, one_step); in vsc85xx_hwtstamp()
1124 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in vsc85xx_hwtstamp()
1127 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_INGR_PREDICTOR, in vsc85xx_hwtstamp()
1129 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in vsc85xx_hwtstamp()
1132 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_PREDICTOR, in vsc85xx_hwtstamp()
1238 static struct vsc8531_private *vsc8584_base_priv(struct phy_device *phydev) in vsc8584_base_priv() argument
1240 struct vsc8531_private *vsc8531 = phydev->priv; in vsc8584_base_priv()
1242 if (vsc8531->ts_base_addr != phydev->mdio.addr) { in vsc8584_base_priv()
1245 dev = phydev->mdio.bus->mdio_map[vsc8531->ts_base_addr]; in vsc8584_base_priv()
1246 phydev = container_of(dev, struct phy_device, mdio); in vsc8584_base_priv()
1248 return phydev->priv; in vsc8584_base_priv()
1254 static bool vsc8584_is_1588_input_clk_configured(struct phy_device *phydev) in vsc8584_is_1588_input_clk_configured() argument
1256 struct vsc8531_private *vsc8531 = vsc8584_base_priv(phydev); in vsc8584_is_1588_input_clk_configured()
1261 static void vsc8584_set_input_clk_configured(struct phy_device *phydev) in vsc8584_set_input_clk_configured() argument
1263 struct vsc8531_private *vsc8531 = vsc8584_base_priv(phydev); in vsc8584_set_input_clk_configured()
1268 static int __vsc8584_init_ptp(struct phy_device *phydev) in __vsc8584_init_ptp() argument
1270 struct vsc8531_private *vsc8531 = phydev->priv; in __vsc8584_init_ptp()
1275 if (!vsc8584_is_1588_input_clk_configured(phydev)) { in __vsc8584_init_ptp()
1276 phy_lock_mdio_bus(phydev); in __vsc8584_init_ptp()
1281 phy_ts_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in __vsc8584_init_ptp()
1283 phy_ts_base_write(phydev, 29, 0x7ae0); in __vsc8584_init_ptp()
1284 phy_ts_base_write(phydev, 30, 0xb71c); in __vsc8584_init_ptp()
1285 phy_ts_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in __vsc8584_init_ptp()
1288 phy_unlock_mdio_bus(phydev); in __vsc8584_init_ptp()
1290 vsc8584_set_input_clk_configured(phydev); in __vsc8584_init_ptp()
1294 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in __vsc8584_init_ptp()
1297 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_INGR_PREDICTOR, in __vsc8584_init_ptp()
1299 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in __vsc8584_init_ptp()
1302 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_PREDICTOR, in __vsc8584_init_ptp()
1306 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_CTRL); in __vsc8584_init_ptp()
1309 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_CTRL, val); in __vsc8584_init_ptp()
1311 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_SEQUENCE); in __vsc8584_init_ptp()
1314 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_SEQUENCE, val); in __vsc8584_init_ptp()
1316 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_SEQ); in __vsc8584_init_ptp()
1321 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_SEQ, val); in __vsc8584_init_ptp()
1323 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_1PPS_WIDTH_ADJ, in __vsc8584_init_ptp()
1326 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_INGR_DELAY_FIFO, in __vsc8584_init_ptp()
1331 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_DELAY_FIFO, in __vsc8584_init_ptp()
1337 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in __vsc8584_init_ptp()
1347 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_ACCUR_CFG_STATUS, in __vsc8584_init_ptp()
1350 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in __vsc8584_init_ptp()
1353 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_ACCUR_CFG_STATUS, in __vsc8584_init_ptp()
1356 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in __vsc8584_init_ptp()
1364 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_ACCUR_CFG_STATUS, in __vsc8584_init_ptp()
1367 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in __vsc8584_init_ptp()
1370 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_ACCUR_CFG_STATUS, in __vsc8584_init_ptp()
1373 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in __vsc8584_init_ptp()
1376 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_ACCUR_CFG_STATUS, in __vsc8584_init_ptp()
1380 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in __vsc8584_init_ptp()
1383 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_TSTAMP_FIFO_SI, in __vsc8584_init_ptp()
1386 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in __vsc8584_init_ptp()
1389 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_INGR_REWRITER_CTRL, in __vsc8584_init_ptp()
1391 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in __vsc8584_init_ptp()
1394 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_REWRITER_CTRL, in __vsc8584_init_ptp()
1398 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in __vsc8584_init_ptp()
1401 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_INGR_REWRITER_CTRL, in __vsc8584_init_ptp()
1403 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in __vsc8584_init_ptp()
1407 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_REWRITER_CTRL, in __vsc8584_init_ptp()
1413 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in __vsc8584_init_ptp()
1416 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_INGR_TSP_CTRL, in __vsc8584_init_ptp()
1419 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_TSP_CTRL); in __vsc8584_init_ptp()
1421 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_TSP_CTRL, val); in __vsc8584_init_ptp()
1423 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in __vsc8584_init_ptp()
1426 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_SERIAL_TOD_IFACE, in __vsc8584_init_ptp()
1429 vsc85xx_ts_fsb_init(phydev); in __vsc8584_init_ptp()
1432 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in __vsc8584_init_ptp()
1437 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_TS_FIFO_CTRL, in __vsc8584_init_ptp()
1440 vsc85xx_ts_reset_fifo(phydev); in __vsc8584_init_ptp()
1445 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_IFACE_CTRL, val); in __vsc8584_init_ptp()
1447 vsc85xx_ts_set_latencies(phydev); in __vsc8584_init_ptp()
1449 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, MSCC_PHY_PTP_VERSION_CODE); in __vsc8584_init_ptp()
1451 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, MSCC_PHY_PTP_IFACE_CTRL); in __vsc8584_init_ptp()
1453 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_IFACE_CTRL, val); in __vsc8584_init_ptp()
1455 vsc85xx_ts_disable_flows(phydev, EGRESS); in __vsc8584_init_ptp()
1456 vsc85xx_ts_disable_flows(phydev, INGRESS); in __vsc8584_init_ptp()
1458 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in __vsc8584_init_ptp()
1470 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_ANALYZER_MODE, in __vsc8584_init_ptp()
1478 vsc85xx_eth_cmp1_init(phydev, INGRESS); in __vsc8584_init_ptp()
1479 vsc85xx_ip_cmp1_init(phydev, INGRESS); in __vsc8584_init_ptp()
1480 vsc85xx_ptp_cmp_init(phydev, INGRESS); in __vsc8584_init_ptp()
1481 vsc85xx_eth_cmp1_init(phydev, EGRESS); in __vsc8584_init_ptp()
1482 vsc85xx_ip_cmp1_init(phydev, EGRESS); in __vsc8584_init_ptp()
1483 vsc85xx_ptp_cmp_init(phydev, EGRESS); in __vsc8584_init_ptp()
1485 vsc85xx_ts_eth_cmp1_sig(phydev); in __vsc8584_init_ptp()
1491 phydev->mii_ts = &vsc8531->mii_ts; in __vsc8584_init_ptp()
1496 &phydev->mdio.dev); in __vsc8584_init_ptp()
1500 void vsc8584_config_ts_intr(struct phy_device *phydev) in vsc8584_config_ts_intr() argument
1502 struct vsc8531_private *priv = phydev->priv; in vsc8584_config_ts_intr()
1505 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_1588_VSC85XX_INT_MASK, in vsc8584_config_ts_intr()
1510 int vsc8584_ptp_init(struct phy_device *phydev) in vsc8584_ptp_init() argument
1512 switch (phydev->phy_id & phydev->drv->phy_id_mask) { in vsc8584_ptp_init()
1518 return __vsc8584_init_ptp(phydev); in vsc8584_ptp_init()
1524 irqreturn_t vsc8584_handle_ts_interrupt(struct phy_device *phydev) in vsc8584_handle_ts_interrupt() argument
1526 struct vsc8531_private *priv = phydev->priv; in vsc8584_handle_ts_interrupt()
1530 rc = vsc85xx_ts_read_csr(phydev, PROCESSOR, in vsc8584_handle_ts_interrupt()
1533 vsc85xx_ts_write_csr(phydev, PROCESSOR, in vsc8584_handle_ts_interrupt()
1545 vsc85xx_ts_reset_fifo(phydev); in vsc8584_handle_ts_interrupt()
1552 int vsc8584_ptp_probe(struct phy_device *phydev) in vsc8584_ptp_probe() argument
1554 struct vsc8531_private *vsc8531 = phydev->priv; in vsc8584_ptp_probe()
1556 vsc8531->ptp = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531->ptp), in vsc8584_ptp_probe()
1569 vsc8531->load_save = devm_gpiod_get_optional(&phydev->mdio.dev, "load-save", in vsc8584_ptp_probe()
1573 phydev_err(phydev, "Can't get load-save GPIO (%ld)\n", in vsc8584_ptp_probe()
1578 vsc8531->ptp->phydev = phydev; in vsc8584_ptp_probe()
1583 int vsc8584_ptp_probe_once(struct phy_device *phydev) in vsc8584_ptp_probe_once() argument
1586 (struct vsc85xx_shared_private *)phydev->shared->priv; in vsc8584_ptp_probe_once()