Lines Matching refs:phy_write_mmd
223 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, VEND1_LTC_LOAD_CTRL, in _nxp_c45_ptp_gettimex64()
255 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, VEND1_LTC_WR_NSEC_0, in _nxp_c45_ptp_settime64()
257 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, VEND1_LTC_WR_NSEC_1, in _nxp_c45_ptp_settime64()
259 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, VEND1_LTC_WR_SEC_0, in _nxp_c45_ptp_settime64()
261 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, VEND1_LTC_WR_SEC_1, in _nxp_c45_ptp_settime64()
263 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, VEND1_LTC_LOAD_CTRL, in _nxp_c45_ptp_settime64()
294 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, VEND1_RATE_ADJ_SUBNS_0, in nxp_c45_ptp_adjfine()
301 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, VEND1_RATE_ADJ_SUBNS_1, in nxp_c45_ptp_adjfine()
349 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, VEND1_EGR_RING_CTRL, in nxp_c45_get_hwtxts()
543 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_EVENT_MSG_FILT, in nxp_c45_hwtstamp()
549 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_EVENT_MSG_FILT, in nxp_c45_hwtstamp()
650 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_DEVICE_CONTROL, in nxp_c45_config_enable()
655 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_PORT_CONTROL, in nxp_c45_config_enable()
657 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_PHY_CONTROL, in nxp_c45_config_enable()
659 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_PORT_INFRA_CONTROL, in nxp_c45_config_enable()
690 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_PHY_IRQ_ACK, in nxp_c45_handle_interrupt()
715 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_DEVICE_CONTROL, in nxp_c45_soft_reset()
728 return phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_CABLE_TEST, in nxp_c45_cable_test_start()
776 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, PMAPMD_B100T1_PMAPMD_CTL, in nxp_c45_setup_master_slave()
781 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, PMAPMD_B100T1_PMAPMD_CTL, in nxp_c45_setup_master_slave()
897 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_TXID, in nxp_c45_set_delays()
907 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_RXID, in nxp_c45_set_delays()
968 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG, in nxp_c45_set_phy_mode()
979 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG, in nxp_c45_set_phy_mode()
992 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG, in nxp_c45_set_phy_mode()
1000 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG, in nxp_c45_set_phy_mode()
1008 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG, in nxp_c45_set_phy_mode()
1016 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG, in nxp_c45_set_phy_mode()
1041 phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F8, 1); in nxp_c45_config_init()
1042 phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F9, 2); in nxp_c45_config_init()
1064 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_PTP_CLK_PERIOD, in nxp_c45_config_init()
1068 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_RX_TS_INSRT_CTRL, in nxp_c45_config_init()