Lines Matching refs:ah
96 static int ath5k_reset(struct ath5k_hw *ah, struct ieee80211_channel *chan,
200 static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp) in ath5k_extend_tsf() argument
202 u64 tsf = ath5k_hw_get_tsf64(ah); in ath5k_extend_tsf()
233 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv; in ath5k_ioread32() local
234 return ath5k_hw_reg_read(ah, reg_offset); in ath5k_ioread32()
239 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv; in ath5k_iowrite32() local
240 ath5k_hw_reg_write(ah, val, reg_offset); in ath5k_iowrite32()
256 struct ath5k_hw *ah = hw->priv; in ath5k_reg_notifier() local
257 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah); in ath5k_reg_notifier()
295 ath5k_setup_channels(struct ath5k_hw *ah, struct ieee80211_channel *channels, in ath5k_setup_channels() argument
313 ATH5K_WARN(ah, "bad mode, not copying channels\n"); in ath5k_setup_channels()
330 if (!ath5k_channel_ok(ah, &channels[count])) in ath5k_setup_channels()
343 ath5k_setup_rate_idx(struct ath5k_hw *ah, struct ieee80211_supported_band *b) in ath5k_setup_rate_idx() argument
348 ah->rate_idx[b->band][i] = -1; in ath5k_setup_rate_idx()
351 ah->rate_idx[b->band][b->bitrates[i].hw_value] = i; in ath5k_setup_rate_idx()
353 ah->rate_idx[b->band][b->bitrates[i].hw_value_short] = i; in ath5k_setup_rate_idx()
360 struct ath5k_hw *ah = hw->priv; in ath5k_setup_bands() local
365 BUILD_BUG_ON(ARRAY_SIZE(ah->sbands) < NUM_NL80211_BANDS); in ath5k_setup_bands()
366 max_c = ARRAY_SIZE(ah->channels); in ath5k_setup_bands()
369 sband = &ah->sbands[NL80211_BAND_2GHZ]; in ath5k_setup_bands()
371 sband->bitrates = &ah->rates[NL80211_BAND_2GHZ][0]; in ath5k_setup_bands()
373 if (test_bit(AR5K_MODE_11G, ah->ah_capabilities.cap_mode)) { in ath5k_setup_bands()
379 sband->channels = ah->channels; in ath5k_setup_bands()
380 sband->n_channels = ath5k_setup_channels(ah, sband->channels, in ath5k_setup_bands()
386 } else if (test_bit(AR5K_MODE_11B, ah->ah_capabilities.cap_mode)) { in ath5k_setup_bands()
396 if (ah->ah_version == AR5K_AR5211) { in ath5k_setup_bands()
405 sband->channels = ah->channels; in ath5k_setup_bands()
406 sband->n_channels = ath5k_setup_channels(ah, sband->channels, in ath5k_setup_bands()
413 ath5k_setup_rate_idx(ah, sband); in ath5k_setup_bands()
416 if (test_bit(AR5K_MODE_11A, ah->ah_capabilities.cap_mode)) { in ath5k_setup_bands()
417 sband = &ah->sbands[NL80211_BAND_5GHZ]; in ath5k_setup_bands()
419 sband->bitrates = &ah->rates[NL80211_BAND_5GHZ][0]; in ath5k_setup_bands()
425 sband->channels = &ah->channels[count_c]; in ath5k_setup_bands()
426 sband->n_channels = ath5k_setup_channels(ah, sband->channels, in ath5k_setup_bands()
431 ath5k_setup_rate_idx(ah, sband); in ath5k_setup_bands()
433 ath5k_debug_dump_bands(ah); in ath5k_setup_bands()
446 ath5k_chan_set(struct ath5k_hw *ah, struct cfg80211_chan_def *chandef) in ath5k_chan_set() argument
448 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, in ath5k_chan_set()
450 ah->curchan->center_freq, chandef->chan->center_freq); in ath5k_chan_set()
455 ah->ah_bwmode = AR5K_BWMODE_DEFAULT; in ath5k_chan_set()
458 ah->ah_bwmode = AR5K_BWMODE_5MHZ; in ath5k_chan_set()
461 ah->ah_bwmode = AR5K_BWMODE_10MHZ; in ath5k_chan_set()
474 return ath5k_reset(ah, chandef->chan, true); in ath5k_chan_set()
518 ath5k_update_bssid_mask_and_opmode(struct ath5k_hw *ah, in ath5k_update_bssid_mask_and_opmode() argument
521 struct ath_common *common = ath5k_hw_common(ah); in ath5k_update_bssid_mask_and_opmode()
541 ah->hw, IEEE80211_IFACE_ITER_RESUME_ALL, in ath5k_update_bssid_mask_and_opmode()
543 memcpy(ah->bssidmask, iter_data.mask, ETH_ALEN); in ath5k_update_bssid_mask_and_opmode()
545 ah->opmode = iter_data.opmode; in ath5k_update_bssid_mask_and_opmode()
546 if (ah->opmode == NL80211_IFTYPE_UNSPECIFIED) in ath5k_update_bssid_mask_and_opmode()
548 ah->opmode = NL80211_IFTYPE_STATION; in ath5k_update_bssid_mask_and_opmode()
550 ath5k_hw_set_opmode(ah, ah->opmode); in ath5k_update_bssid_mask_and_opmode()
551 ATH5K_DBG(ah, ATH5K_DEBUG_MODE, "mode setup opmode %d (%s)\n", in ath5k_update_bssid_mask_and_opmode()
552 ah->opmode, ath_opmode_to_string(ah->opmode)); in ath5k_update_bssid_mask_and_opmode()
555 ath5k_hw_set_lladdr(ah, iter_data.active_mac); in ath5k_update_bssid_mask_and_opmode()
557 if (ath5k_hw_hasbssidmask(ah)) in ath5k_update_bssid_mask_and_opmode()
558 ath5k_hw_set_bssid_mask(ah, ah->bssidmask); in ath5k_update_bssid_mask_and_opmode()
566 ah->filter_flags |= AR5K_RX_FILTER_PROM; in ath5k_update_bssid_mask_and_opmode()
569 rfilt = ah->filter_flags; in ath5k_update_bssid_mask_and_opmode()
570 ath5k_hw_set_rx_filter(ah, rfilt); in ath5k_update_bssid_mask_and_opmode()
571 ATH5K_DBG(ah, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt); in ath5k_update_bssid_mask_and_opmode()
575 ath5k_hw_to_driver_rix(struct ath5k_hw *ah, int hw_rix) in ath5k_hw_to_driver_rix() argument
584 rix = ah->rate_idx[ah->curchan->band][hw_rix]; in ath5k_hw_to_driver_rix()
596 struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_hw *ah, dma_addr_t *skb_addr) in ath5k_rx_skb_alloc() argument
598 struct ath_common *common = ath5k_hw_common(ah); in ath5k_rx_skb_alloc()
610 ATH5K_ERR(ah, "can't alloc skbuff of size %u\n", in ath5k_rx_skb_alloc()
615 *skb_addr = dma_map_single(ah->dev, in ath5k_rx_skb_alloc()
619 if (unlikely(dma_mapping_error(ah->dev, *skb_addr))) { in ath5k_rx_skb_alloc()
620 ATH5K_ERR(ah, "%s: DMA mapping failed\n", __func__); in ath5k_rx_skb_alloc()
628 ath5k_rxbuf_setup(struct ath5k_hw *ah, struct ath5k_buf *bf) in ath5k_rxbuf_setup() argument
635 skb = ath5k_rx_skb_alloc(ah, &bf->skbaddr); in ath5k_rxbuf_setup()
659 ret = ath5k_hw_setup_rx_desc(ah, ds, ah->common.rx_bufsize, 0); in ath5k_rxbuf_setup()
661 ATH5K_ERR(ah, "%s: could not setup RX desc\n", __func__); in ath5k_rxbuf_setup()
665 if (ah->rxlink != NULL) in ath5k_rxbuf_setup()
666 *ah->rxlink = bf->daddr; in ath5k_rxbuf_setup()
667 ah->rxlink = &ds->ds_link; in ath5k_rxbuf_setup()
731 ath5k_txbuf_setup(struct ath5k_hw *ah, struct ath5k_buf *bf, in ath5k_txbuf_setup() argument
750 bf->skbaddr = dma_map_single(ah->dev, skb->data, skb->len, in ath5k_txbuf_setup()
753 if (dma_mapping_error(ah->dev, bf->skbaddr)) in ath5k_txbuf_setup()
759 rate = ath5k_get_rate(ah->hw, info, bf, 0); in ath5k_txbuf_setup()
771 hw_rate = ath5k_get_rate_hw_value(ah->hw, info, bf, 0); in ath5k_txbuf_setup()
784 cts_rate = ieee80211_get_rts_cts_rate(ah->hw, info)->hw_value; in ath5k_txbuf_setup()
785 duration = le16_to_cpu(ieee80211_rts_duration(ah->hw, in ath5k_txbuf_setup()
790 cts_rate = ieee80211_get_rts_cts_rate(ah->hw, info)->hw_value; in ath5k_txbuf_setup()
791 duration = le16_to_cpu(ieee80211_ctstoself_duration(ah->hw, in ath5k_txbuf_setup()
795 ret = ah->ah_setup_tx_desc(ah, ds, pktlen, in ath5k_txbuf_setup()
798 (ah->ah_txpower.txp_requested * 2), in ath5k_txbuf_setup()
800 bf->rates[0].count, keyidx, ah->ah_tx_ant, flags, in ath5k_txbuf_setup()
806 if (ah->ah_capabilities.cap_has_mrr_support) { in ath5k_txbuf_setup()
812 rate = ath5k_get_rate(ah->hw, info, bf, i); in ath5k_txbuf_setup()
816 mrr_rate[i] = ath5k_get_rate_hw_value(ah->hw, info, bf, i); in ath5k_txbuf_setup()
820 ath5k_hw_setup_mrr_tx_desc(ah, ds, in ath5k_txbuf_setup()
833 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr); in ath5k_txbuf_setup()
838 ath5k_hw_start_tx_dma(ah, txq->qnum); in ath5k_txbuf_setup()
843 dma_unmap_single(ah->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE); in ath5k_txbuf_setup()
852 ath5k_desc_alloc(struct ath5k_hw *ah) in ath5k_desc_alloc() argument
861 ah->desc_len = sizeof(struct ath5k_desc) * in ath5k_desc_alloc()
864 ah->desc = dma_alloc_coherent(ah->dev, ah->desc_len, in ath5k_desc_alloc()
865 &ah->desc_daddr, GFP_KERNEL); in ath5k_desc_alloc()
866 if (ah->desc == NULL) { in ath5k_desc_alloc()
867 ATH5K_ERR(ah, "can't allocate descriptors\n"); in ath5k_desc_alloc()
871 ds = ah->desc; in ath5k_desc_alloc()
872 da = ah->desc_daddr; in ath5k_desc_alloc()
873 ATH5K_DBG(ah, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n", in ath5k_desc_alloc()
874 ds, ah->desc_len, (unsigned long long)ah->desc_daddr); in ath5k_desc_alloc()
879 ATH5K_ERR(ah, "can't allocate bufptr\n"); in ath5k_desc_alloc()
883 ah->bufptr = bf; in ath5k_desc_alloc()
885 INIT_LIST_HEAD(&ah->rxbuf); in ath5k_desc_alloc()
889 list_add_tail(&bf->list, &ah->rxbuf); in ath5k_desc_alloc()
892 INIT_LIST_HEAD(&ah->txbuf); in ath5k_desc_alloc()
893 ah->txbuf_len = ATH_TXBUF; in ath5k_desc_alloc()
897 list_add_tail(&bf->list, &ah->txbuf); in ath5k_desc_alloc()
901 INIT_LIST_HEAD(&ah->bcbuf); in ath5k_desc_alloc()
905 list_add_tail(&bf->list, &ah->bcbuf); in ath5k_desc_alloc()
910 dma_free_coherent(ah->dev, ah->desc_len, ah->desc, ah->desc_daddr); in ath5k_desc_alloc()
912 ah->desc = NULL; in ath5k_desc_alloc()
917 ath5k_txbuf_free_skb(struct ath5k_hw *ah, struct ath5k_buf *bf) in ath5k_txbuf_free_skb() argument
922 dma_unmap_single(ah->dev, bf->skbaddr, bf->skb->len, in ath5k_txbuf_free_skb()
924 ieee80211_free_txskb(ah->hw, bf->skb); in ath5k_txbuf_free_skb()
931 ath5k_rxbuf_free_skb(struct ath5k_hw *ah, struct ath5k_buf *bf) in ath5k_rxbuf_free_skb() argument
933 struct ath_common *common = ath5k_hw_common(ah); in ath5k_rxbuf_free_skb()
938 dma_unmap_single(ah->dev, bf->skbaddr, common->rx_bufsize, in ath5k_rxbuf_free_skb()
947 ath5k_desc_free(struct ath5k_hw *ah) in ath5k_desc_free() argument
951 list_for_each_entry(bf, &ah->txbuf, list) in ath5k_desc_free()
952 ath5k_txbuf_free_skb(ah, bf); in ath5k_desc_free()
953 list_for_each_entry(bf, &ah->rxbuf, list) in ath5k_desc_free()
954 ath5k_rxbuf_free_skb(ah, bf); in ath5k_desc_free()
955 list_for_each_entry(bf, &ah->bcbuf, list) in ath5k_desc_free()
956 ath5k_txbuf_free_skb(ah, bf); in ath5k_desc_free()
959 dma_free_coherent(ah->dev, ah->desc_len, ah->desc, ah->desc_daddr); in ath5k_desc_free()
960 ah->desc = NULL; in ath5k_desc_free()
961 ah->desc_daddr = 0; in ath5k_desc_free()
963 kfree(ah->bufptr); in ath5k_desc_free()
964 ah->bufptr = NULL; in ath5k_desc_free()
973 ath5k_txq_setup(struct ath5k_hw *ah, in ath5k_txq_setup() argument
1001 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi); in ath5k_txq_setup()
1009 txq = &ah->txqs[qnum]; in ath5k_txq_setup()
1021 return &ah->txqs[qnum]; in ath5k_txq_setup()
1025 ath5k_beaconq_setup(struct ath5k_hw *ah) in ath5k_beaconq_setup() argument
1037 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi); in ath5k_beaconq_setup()
1041 ath5k_beaconq_config(struct ath5k_hw *ah) in ath5k_beaconq_config() argument
1046 ret = ath5k_hw_get_tx_queueprops(ah, ah->bhalq, &qi); in ath5k_beaconq_config()
1050 if (ah->opmode == NL80211_IFTYPE_AP || in ath5k_beaconq_config()
1051 ah->opmode == NL80211_IFTYPE_MESH_POINT) { in ath5k_beaconq_config()
1059 } else if (ah->opmode == NL80211_IFTYPE_ADHOC) { in ath5k_beaconq_config()
1068 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, in ath5k_beaconq_config()
1072 ret = ath5k_hw_set_tx_queueprops(ah, ah->bhalq, &qi); in ath5k_beaconq_config()
1074 ATH5K_ERR(ah, "%s: unable to update parameters for beacon " in ath5k_beaconq_config()
1078 ret = ath5k_hw_reset_tx_queue(ah, ah->bhalq); /* push to h/w */ in ath5k_beaconq_config()
1083 ret = ath5k_hw_get_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi); in ath5k_beaconq_config()
1087 qi.tqi_ready_time = (ah->bintval * 80) / 100; in ath5k_beaconq_config()
1088 ret = ath5k_hw_set_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi); in ath5k_beaconq_config()
1092 ret = ath5k_hw_reset_tx_queue(ah, AR5K_TX_QUEUE_ID_CAB); in ath5k_beaconq_config()
1109 ath5k_drain_tx_buffs(struct ath5k_hw *ah) in ath5k_drain_tx_buffs() argument
1115 for (i = 0; i < ARRAY_SIZE(ah->txqs); i++) { in ath5k_drain_tx_buffs()
1116 if (ah->txqs[i].setup) { in ath5k_drain_tx_buffs()
1117 txq = &ah->txqs[i]; in ath5k_drain_tx_buffs()
1120 ath5k_debug_printtxbuf(ah, bf); in ath5k_drain_tx_buffs()
1122 ath5k_txbuf_free_skb(ah, bf); in ath5k_drain_tx_buffs()
1124 spin_lock(&ah->txbuflock); in ath5k_drain_tx_buffs()
1125 list_move_tail(&bf->list, &ah->txbuf); in ath5k_drain_tx_buffs()
1126 ah->txbuf_len++; in ath5k_drain_tx_buffs()
1128 spin_unlock(&ah->txbuflock); in ath5k_drain_tx_buffs()
1138 ath5k_txq_release(struct ath5k_hw *ah) in ath5k_txq_release() argument
1140 struct ath5k_txq *txq = ah->txqs; in ath5k_txq_release()
1143 for (i = 0; i < ARRAY_SIZE(ah->txqs); i++, txq++) in ath5k_txq_release()
1145 ath5k_hw_release_tx_queue(ah, txq->qnum); in ath5k_txq_release()
1159 ath5k_rx_start(struct ath5k_hw *ah) in ath5k_rx_start() argument
1161 struct ath_common *common = ath5k_hw_common(ah); in ath5k_rx_start()
1167 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n", in ath5k_rx_start()
1170 spin_lock_bh(&ah->rxbuflock); in ath5k_rx_start()
1171 ah->rxlink = NULL; in ath5k_rx_start()
1172 list_for_each_entry(bf, &ah->rxbuf, list) { in ath5k_rx_start()
1173 ret = ath5k_rxbuf_setup(ah, bf); in ath5k_rx_start()
1175 spin_unlock_bh(&ah->rxbuflock); in ath5k_rx_start()
1179 bf = list_first_entry(&ah->rxbuf, struct ath5k_buf, list); in ath5k_rx_start()
1180 ath5k_hw_set_rxdp(ah, bf->daddr); in ath5k_rx_start()
1181 spin_unlock_bh(&ah->rxbuflock); in ath5k_rx_start()
1183 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */ in ath5k_rx_start()
1184 ath5k_update_bssid_mask_and_opmode(ah, NULL); /* set filters, etc. */ in ath5k_rx_start()
1185 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */ in ath5k_rx_start()
1200 ath5k_rx_stop(struct ath5k_hw *ah) in ath5k_rx_stop() argument
1203 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */ in ath5k_rx_stop()
1204 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */ in ath5k_rx_stop()
1206 ath5k_debug_printrxbuffs(ah); in ath5k_rx_stop()
1210 ath5k_rx_decrypted(struct ath5k_hw *ah, struct sk_buff *skb, in ath5k_rx_decrypted() argument
1213 struct ath_common *common = ath5k_hw_common(ah); in ath5k_rx_decrypted()
1239 ath5k_check_ibss_tsf(struct ath5k_hw *ah, struct sk_buff *skb, in ath5k_check_ibss_tsf() argument
1252 tsf = ath5k_hw_get_tsf64(ah); in ath5k_check_ibss_tsf()
1256 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, in ath5k_check_ibss_tsf()
1275 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, in ath5k_check_ibss_tsf()
1288 if (hw_tu >= ah->nexttbtt) in ath5k_check_ibss_tsf()
1289 ath5k_beacon_update_timers(ah, bc_tstamp); in ath5k_check_ibss_tsf()
1294 if (!ath5k_hw_check_beacon_timers(ah, ah->bintval)) { in ath5k_check_ibss_tsf()
1295 ath5k_beacon_update_timers(ah, bc_tstamp); in ath5k_check_ibss_tsf()
1296 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, in ath5k_check_ibss_tsf()
1370 ath5k_receive_frame(struct ath5k_hw *ah, struct sk_buff *skb, in ath5k_receive_frame() argument
1374 struct ath_common *common = ath5k_hw_common(ah); in ath5k_receive_frame()
1396 rxs->mactime = ath5k_extend_tsf(ah, rs->rs_tstamp); in ath5k_receive_frame()
1399 rxs->freq = ah->curchan->center_freq; in ath5k_receive_frame()
1400 rxs->band = ah->curchan->band; in ath5k_receive_frame()
1402 rxs->signal = ah->ah_noise_floor + rs->rs_rssi; in ath5k_receive_frame()
1407 ah->stats.antenna_rx[rs->rs_antenna]++; in ath5k_receive_frame()
1409 ah->stats.antenna_rx[0]++; /* invalid */ in ath5k_receive_frame()
1411 rxs->rate_idx = ath5k_hw_to_driver_rix(ah, rs->rs_rate); in ath5k_receive_frame()
1412 rxs->flag |= ath5k_rx_decrypted(ah, skb, rs); in ath5k_receive_frame()
1413 switch (ah->ah_bwmode) { in ath5k_receive_frame()
1425 ah->sbands[ah->curchan->band].bitrates[rxs->rate_idx].hw_value_short) in ath5k_receive_frame()
1428 trace_ath5k_rx(ah, skb); in ath5k_receive_frame()
1431 ewma_beacon_rssi_add(&ah->ah_beacon_rssi_avg, rs->rs_rssi); in ath5k_receive_frame()
1434 if (ah->opmode == NL80211_IFTYPE_ADHOC) in ath5k_receive_frame()
1435 ath5k_check_ibss_tsf(ah, skb, rxs); in ath5k_receive_frame()
1438 ieee80211_rx(ah->hw, skb); in ath5k_receive_frame()
1447 ath5k_receive_frame_ok(struct ath5k_hw *ah, struct ath5k_rx_status *rs) in ath5k_receive_frame_ok() argument
1449 ah->stats.rx_all_count++; in ath5k_receive_frame_ok()
1450 ah->stats.rx_bytes_count += rs->rs_datalen; in ath5k_receive_frame_ok()
1456 ah->stats.rxerr_crc++; in ath5k_receive_frame_ok()
1458 ah->stats.rxerr_fifo++; in ath5k_receive_frame_ok()
1460 ah->stats.rxerr_phy++; in ath5k_receive_frame_ok()
1462 ah->stats.rxerr_phy_code[rs->rs_phyerr]++; in ath5k_receive_frame_ok()
1489 ah->stats.rxerr_decrypt++; in ath5k_receive_frame_ok()
1495 ah->stats.rxerr_mic++; in ath5k_receive_frame_ok()
1504 if (ah->fif_filter_flags & FIF_FCSFAIL) in ath5k_receive_frame_ok()
1512 ah->stats.rxerr_jumbo++; in ath5k_receive_frame_ok()
1519 ath5k_set_current_imask(struct ath5k_hw *ah) in ath5k_set_current_imask() argument
1524 if (test_bit(ATH_STAT_RESET, ah->status)) in ath5k_set_current_imask()
1527 spin_lock_irqsave(&ah->irqlock, flags); in ath5k_set_current_imask()
1528 imask = ah->imask; in ath5k_set_current_imask()
1529 if (ah->rx_pending) in ath5k_set_current_imask()
1531 if (ah->tx_pending) in ath5k_set_current_imask()
1533 ath5k_hw_set_imr(ah, imask); in ath5k_set_current_imask()
1534 spin_unlock_irqrestore(&ah->irqlock, flags); in ath5k_set_current_imask()
1543 struct ath5k_hw *ah = from_tasklet(ah, t, rxtq); in ath5k_tasklet_rx() local
1544 struct ath_common *common = ath5k_hw_common(ah); in ath5k_tasklet_rx()
1549 spin_lock(&ah->rxbuflock); in ath5k_tasklet_rx()
1550 if (list_empty(&ah->rxbuf)) { in ath5k_tasklet_rx()
1551 ATH5K_WARN(ah, "empty rx buf pool\n"); in ath5k_tasklet_rx()
1555 bf = list_first_entry(&ah->rxbuf, struct ath5k_buf, list); in ath5k_tasklet_rx()
1561 if (ath5k_hw_get_rxdp(ah) == bf->daddr) in ath5k_tasklet_rx()
1564 ret = ah->ah_proc_rx_desc(ah, ds, &rs); in ath5k_tasklet_rx()
1568 ATH5K_ERR(ah, "error in processing rx descriptor\n"); in ath5k_tasklet_rx()
1569 ah->stats.rxerr_proc++; in ath5k_tasklet_rx()
1573 if (ath5k_receive_frame_ok(ah, &rs)) { in ath5k_tasklet_rx()
1574 next_skb = ath5k_rx_skb_alloc(ah, &next_skb_addr); in ath5k_tasklet_rx()
1583 dma_unmap_single(ah->dev, bf->skbaddr, in ath5k_tasklet_rx()
1589 ath5k_receive_frame(ah, skb, &rs); in ath5k_tasklet_rx()
1595 list_move_tail(&bf->list, &ah->rxbuf); in ath5k_tasklet_rx()
1596 } while (ath5k_rxbuf_setup(ah, bf) == 0); in ath5k_tasklet_rx()
1598 spin_unlock(&ah->rxbuflock); in ath5k_tasklet_rx()
1599 ah->rx_pending = false; in ath5k_tasklet_rx()
1600 ath5k_set_current_imask(ah); in ath5k_tasklet_rx()
1612 struct ath5k_hw *ah = hw->priv; in ath5k_tx_queue() local
1617 trace_ath5k_tx(ah, skb, txq); in ath5k_tx_queue()
1625 ATH5K_ERR(ah, "tx hdrlen not %%4: not enough" in ath5k_tx_queue()
1634 spin_lock_irqsave(&ah->txbuflock, flags); in ath5k_tx_queue()
1635 if (list_empty(&ah->txbuf)) { in ath5k_tx_queue()
1636 ATH5K_ERR(ah, "no further txbuf available, dropping packet\n"); in ath5k_tx_queue()
1637 spin_unlock_irqrestore(&ah->txbuflock, flags); in ath5k_tx_queue()
1641 bf = list_first_entry(&ah->txbuf, struct ath5k_buf, list); in ath5k_tx_queue()
1643 ah->txbuf_len--; in ath5k_tx_queue()
1644 if (list_empty(&ah->txbuf)) in ath5k_tx_queue()
1646 spin_unlock_irqrestore(&ah->txbuflock, flags); in ath5k_tx_queue()
1650 if (ath5k_txbuf_setup(ah, bf, txq, padsize, control)) { in ath5k_tx_queue()
1652 spin_lock_irqsave(&ah->txbuflock, flags); in ath5k_tx_queue()
1653 list_add_tail(&bf->list, &ah->txbuf); in ath5k_tx_queue()
1654 ah->txbuf_len++; in ath5k_tx_queue()
1655 spin_unlock_irqrestore(&ah->txbuflock, flags); in ath5k_tx_queue()
1665 ath5k_tx_frame_completed(struct ath5k_hw *ah, struct sk_buff *skb, in ath5k_tx_frame_completed() argument
1674 ah->stats.tx_all_count++; in ath5k_tx_frame_completed()
1675 ah->stats.tx_bytes_count += skb->len; in ath5k_tx_frame_completed()
1698 ah->stats.ack_fail++; in ath5k_tx_frame_completed()
1701 ah->stats.txerr_filt++; in ath5k_tx_frame_completed()
1704 ah->stats.txerr_retry++; in ath5k_tx_frame_completed()
1706 ah->stats.txerr_fifo++; in ath5k_tx_frame_completed()
1722 ah->stats.antenna_tx[ts->ts_antenna]++; in ath5k_tx_frame_completed()
1724 ah->stats.antenna_tx[0]++; /* invalid */ in ath5k_tx_frame_completed()
1726 trace_ath5k_tx_complete(ah, skb, txq, ts); in ath5k_tx_frame_completed()
1727 ieee80211_tx_status(ah->hw, skb); in ath5k_tx_frame_completed()
1731 ath5k_tx_processq(struct ath5k_hw *ah, struct ath5k_txq *txq) in ath5k_tx_processq() argument
1748 ret = ah->ah_proc_tx_desc(ah, ds, &ts); in ath5k_tx_processq()
1752 ATH5K_ERR(ah, in ath5k_tx_processq()
1761 dma_unmap_single(ah->dev, bf->skbaddr, skb->len, in ath5k_tx_processq()
1763 ath5k_tx_frame_completed(ah, skb, txq, &ts, bf); in ath5k_tx_processq()
1772 if (ath5k_hw_get_txdp(ah, txq->qnum) != bf->daddr) { in ath5k_tx_processq()
1773 spin_lock(&ah->txbuflock); in ath5k_tx_processq()
1774 list_move_tail(&bf->list, &ah->txbuf); in ath5k_tx_processq()
1775 ah->txbuf_len++; in ath5k_tx_processq()
1777 spin_unlock(&ah->txbuflock); in ath5k_tx_processq()
1782 ieee80211_wake_queue(ah->hw, txq->qnum); in ath5k_tx_processq()
1789 struct ath5k_hw *ah = from_tasklet(ah, t, txtq); in ath5k_tasklet_tx() local
1792 if (ah->txqs[i].setup && (ah->ah_txq_isr_txok_all & BIT(i))) in ath5k_tasklet_tx()
1793 ath5k_tx_processq(ah, &ah->txqs[i]); in ath5k_tasklet_tx()
1795 ah->tx_pending = false; in ath5k_tasklet_tx()
1796 ath5k_set_current_imask(ah); in ath5k_tasklet_tx()
1808 ath5k_beacon_setup(struct ath5k_hw *ah, struct ath5k_buf *bf) in ath5k_beacon_setup() argument
1818 bf->skbaddr = dma_map_single(ah->dev, skb->data, skb->len, in ath5k_beacon_setup()
1820 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] " in ath5k_beacon_setup()
1824 if (dma_mapping_error(ah->dev, bf->skbaddr)) { in ath5k_beacon_setup()
1825 ATH5K_ERR(ah, "beacon DMA mapping failed\n"); in ath5k_beacon_setup()
1832 antenna = ah->ah_tx_ant; in ath5k_beacon_setup()
1835 if (ah->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) { in ath5k_beacon_setup()
1859 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP) in ath5k_beacon_setup()
1860 antenna = ah->bsent & 4 ? 2 : 1; in ath5k_beacon_setup()
1867 ret = ah->ah_setup_tx_desc(ah, ds, skb->len, in ath5k_beacon_setup()
1870 (ah->ah_txpower.txp_requested * 2), in ath5k_beacon_setup()
1871 ieee80211_get_tx_rate(ah->hw, info)->hw_value, in ath5k_beacon_setup()
1879 dma_unmap_single(ah->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE); in ath5k_beacon_setup()
1894 struct ath5k_hw *ah = hw->priv; in ath5k_beacon_update() local
1911 ath5k_txbuf_free_skb(ah, avf->bbuf); in ath5k_beacon_update()
1913 ret = ath5k_beacon_setup(ah, avf->bbuf); in ath5k_beacon_update()
1927 ath5k_beacon_send(struct ath5k_hw *ah) in ath5k_beacon_send() argument
1935 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, "in beacon_send\n"); in ath5k_beacon_send()
1944 if (unlikely(ath5k_hw_num_tx_pending(ah, ah->bhalq) != 0)) { in ath5k_beacon_send()
1945 ah->bmisscount++; in ath5k_beacon_send()
1946 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, in ath5k_beacon_send()
1947 "missed %u consecutive beacons\n", ah->bmisscount); in ath5k_beacon_send()
1948 if (ah->bmisscount > 10) { /* NB: 10 is a guess */ in ath5k_beacon_send()
1949 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, in ath5k_beacon_send()
1951 ah->bmisscount); in ath5k_beacon_send()
1952 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, in ath5k_beacon_send()
1954 ieee80211_queue_work(ah->hw, &ah->reset_work); in ath5k_beacon_send()
1958 if (unlikely(ah->bmisscount != 0)) { in ath5k_beacon_send()
1959 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, in ath5k_beacon_send()
1961 ah->bmisscount); in ath5k_beacon_send()
1962 ah->bmisscount = 0; in ath5k_beacon_send()
1965 if ((ah->opmode == NL80211_IFTYPE_AP && ah->num_ap_vifs + in ath5k_beacon_send()
1966 ah->num_mesh_vifs > 1) || in ath5k_beacon_send()
1967 ah->opmode == NL80211_IFTYPE_MESH_POINT) { in ath5k_beacon_send()
1968 u64 tsf = ath5k_hw_get_tsf64(ah); in ath5k_beacon_send()
1970 int slot = ((tsftu % ah->bintval) * ATH_BCBUF) / ah->bintval; in ath5k_beacon_send()
1971 vif = ah->bslot[(slot + 1) % ATH_BCBUF]; in ath5k_beacon_send()
1972 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, in ath5k_beacon_send()
1974 (unsigned long long)tsf, tsftu, ah->bintval, slot, vif); in ath5k_beacon_send()
1976 vif = ah->bslot[0]; in ath5k_beacon_send()
1989 if (unlikely(ath5k_hw_stop_beacon_queue(ah, ah->bhalq))) { in ath5k_beacon_send()
1990 ATH5K_WARN(ah, "beacon queue %u didn't start/stop ?\n", ah->bhalq); in ath5k_beacon_send()
1995 if (ah->opmode == NL80211_IFTYPE_AP || in ath5k_beacon_send()
1996 ah->opmode == NL80211_IFTYPE_MESH_POINT) { in ath5k_beacon_send()
1997 err = ath5k_beacon_update(ah->hw, vif); in ath5k_beacon_send()
2002 if (unlikely(bf->skb == NULL || ah->opmode == NL80211_IFTYPE_STATION || in ath5k_beacon_send()
2003 ah->opmode == NL80211_IFTYPE_MONITOR)) { in ath5k_beacon_send()
2004 ATH5K_WARN(ah, "bf=%p bf_skb=%p\n", bf, bf->skb); in ath5k_beacon_send()
2008 trace_ath5k_tx(ah, bf->skb, &ah->txqs[ah->bhalq]); in ath5k_beacon_send()
2010 ath5k_hw_set_txdp(ah, ah->bhalq, bf->daddr); in ath5k_beacon_send()
2011 ath5k_hw_start_tx_dma(ah, ah->bhalq); in ath5k_beacon_send()
2012 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n", in ath5k_beacon_send()
2013 ah->bhalq, (unsigned long long)bf->daddr, bf->desc); in ath5k_beacon_send()
2015 skb = ieee80211_get_buffered_bc(ah->hw, vif); in ath5k_beacon_send()
2017 ath5k_tx_queue(ah->hw, skb, ah->cabq, NULL); in ath5k_beacon_send()
2019 if (ah->cabq->txq_len >= ah->cabq->txq_max) in ath5k_beacon_send()
2022 skb = ieee80211_get_buffered_bc(ah->hw, vif); in ath5k_beacon_send()
2025 ah->bsent++; in ath5k_beacon_send()
2045 ath5k_beacon_update_timers(struct ath5k_hw *ah, u64 bc_tsf) in ath5k_beacon_update_timers() argument
2050 intval = ah->bintval & AR5K_BEACON_PERIOD; in ath5k_beacon_update_timers()
2051 if (ah->opmode == NL80211_IFTYPE_AP && ah->num_ap_vifs in ath5k_beacon_update_timers()
2052 + ah->num_mesh_vifs > 1) { in ath5k_beacon_update_timers()
2055 ATH5K_WARN(ah, "intval %u is too low, min 15\n", in ath5k_beacon_update_timers()
2065 hw_tsf = ath5k_hw_get_tsf64(ah); in ath5k_beacon_update_timers()
2094 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, in ath5k_beacon_update_timers()
2109 ah->nexttbtt = nexttbtt; in ath5k_beacon_update_timers()
2112 ath5k_hw_init_beacon_timers(ah, nexttbtt, intval); in ath5k_beacon_update_timers()
2119 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, in ath5k_beacon_update_timers()
2122 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, in ath5k_beacon_update_timers()
2125 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, in ath5k_beacon_update_timers()
2128 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, in ath5k_beacon_update_timers()
2132 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, "intval %u %s %s\n", in ath5k_beacon_update_timers()
2147 ath5k_beacon_config(struct ath5k_hw *ah) in ath5k_beacon_config() argument
2149 spin_lock_bh(&ah->block); in ath5k_beacon_config()
2150 ah->bmisscount = 0; in ath5k_beacon_config()
2151 ah->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA); in ath5k_beacon_config()
2153 if (ah->enable_beacon) { in ath5k_beacon_config()
2161 ath5k_beaconq_config(ah); in ath5k_beacon_config()
2163 ah->imask |= AR5K_INT_SWBA; in ath5k_beacon_config()
2165 if (ah->opmode == NL80211_IFTYPE_ADHOC) { in ath5k_beacon_config()
2166 if (ath5k_hw_hasveol(ah)) in ath5k_beacon_config()
2167 ath5k_beacon_send(ah); in ath5k_beacon_config()
2169 ath5k_beacon_update_timers(ah, -1); in ath5k_beacon_config()
2171 ath5k_hw_stop_beacon_queue(ah, ah->bhalq); in ath5k_beacon_config()
2174 ath5k_hw_set_imr(ah, ah->imask); in ath5k_beacon_config()
2175 spin_unlock_bh(&ah->block); in ath5k_beacon_config()
2180 struct ath5k_hw *ah = from_tasklet(ah, t, beacontq); in ath5k_tasklet_beacon() local
2190 if (ah->opmode == NL80211_IFTYPE_ADHOC) { in ath5k_tasklet_beacon()
2192 u64 tsf = ath5k_hw_get_tsf64(ah); in ath5k_tasklet_beacon()
2193 ah->nexttbtt += ah->bintval; in ath5k_tasklet_beacon()
2194 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, in ath5k_tasklet_beacon()
2197 ah->nexttbtt, in ath5k_tasklet_beacon()
2201 spin_lock(&ah->block); in ath5k_tasklet_beacon()
2202 ath5k_beacon_send(ah); in ath5k_tasklet_beacon()
2203 spin_unlock(&ah->block); in ath5k_tasklet_beacon()
2213 ath5k_intr_calibration_poll(struct ath5k_hw *ah) in ath5k_intr_calibration_poll() argument
2215 if (time_is_before_eq_jiffies(ah->ah_cal_next_ani) && in ath5k_intr_calibration_poll()
2216 !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL) && in ath5k_intr_calibration_poll()
2217 !(ah->ah_cal_mask & AR5K_CALIBRATION_SHORT)) { in ath5k_intr_calibration_poll()
2221 ah->ah_cal_next_ani = jiffies + in ath5k_intr_calibration_poll()
2223 tasklet_schedule(&ah->ani_tasklet); in ath5k_intr_calibration_poll()
2225 } else if (time_is_before_eq_jiffies(ah->ah_cal_next_short) && in ath5k_intr_calibration_poll()
2226 !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL) && in ath5k_intr_calibration_poll()
2227 !(ah->ah_cal_mask & AR5K_CALIBRATION_SHORT)) { in ath5k_intr_calibration_poll()
2236 ah->ah_cal_next_short = jiffies + in ath5k_intr_calibration_poll()
2238 ieee80211_queue_work(ah->hw, &ah->calib_work); in ath5k_intr_calibration_poll()
2246 ath5k_schedule_rx(struct ath5k_hw *ah) in ath5k_schedule_rx() argument
2248 ah->rx_pending = true; in ath5k_schedule_rx()
2249 tasklet_schedule(&ah->rxtq); in ath5k_schedule_rx()
2253 ath5k_schedule_tx(struct ath5k_hw *ah) in ath5k_schedule_tx() argument
2255 ah->tx_pending = true; in ath5k_schedule_tx()
2256 tasklet_schedule(&ah->txtq); in ath5k_schedule_tx()
2262 struct ath5k_hw *ah = dev_id; in ath5k_intr() local
2277 if (unlikely(test_bit(ATH_STAT_INVALID, ah->status) || in ath5k_intr()
2278 ((ath5k_get_bus_type(ah) != ATH_AHB) && in ath5k_intr()
2279 !ath5k_hw_is_intr_pending(ah)))) in ath5k_intr()
2284 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */ in ath5k_intr()
2286 ATH5K_DBG(ah, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n", in ath5k_intr()
2287 status, ah->imask); in ath5k_intr()
2298 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, in ath5k_intr()
2300 ieee80211_queue_work(ah->hw, &ah->reset_work); in ath5k_intr()
2317 ah->stats.rxorn_intr++; in ath5k_intr()
2319 if (ah->ah_mac_srev < AR5K_SREV_AR5212) { in ath5k_intr()
2320 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, in ath5k_intr()
2322 ieee80211_queue_work(ah->hw, &ah->reset_work); in ath5k_intr()
2324 ath5k_schedule_rx(ah); in ath5k_intr()
2330 tasklet_hi_schedule(&ah->beacontq); in ath5k_intr()
2340 ah->stats.rxeol_intr++; in ath5k_intr()
2345 ath5k_hw_update_tx_triglevel(ah, true); in ath5k_intr()
2349 ath5k_schedule_rx(ah); in ath5k_intr()
2356 ath5k_schedule_tx(ah); in ath5k_intr()
2364 ah->stats.mib_intr++; in ath5k_intr()
2365 ath5k_hw_update_mib_counters(ah); in ath5k_intr()
2366 ath5k_ani_mib_intr(ah); in ath5k_intr()
2371 tasklet_schedule(&ah->rf_kill.toggleq); in ath5k_intr()
2375 if (ath5k_get_bus_type(ah) == ATH_AHB) in ath5k_intr()
2378 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0); in ath5k_intr()
2386 if (ah->rx_pending || ah->tx_pending) in ath5k_intr()
2387 ath5k_set_current_imask(ah); in ath5k_intr()
2390 ATH5K_WARN(ah, "too many interrupts, giving up for now\n"); in ath5k_intr()
2393 ath5k_intr_calibration_poll(ah); in ath5k_intr()
2405 struct ath5k_hw *ah = container_of(work, struct ath5k_hw, in ath5k_calibrate_work() local
2409 if (time_is_before_eq_jiffies(ah->ah_cal_next_full)) { in ath5k_calibrate_work()
2411 ah->ah_cal_next_full = jiffies + in ath5k_calibrate_work()
2413 ah->ah_cal_mask |= AR5K_CALIBRATION_FULL; in ath5k_calibrate_work()
2415 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, in ath5k_calibrate_work()
2418 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) { in ath5k_calibrate_work()
2423 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, in ath5k_calibrate_work()
2425 ieee80211_queue_work(ah->hw, &ah->reset_work); in ath5k_calibrate_work()
2428 ah->ah_cal_mask |= AR5K_CALIBRATION_SHORT; in ath5k_calibrate_work()
2431 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n", in ath5k_calibrate_work()
2432 ieee80211_frequency_to_channel(ah->curchan->center_freq), in ath5k_calibrate_work()
2433 ah->curchan->hw_value); in ath5k_calibrate_work()
2435 if (ath5k_hw_phy_calibrate(ah, ah->curchan)) in ath5k_calibrate_work()
2436 ATH5K_ERR(ah, "calibration of channel %u failed\n", in ath5k_calibrate_work()
2438 ah->curchan->center_freq)); in ath5k_calibrate_work()
2441 if (ah->ah_cal_mask & AR5K_CALIBRATION_FULL) in ath5k_calibrate_work()
2442 ah->ah_cal_mask &= ~AR5K_CALIBRATION_FULL; in ath5k_calibrate_work()
2443 else if (ah->ah_cal_mask & AR5K_CALIBRATION_SHORT) in ath5k_calibrate_work()
2444 ah->ah_cal_mask &= ~AR5K_CALIBRATION_SHORT; in ath5k_calibrate_work()
2451 struct ath5k_hw *ah = from_tasklet(ah, t, ani_tasklet); in ath5k_tasklet_ani() local
2453 ah->ah_cal_mask |= AR5K_CALIBRATION_ANI; in ath5k_tasklet_ani()
2454 ath5k_ani_calibration(ah); in ath5k_tasklet_ani()
2455 ah->ah_cal_mask &= ~AR5K_CALIBRATION_ANI; in ath5k_tasklet_ani()
2462 struct ath5k_hw *ah = container_of(work, struct ath5k_hw, in ath5k_tx_complete_poll_work() local
2468 if (!test_bit(ATH_STAT_STARTED, ah->status)) in ath5k_tx_complete_poll_work()
2471 mutex_lock(&ah->lock); in ath5k_tx_complete_poll_work()
2473 for (i = 0; i < ARRAY_SIZE(ah->txqs); i++) { in ath5k_tx_complete_poll_work()
2474 if (ah->txqs[i].setup) { in ath5k_tx_complete_poll_work()
2475 txq = &ah->txqs[i]; in ath5k_tx_complete_poll_work()
2479 ATH5K_DBG(ah, ATH5K_DEBUG_XMIT, in ath5k_tx_complete_poll_work()
2495 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, in ath5k_tx_complete_poll_work()
2497 ath5k_reset(ah, NULL, true); in ath5k_tx_complete_poll_work()
2500 mutex_unlock(&ah->lock); in ath5k_tx_complete_poll_work()
2502 ieee80211_queue_delayed_work(ah->hw, &ah->tx_complete_work, in ath5k_tx_complete_poll_work()
2528 ath5k_init_ah(struct ath5k_hw *ah, const struct ath_bus_ops *bus_ops) in ath5k_init_ah() argument
2530 struct ieee80211_hw *hw = ah->hw; in ath5k_init_ah()
2536 SET_IEEE80211_DEV(hw, ah->dev); in ath5k_init_ah()
2570 __set_bit(ATH_STAT_INVALID, ah->status); in ath5k_init_ah()
2572 ah->opmode = NL80211_IFTYPE_STATION; in ath5k_init_ah()
2573 ah->bintval = 1000; in ath5k_init_ah()
2574 mutex_init(&ah->lock); in ath5k_init_ah()
2575 spin_lock_init(&ah->rxbuflock); in ath5k_init_ah()
2576 spin_lock_init(&ah->txbuflock); in ath5k_init_ah()
2577 spin_lock_init(&ah->block); in ath5k_init_ah()
2578 spin_lock_init(&ah->irqlock); in ath5k_init_ah()
2581 ret = request_irq(ah->irq, ath5k_intr, IRQF_SHARED, "ath", ah); in ath5k_init_ah()
2583 ATH5K_ERR(ah, "request_irq failed\n"); in ath5k_init_ah()
2587 common = ath5k_hw_common(ah); in ath5k_init_ah()
2590 common->ah = ah; in ath5k_init_ah()
2592 common->priv = ah; in ath5k_init_ah()
2605 ret = ath5k_hw_init(ah); in ath5k_init_ah()
2610 if (ah->ah_capabilities.cap_has_mrr_support) { in ath5k_init_ah()
2623 ATH5K_INFO(ah, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n", in ath5k_init_ah()
2624 ath5k_chip_name(AR5K_VERSION_MAC, ah->ah_mac_srev), in ath5k_init_ah()
2625 ah->ah_mac_srev, in ath5k_init_ah()
2626 ah->ah_phy_revision); in ath5k_init_ah()
2628 if (!ah->ah_single_chip) { in ath5k_init_ah()
2630 if (ah->ah_radio_5ghz_revision && in ath5k_init_ah()
2631 !ah->ah_radio_2ghz_revision) { in ath5k_init_ah()
2634 ah->ah_capabilities.cap_mode)) { in ath5k_init_ah()
2635 ATH5K_INFO(ah, "RF%s 2GHz radio found (0x%x)\n", in ath5k_init_ah()
2637 ah->ah_radio_5ghz_revision), in ath5k_init_ah()
2638 ah->ah_radio_5ghz_revision); in ath5k_init_ah()
2642 ah->ah_capabilities.cap_mode)) { in ath5k_init_ah()
2643 ATH5K_INFO(ah, "RF%s 5GHz radio found (0x%x)\n", in ath5k_init_ah()
2645 ah->ah_radio_5ghz_revision), in ath5k_init_ah()
2646 ah->ah_radio_5ghz_revision); in ath5k_init_ah()
2649 ATH5K_INFO(ah, "RF%s multiband radio found" in ath5k_init_ah()
2652 ah->ah_radio_5ghz_revision), in ath5k_init_ah()
2653 ah->ah_radio_5ghz_revision); in ath5k_init_ah()
2658 else if (ah->ah_radio_5ghz_revision && in ath5k_init_ah()
2659 ah->ah_radio_2ghz_revision) { in ath5k_init_ah()
2660 ATH5K_INFO(ah, "RF%s 5GHz radio found (0x%x)\n", in ath5k_init_ah()
2662 ah->ah_radio_5ghz_revision), in ath5k_init_ah()
2663 ah->ah_radio_5ghz_revision); in ath5k_init_ah()
2664 ATH5K_INFO(ah, "RF%s 2GHz radio found (0x%x)\n", in ath5k_init_ah()
2666 ah->ah_radio_2ghz_revision), in ath5k_init_ah()
2667 ah->ah_radio_2ghz_revision); in ath5k_init_ah()
2671 ath5k_debug_init_device(ah); in ath5k_init_ah()
2674 __clear_bit(ATH_STAT_INVALID, ah->status); in ath5k_init_ah()
2678 ath5k_hw_deinit(ah); in ath5k_init_ah()
2680 free_irq(ah->irq, ah); in ath5k_init_ah()
2686 ath5k_stop_locked(struct ath5k_hw *ah) in ath5k_stop_locked() argument
2689 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "invalid %u\n", in ath5k_stop_locked()
2690 test_bit(ATH_STAT_INVALID, ah->status)); in ath5k_stop_locked()
2707 ieee80211_stop_queues(ah->hw); in ath5k_stop_locked()
2709 if (!test_bit(ATH_STAT_INVALID, ah->status)) { in ath5k_stop_locked()
2710 ath5k_led_off(ah); in ath5k_stop_locked()
2711 ath5k_hw_set_imr(ah, 0); in ath5k_stop_locked()
2712 synchronize_irq(ah->irq); in ath5k_stop_locked()
2713 ath5k_rx_stop(ah); in ath5k_stop_locked()
2714 ath5k_hw_dma_stop(ah); in ath5k_stop_locked()
2715 ath5k_drain_tx_buffs(ah); in ath5k_stop_locked()
2716 ath5k_hw_phy_disable(ah); in ath5k_stop_locked()
2724 struct ath5k_hw *ah = hw->priv; in ath5k_start() local
2725 struct ath_common *common = ath5k_hw_common(ah); in ath5k_start()
2728 mutex_lock(&ah->lock); in ath5k_start()
2730 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "mode %d\n", ah->opmode); in ath5k_start()
2736 ath5k_stop_locked(ah); in ath5k_start()
2745 ah->curchan = ah->hw->conf.chandef.chan; in ath5k_start()
2746 ah->imask = AR5K_INT_RXOK in ath5k_start()
2756 ret = ath5k_reset(ah, NULL, false); in ath5k_start()
2761 ath5k_rfkill_hw_start(ah); in ath5k_start()
2772 ah->ah_ack_bitrate_high = true; in ath5k_start()
2774 for (i = 0; i < ARRAY_SIZE(ah->bslot); i++) in ath5k_start()
2775 ah->bslot[i] = NULL; in ath5k_start()
2779 mutex_unlock(&ah->lock); in ath5k_start()
2781 set_bit(ATH_STAT_STARTED, ah->status); in ath5k_start()
2782 ieee80211_queue_delayed_work(ah->hw, &ah->tx_complete_work, in ath5k_start()
2788 static void ath5k_stop_tasklets(struct ath5k_hw *ah) in ath5k_stop_tasklets() argument
2790 ah->rx_pending = false; in ath5k_stop_tasklets()
2791 ah->tx_pending = false; in ath5k_stop_tasklets()
2792 tasklet_kill(&ah->rxtq); in ath5k_stop_tasklets()
2793 tasklet_kill(&ah->txtq); in ath5k_stop_tasklets()
2794 tasklet_kill(&ah->beacontq); in ath5k_stop_tasklets()
2795 tasklet_kill(&ah->ani_tasklet); in ath5k_stop_tasklets()
2806 struct ath5k_hw *ah = hw->priv; in ath5k_stop() local
2809 mutex_lock(&ah->lock); in ath5k_stop()
2810 ret = ath5k_stop_locked(ah); in ath5k_stop()
2811 if (ret == 0 && !test_bit(ATH_STAT_INVALID, ah->status)) { in ath5k_stop()
2832 ret = ath5k_hw_on_hold(ah); in ath5k_stop()
2834 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, in ath5k_stop()
2838 mutex_unlock(&ah->lock); in ath5k_stop()
2840 ath5k_stop_tasklets(ah); in ath5k_stop()
2842 clear_bit(ATH_STAT_STARTED, ah->status); in ath5k_stop()
2843 cancel_delayed_work_sync(&ah->tx_complete_work); in ath5k_stop()
2846 ath5k_rfkill_hw_stop(ah); in ath5k_stop()
2856 ath5k_reset(struct ath5k_hw *ah, struct ieee80211_channel *chan, in ath5k_reset() argument
2859 struct ath_common *common = ath5k_hw_common(ah); in ath5k_reset()
2863 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "resetting\n"); in ath5k_reset()
2865 __set_bit(ATH_STAT_RESET, ah->status); in ath5k_reset()
2867 ath5k_hw_set_imr(ah, 0); in ath5k_reset()
2868 synchronize_irq(ah->irq); in ath5k_reset()
2869 ath5k_stop_tasklets(ah); in ath5k_reset()
2874 ani_mode = ah->ani_state.ani_mode; in ath5k_reset()
2875 ath5k_ani_init(ah, ATH5K_ANI_MODE_OFF); in ath5k_reset()
2880 ath5k_drain_tx_buffs(ah); in ath5k_reset()
2883 ath5k_hw_stop_rx_pcu(ah); in ath5k_reset()
2890 ret = ath5k_hw_dma_stop(ah); in ath5k_reset()
2896 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, in ath5k_reset()
2902 ah->curchan = chan; in ath5k_reset()
2904 ret = ath5k_hw_reset(ah, ah->opmode, ah->curchan, fast, skip_pcu); in ath5k_reset()
2906 ATH5K_ERR(ah, "can't reset hardware (%d)\n", ret); in ath5k_reset()
2910 ret = ath5k_rx_start(ah); in ath5k_reset()
2912 ATH5K_ERR(ah, "can't start recv logic\n"); in ath5k_reset()
2916 ath5k_ani_init(ah, ani_mode); in ath5k_reset()
2929 ah->ah_cal_next_full = jiffies + in ath5k_reset()
2931 ah->ah_cal_next_ani = jiffies + in ath5k_reset()
2933 ah->ah_cal_next_short = jiffies + in ath5k_reset()
2936 ewma_beacon_rssi_init(&ah->ah_beacon_rssi_avg); in ath5k_reset()
2939 memset(&ah->survey, 0, sizeof(ah->survey)); in ath5k_reset()
2957 __clear_bit(ATH_STAT_RESET, ah->status); in ath5k_reset()
2959 ath5k_beacon_config(ah); in ath5k_reset()
2962 ieee80211_wake_queues(ah->hw); in ath5k_reset()
2971 struct ath5k_hw *ah = container_of(work, struct ath5k_hw, in ath5k_reset_work() local
2974 mutex_lock(&ah->lock); in ath5k_reset_work()
2975 ath5k_reset(ah, NULL, true); in ath5k_reset_work()
2976 mutex_unlock(&ah->lock); in ath5k_reset_work()
2983 struct ath5k_hw *ah = hw->priv; in ath5k_init() local
2984 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah); in ath5k_init()
2998 ATH5K_ERR(ah, "can't get channels\n"); in ath5k_init()
3005 ret = ath5k_desc_alloc(ah); in ath5k_init()
3007 ATH5K_ERR(ah, "can't allocate descriptors\n"); in ath5k_init()
3017 ret = ath5k_beaconq_setup(ah); in ath5k_init()
3019 ATH5K_ERR(ah, "can't setup a beacon xmit queue\n"); in ath5k_init()
3022 ah->bhalq = ret; in ath5k_init()
3023 ah->cabq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_CAB, 0); in ath5k_init()
3024 if (IS_ERR(ah->cabq)) { in ath5k_init()
3025 ATH5K_ERR(ah, "can't setup cab queue\n"); in ath5k_init()
3026 ret = PTR_ERR(ah->cabq); in ath5k_init()
3032 if (ah->ah_capabilities.cap_queues.q_tx_num >= 6) { in ath5k_init()
3035 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VO); in ath5k_init()
3037 ATH5K_ERR(ah, "can't setup xmit queue\n"); in ath5k_init()
3041 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VI); in ath5k_init()
3043 ATH5K_ERR(ah, "can't setup xmit queue\n"); in ath5k_init()
3047 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE); in ath5k_init()
3049 ATH5K_ERR(ah, "can't setup xmit queue\n"); in ath5k_init()
3053 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK); in ath5k_init()
3055 ATH5K_ERR(ah, "can't setup xmit queue\n"); in ath5k_init()
3062 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE); in ath5k_init()
3064 ATH5K_ERR(ah, "can't setup xmit queue\n"); in ath5k_init()
3071 tasklet_setup(&ah->rxtq, ath5k_tasklet_rx); in ath5k_init()
3072 tasklet_setup(&ah->txtq, ath5k_tasklet_tx); in ath5k_init()
3073 tasklet_setup(&ah->beacontq, ath5k_tasklet_beacon); in ath5k_init()
3074 tasklet_setup(&ah->ani_tasklet, ath5k_tasklet_ani); in ath5k_init()
3076 INIT_WORK(&ah->reset_work, ath5k_reset_work); in ath5k_init()
3077 INIT_WORK(&ah->calib_work, ath5k_calibrate_work); in ath5k_init()
3078 INIT_DELAYED_WORK(&ah->tx_complete_work, ath5k_tx_complete_poll_work); in ath5k_init()
3080 ret = ath5k_hw_common(ah)->bus_ops->eeprom_read_mac(ah, mac); in ath5k_init()
3082 ATH5K_ERR(ah, "unable to read address from EEPROM\n"); in ath5k_init()
3088 ath5k_update_bssid_mask_and_opmode(ah, NULL); in ath5k_init()
3090 regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain; in ath5k_init()
3093 ATH5K_ERR(ah, "can't initialize regulatory system\n"); in ath5k_init()
3099 ATH5K_ERR(ah, "can't register ieee80211 hw\n"); in ath5k_init()
3106 ath5k_init_leds(ah); in ath5k_init()
3108 ath5k_sysfs_register(ah); in ath5k_init()
3112 ath5k_txq_release(ah); in ath5k_init()
3114 ath5k_hw_release_tx_queue(ah, ah->bhalq); in ath5k_init()
3116 ath5k_desc_free(ah); in ath5k_init()
3122 ath5k_deinit_ah(struct ath5k_hw *ah) in ath5k_deinit_ah() argument
3124 struct ieee80211_hw *hw = ah->hw; in ath5k_deinit_ah()
3140 ath5k_desc_free(ah); in ath5k_deinit_ah()
3141 ath5k_txq_release(ah); in ath5k_deinit_ah()
3142 ath5k_hw_release_tx_queue(ah, ah->bhalq); in ath5k_deinit_ah()
3143 ath5k_unregister_leds(ah); in ath5k_deinit_ah()
3145 ath5k_sysfs_unregister(ah); in ath5k_deinit_ah()
3151 ath5k_hw_deinit(ah); in ath5k_deinit_ah()
3152 free_irq(ah->irq, ah); in ath5k_deinit_ah()
3156 ath5k_any_vif_assoc(struct ath5k_hw *ah) in ath5k_any_vif_assoc() argument
3165 ah->hw, IEEE80211_IFACE_ITER_RESUME_ALL, in ath5k_any_vif_assoc()
3173 struct ath5k_hw *ah = hw->priv; in ath5k_set_beacon_filter() local
3175 rfilt = ath5k_hw_get_rx_filter(ah); in ath5k_set_beacon_filter()
3180 ath5k_hw_set_rx_filter(ah, rfilt); in ath5k_set_beacon_filter()
3181 ah->filter_flags = rfilt; in ath5k_set_beacon_filter()
3184 void _ath5k_printk(const struct ath5k_hw *ah, const char *level, in _ath5k_printk() argument
3195 if (ah && ah->hw) in _ath5k_printk()
3197 level, wiphy_name(ah->hw->wiphy), &vaf); in _ath5k_printk()