Lines Matching refs:ah
48 ath5k_hw_start_rx_dma(struct ath5k_hw *ah) in ath5k_hw_start_rx_dma() argument
50 ath5k_hw_reg_write(ah, AR5K_CR_RXE, AR5K_CR); in ath5k_hw_start_rx_dma()
51 ath5k_hw_reg_read(ah, AR5K_CR); in ath5k_hw_start_rx_dma()
59 ath5k_hw_stop_rx_dma(struct ath5k_hw *ah) in ath5k_hw_stop_rx_dma() argument
63 ath5k_hw_reg_write(ah, AR5K_CR_RXD, AR5K_CR); in ath5k_hw_stop_rx_dma()
69 (ath5k_hw_reg_read(ah, AR5K_CR) & AR5K_CR_RXE) != 0; in ath5k_hw_stop_rx_dma()
74 ATH5K_DBG(ah, ATH5K_DEBUG_DMA, in ath5k_hw_stop_rx_dma()
85 ath5k_hw_get_rxdp(struct ath5k_hw *ah) in ath5k_hw_get_rxdp() argument
87 return ath5k_hw_reg_read(ah, AR5K_RXDP); in ath5k_hw_get_rxdp()
98 ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr) in ath5k_hw_set_rxdp() argument
100 if (ath5k_hw_reg_read(ah, AR5K_CR) & AR5K_CR_RXE) { in ath5k_hw_set_rxdp()
101 ATH5K_DBG(ah, ATH5K_DEBUG_DMA, in ath5k_hw_set_rxdp()
106 ath5k_hw_reg_write(ah, phys_addr, AR5K_RXDP); in ath5k_hw_set_rxdp()
130 ath5k_hw_start_tx_dma(struct ath5k_hw *ah, unsigned int queue) in ath5k_hw_start_tx_dma() argument
134 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num); in ath5k_hw_start_tx_dma()
137 if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE) in ath5k_hw_start_tx_dma()
140 if (ah->ah_version == AR5K_AR5210) { in ath5k_hw_start_tx_dma()
141 tx_queue = ath5k_hw_reg_read(ah, AR5K_CR); in ath5k_hw_start_tx_dma()
146 switch (ah->ah_txq[queue].tqi_type) { in ath5k_hw_start_tx_dma()
152 ath5k_hw_reg_write(ah, AR5K_BCR_TQ1V | AR5K_BCR_BDMAE, in ath5k_hw_start_tx_dma()
157 ath5k_hw_reg_write(ah, AR5K_BCR_TQ1FV | AR5K_BCR_TQ1V | in ath5k_hw_start_tx_dma()
164 ath5k_hw_reg_write(ah, tx_queue, AR5K_CR); in ath5k_hw_start_tx_dma()
165 ath5k_hw_reg_read(ah, AR5K_CR); in ath5k_hw_start_tx_dma()
168 if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXD, queue)) in ath5k_hw_start_tx_dma()
172 AR5K_REG_WRITE_Q(ah, AR5K_QCU_TXE, queue); in ath5k_hw_start_tx_dma()
188 ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue) in ath5k_hw_stop_tx_dma() argument
193 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num); in ath5k_hw_stop_tx_dma()
196 if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE) in ath5k_hw_stop_tx_dma()
199 if (ah->ah_version == AR5K_AR5210) { in ath5k_hw_stop_tx_dma()
200 tx_queue = ath5k_hw_reg_read(ah, AR5K_CR); in ath5k_hw_stop_tx_dma()
205 switch (ah->ah_txq[queue].tqi_type) { in ath5k_hw_stop_tx_dma()
213 ath5k_hw_reg_write(ah, 0, AR5K_BSR); in ath5k_hw_stop_tx_dma()
220 ath5k_hw_reg_write(ah, tx_queue, AR5K_CR); in ath5k_hw_stop_tx_dma()
221 ath5k_hw_reg_read(ah, AR5K_CR); in ath5k_hw_stop_tx_dma()
228 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue), in ath5k_hw_stop_tx_dma()
234 AR5K_REG_WRITE_Q(ah, AR5K_QCU_TXD, queue); in ath5k_hw_stop_tx_dma()
238 (AR5K_REG_READ_Q(ah, AR5K_QCU_TXE, queue) != 0); in ath5k_hw_stop_tx_dma()
242 if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXE, queue)) in ath5k_hw_stop_tx_dma()
243 ATH5K_DBG(ah, ATH5K_DEBUG_DMA, in ath5k_hw_stop_tx_dma()
249 pending = ath5k_hw_reg_read(ah, in ath5k_hw_stop_tx_dma()
257 if (ah->ah_mac_version >= (AR5K_SREV_AR2414 >> 4) && in ath5k_hw_stop_tx_dma()
260 ath5k_hw_reg_write(ah, in ath5k_hw_stop_tx_dma()
266 ath5k_hw_reg_write(ah, in ath5k_hw_stop_tx_dma()
268 AR5K_REG_SM(ath5k_hw_reg_read(ah, in ath5k_hw_stop_tx_dma()
274 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5211, in ath5k_hw_stop_tx_dma()
279 AR5K_REG_DISABLE_BITS(ah, AR5K_QUIET_CTL1, in ath5k_hw_stop_tx_dma()
285 pending = ath5k_hw_reg_read(ah, in ath5k_hw_stop_tx_dma()
291 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW_5211, in ath5k_hw_stop_tx_dma()
295 ATH5K_DBG(ah, ATH5K_DEBUG_DMA, in ath5k_hw_stop_tx_dma()
303 AR5K_REG_DISABLE_BITS(ah, AR5K_QUEUE_MISC(queue), in ath5k_hw_stop_tx_dma()
307 ath5k_hw_reg_write(ah, 0, AR5K_QCU_TXD); in ath5k_hw_stop_tx_dma()
309 ATH5K_DBG(ah, ATH5K_DEBUG_DMA, in ath5k_hw_stop_tx_dma()
328 ath5k_hw_stop_beacon_queue(struct ath5k_hw *ah, unsigned int queue) in ath5k_hw_stop_beacon_queue() argument
331 ret = ath5k_hw_stop_tx_dma(ah, queue); in ath5k_hw_stop_beacon_queue()
333 ATH5K_DBG(ah, ATH5K_DEBUG_DMA, in ath5k_hw_stop_beacon_queue()
353 ath5k_hw_get_txdp(struct ath5k_hw *ah, unsigned int queue) in ath5k_hw_get_txdp() argument
357 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num); in ath5k_hw_get_txdp()
363 if (ah->ah_version == AR5K_AR5210) { in ath5k_hw_get_txdp()
364 switch (ah->ah_txq[queue].tqi_type) { in ath5k_hw_get_txdp()
379 return ath5k_hw_reg_read(ah, tx_reg); in ath5k_hw_get_txdp()
396 ath5k_hw_set_txdp(struct ath5k_hw *ah, unsigned int queue, u32 phys_addr) in ath5k_hw_set_txdp() argument
400 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num); in ath5k_hw_set_txdp()
406 if (ah->ah_version == AR5K_AR5210) { in ath5k_hw_set_txdp()
407 switch (ah->ah_txq[queue].tqi_type) { in ath5k_hw_set_txdp()
424 if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXE, queue)) in ath5k_hw_set_txdp()
431 ath5k_hw_reg_write(ah, phys_addr, tx_reg); in ath5k_hw_set_txdp()
453 ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, bool increase) in ath5k_hw_update_tx_triglevel() argument
461 imr = ath5k_hw_set_imr(ah, ah->ah_imr & ~AR5K_INT_GLOBAL); in ath5k_hw_update_tx_triglevel()
463 trigger_level = AR5K_REG_MS(ath5k_hw_reg_read(ah, AR5K_TXCFG), in ath5k_hw_update_tx_triglevel()
476 if (ah->ah_version == AR5K_AR5210) in ath5k_hw_update_tx_triglevel()
477 ath5k_hw_reg_write(ah, trigger_level, AR5K_TRIG_LVL); in ath5k_hw_update_tx_triglevel()
479 AR5K_REG_WRITE_BITS(ah, AR5K_TXCFG, in ath5k_hw_update_tx_triglevel()
488 ath5k_hw_set_imr(ah, imr); in ath5k_hw_update_tx_triglevel()
506 ath5k_hw_is_intr_pending(struct ath5k_hw *ah) in ath5k_hw_is_intr_pending() argument
508 return ath5k_hw_reg_read(ah, AR5K_INTPEND) == 1 ? 1 : 0; in ath5k_hw_is_intr_pending()
527 ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask) in ath5k_hw_get_isr() argument
537 if (ah->ah_version == AR5K_AR5210) { in ath5k_hw_get_isr()
539 isr = ath5k_hw_reg_read(ah, AR5K_ISR); in ath5k_hw_get_isr()
549 *interrupt_mask = (isr & AR5K_INT_COMMON) & ah->ah_imr; in ath5k_hw_get_isr()
575 pisr = ath5k_hw_reg_read(ah, AR5K_PISR); in ath5k_hw_get_isr()
581 sisr0 = ath5k_hw_reg_read(ah, AR5K_SISR0); in ath5k_hw_get_isr()
582 sisr1 = ath5k_hw_reg_read(ah, AR5K_SISR1); in ath5k_hw_get_isr()
583 sisr2 = ath5k_hw_reg_read(ah, AR5K_SISR2); in ath5k_hw_get_isr()
584 sisr3 = ath5k_hw_reg_read(ah, AR5K_SISR3); in ath5k_hw_get_isr()
585 sisr4 = ath5k_hw_reg_read(ah, AR5K_SISR4); in ath5k_hw_get_isr()
638 ath5k_hw_reg_write(ah, sisr0, AR5K_SISR0); in ath5k_hw_get_isr()
639 ath5k_hw_reg_write(ah, sisr1, AR5K_SISR1); in ath5k_hw_get_isr()
640 ath5k_hw_reg_write(ah, sisr2, AR5K_SISR2); in ath5k_hw_get_isr()
641 ath5k_hw_reg_write(ah, sisr3, AR5K_SISR3); in ath5k_hw_get_isr()
642 ath5k_hw_reg_write(ah, sisr4, AR5K_SISR4); in ath5k_hw_get_isr()
643 ath5k_hw_reg_write(ah, pisr_clear, AR5K_PISR); in ath5k_hw_get_isr()
645 ath5k_hw_reg_read(ah, AR5K_PISR); in ath5k_hw_get_isr()
651 *interrupt_mask = (pisr & AR5K_INT_COMMON) & ah->ah_imr; in ath5k_hw_get_isr()
658 ah->ah_txq_isr_txok_all |= AR5K_REG_MS(sisr0, in ath5k_hw_get_isr()
662 ah->ah_txq_isr_txok_all |= AR5K_REG_MS(sisr0, in ath5k_hw_get_isr()
666 ah->ah_txq_isr_txok_all |= AR5K_REG_MS(sisr1, in ath5k_hw_get_isr()
670 ah->ah_txq_isr_txok_all |= AR5K_REG_MS(sisr1, in ath5k_hw_get_isr()
677 ah->ah_txq_isr_txurn |= AR5K_REG_MS(sisr2, in ath5k_hw_get_isr()
714 ah->ah_txq_isr_qcborn |= AR5K_REG_MS(sisr3, in ath5k_hw_get_isr()
721 ah->ah_txq_isr_qcburn |= AR5K_REG_MS(sisr3, in ath5k_hw_get_isr()
728 ah->ah_txq_isr_qtrig |= AR5K_REG_MS(sisr4, in ath5k_hw_get_isr()
740 ATH5K_PRINTF("ISR: 0x%08x IMR: 0x%08x\n", data, ah->ah_imr); in ath5k_hw_get_isr()
755 ath5k_hw_set_imr(struct ath5k_hw *ah, enum ath5k_int new_mask) in ath5k_hw_set_imr() argument
759 old_mask = ah->ah_imr; in ath5k_hw_set_imr()
767 ath5k_hw_reg_write(ah, AR5K_IER_DISABLE, AR5K_IER); in ath5k_hw_set_imr()
768 ath5k_hw_reg_read(ah, AR5K_IER); in ath5k_hw_set_imr()
777 if (ah->ah_version != AR5K_AR5210) { in ath5k_hw_set_imr()
779 u32 simr2 = ath5k_hw_reg_read(ah, AR5K_SIMR2) in ath5k_hw_set_imr()
810 ath5k_hw_reg_write(ah, int_mask, AR5K_PIMR); in ath5k_hw_set_imr()
811 ath5k_hw_reg_write(ah, simr2, AR5K_SIMR2); in ath5k_hw_set_imr()
820 ath5k_hw_reg_write(ah, int_mask, AR5K_IMR); in ath5k_hw_set_imr()
826 ath5k_hw_reg_write(ah, 0, AR5K_RXNOFRM); in ath5k_hw_set_imr()
829 ah->ah_imr = new_mask; in ath5k_hw_set_imr()
833 ath5k_hw_reg_write(ah, AR5K_IER_ENABLE, AR5K_IER); in ath5k_hw_set_imr()
834 ath5k_hw_reg_read(ah, AR5K_IER); in ath5k_hw_set_imr()
856 ath5k_hw_dma_init(struct ath5k_hw *ah) in ath5k_hw_dma_init() argument
871 if (ah->ah_version != AR5K_AR5210) { in ath5k_hw_dma_init()
872 AR5K_REG_WRITE_BITS(ah, AR5K_TXCFG, in ath5k_hw_dma_init()
874 AR5K_REG_WRITE_BITS(ah, AR5K_RXCFG, in ath5k_hw_dma_init()
879 if (ah->ah_version != AR5K_AR5210) in ath5k_hw_dma_init()
880 ath5k_hw_set_imr(ah, ah->ah_imr); in ath5k_hw_dma_init()
896 ath5k_hw_dma_stop(struct ath5k_hw *ah) in ath5k_hw_dma_stop() argument
902 ath5k_hw_set_imr(ah, 0); in ath5k_hw_dma_stop()
905 err = ath5k_hw_stop_rx_dma(ah); in ath5k_hw_dma_stop()
911 if (ah->ah_version != AR5K_AR5210) { in ath5k_hw_dma_stop()
912 ath5k_hw_reg_write(ah, 0xffffffff, AR5K_PISR); in ath5k_hw_dma_stop()
916 ath5k_hw_reg_read(ah, AR5K_ISR); in ath5k_hw_dma_stop()
921 err = ath5k_hw_stop_tx_dma(ah, i); in ath5k_hw_dma_stop()