Lines Matching refs:ah
84 ath5k_hw_radio_revision(struct ath5k_hw *ah, enum nl80211_band band) in ath5k_hw_radio_revision() argument
95 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_2GHZ, AR5K_PHY(0)); in ath5k_hw_radio_revision()
98 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0)); in ath5k_hw_radio_revision()
107 ath5k_hw_reg_write(ah, 0x00001c16, AR5K_PHY(0x34)); in ath5k_hw_radio_revision()
110 ath5k_hw_reg_write(ah, 0x00010000, AR5K_PHY(0x20)); in ath5k_hw_radio_revision()
112 if (ah->ah_version == AR5K_AR5210) { in ath5k_hw_radio_revision()
113 srev = (ath5k_hw_reg_read(ah, AR5K_PHY(256)) >> 28) & 0xf; in ath5k_hw_radio_revision()
116 srev = (ath5k_hw_reg_read(ah, AR5K_PHY(0x100)) >> 24) & 0xff; in ath5k_hw_radio_revision()
122 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0)); in ath5k_hw_radio_revision()
136 ath5k_channel_ok(struct ath5k_hw *ah, struct ieee80211_channel *channel) in ath5k_channel_ok() argument
142 if ((freq >= ah->ah_capabilities.cap_range.range_2ghz_min) && in ath5k_channel_ok()
143 (freq <= ah->ah_capabilities.cap_range.range_2ghz_max)) in ath5k_channel_ok()
146 if ((freq >= ah->ah_capabilities.cap_range.range_5ghz_min) && in ath5k_channel_ok()
147 (freq <= ah->ah_capabilities.cap_range.range_5ghz_max)) in ath5k_channel_ok()
159 ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah, in ath5k_hw_chan_has_spur_noise() argument
164 if ((ah->ah_radio == AR5K_RF5112) || in ath5k_hw_chan_has_spur_noise()
165 (ah->ah_radio == AR5K_RF5413) || in ath5k_hw_chan_has_spur_noise()
166 (ah->ah_radio == AR5K_RF2413) || in ath5k_hw_chan_has_spur_noise()
167 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) in ath5k_hw_chan_has_spur_noise()
193 ath5k_hw_rfb_op(struct ath5k_hw *ah, const struct ath5k_rf_reg *rf_regs, in ath5k_hw_rfb_op() argument
205 rfb = ah->ah_rf_banks; in ath5k_hw_rfb_op()
207 for (i = 0; i < ah->ah_rf_regs_count; i++) { in ath5k_hw_rfb_op()
229 offset = ah->ah_offset[bank]; in ath5k_hw_rfb_op()
285 ath5k_hw_write_ofdm_timings(struct ath5k_hw *ah, in ath5k_hw_write_ofdm_timings() argument
292 BUG_ON(!(ah->ah_version == AR5K_AR5212) || in ath5k_hw_write_ofdm_timings()
299 switch (ah->ah_bwmode) { in ath5k_hw_write_ofdm_timings()
337 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3, in ath5k_hw_write_ofdm_timings()
339 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3, in ath5k_hw_write_ofdm_timings()
349 int ath5k_hw_phy_disable(struct ath5k_hw *ah) in ath5k_hw_phy_disable() argument
352 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT); in ath5k_hw_phy_disable()
363 ath5k_hw_wait_for_synth(struct ath5k_hw *ah, in ath5k_hw_wait_for_synth() argument
370 if (ah->ah_version != AR5K_AR5210) { in ath5k_hw_wait_for_synth()
372 delay = ath5k_hw_reg_read(ah, AR5K_PHY_RX_DELAY) & in ath5k_hw_wait_for_synth()
376 if (ah->ah_bwmode == AR5K_BWMODE_10MHZ) in ath5k_hw_wait_for_synth()
378 if (ah->ah_bwmode == AR5K_BWMODE_5MHZ) in ath5k_hw_wait_for_synth()
420 int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah) in ath5k_hw_rfgain_opt_init() argument
423 switch (ah->ah_radio) { in ath5k_hw_rfgain_opt_init()
425 ah->ah_gain.g_step_idx = rfgain_opt_5111.go_default; in ath5k_hw_rfgain_opt_init()
426 ah->ah_gain.g_low = 20; in ath5k_hw_rfgain_opt_init()
427 ah->ah_gain.g_high = 35; in ath5k_hw_rfgain_opt_init()
428 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; in ath5k_hw_rfgain_opt_init()
431 ah->ah_gain.g_step_idx = rfgain_opt_5112.go_default; in ath5k_hw_rfgain_opt_init()
432 ah->ah_gain.g_low = 20; in ath5k_hw_rfgain_opt_init()
433 ah->ah_gain.g_high = 85; in ath5k_hw_rfgain_opt_init()
434 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; in ath5k_hw_rfgain_opt_init()
457 ath5k_hw_request_rfgain_probe(struct ath5k_hw *ah) in ath5k_hw_request_rfgain_probe() argument
462 if (ah->ah_gain.g_state != AR5K_RFGAIN_ACTIVE) in ath5k_hw_request_rfgain_probe()
467 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txpower.txp_ofdm - 4, in ath5k_hw_request_rfgain_probe()
471 ah->ah_gain.g_state = AR5K_RFGAIN_READ_REQUESTED; in ath5k_hw_request_rfgain_probe()
483 ath5k_hw_rf_gainf_corr(struct ath5k_hw *ah) in ath5k_hw_rf_gainf_corr() argument
491 if ((ah->ah_radio != AR5K_RF5112) || in ath5k_hw_rf_gainf_corr()
492 (ah->ah_radio_5ghz_revision <= AR5K_SREV_RAD_5112A)) in ath5k_hw_rf_gainf_corr()
497 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a); in ath5k_hw_rf_gainf_corr()
499 g_step = &go->go_step[ah->ah_gain.g_step_idx]; in ath5k_hw_rf_gainf_corr()
501 if (ah->ah_rf_banks == NULL) in ath5k_hw_rf_gainf_corr()
504 ah->ah_gain.g_f_corr = 0; in ath5k_hw_rf_gainf_corr()
507 if (ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR, false) != 1) in ath5k_hw_rf_gainf_corr()
511 step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXGAIN_STEP, false); in ath5k_hw_rf_gainf_corr()
518 ah->ah_gain.g_f_corr = step * 2; in ath5k_hw_rf_gainf_corr()
521 ah->ah_gain.g_f_corr = (step - 5) * 2; in ath5k_hw_rf_gainf_corr()
524 ah->ah_gain.g_f_corr = step; in ath5k_hw_rf_gainf_corr()
527 ah->ah_gain.g_f_corr = 0; in ath5k_hw_rf_gainf_corr()
531 return ah->ah_gain.g_f_corr; in ath5k_hw_rf_gainf_corr()
546 ath5k_hw_rf_check_gainf_readback(struct ath5k_hw *ah) in ath5k_hw_rf_check_gainf_readback() argument
551 if (ah->ah_rf_banks == NULL) in ath5k_hw_rf_check_gainf_readback()
554 if (ah->ah_radio == AR5K_RF5111) { in ath5k_hw_rf_check_gainf_readback()
557 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111); in ath5k_hw_rf_check_gainf_readback()
559 step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_RFGAIN_STEP, in ath5k_hw_rf_check_gainf_readback()
567 ah->ah_gain.g_high = level[3] - in ath5k_hw_rf_check_gainf_readback()
569 ah->ah_gain.g_low = level[0] + in ath5k_hw_rf_check_gainf_readback()
574 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112); in ath5k_hw_rf_check_gainf_readback()
576 mix_ovr = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR, in ath5k_hw_rf_check_gainf_readback()
585 ah->ah_gain.g_high = 55; in ath5k_hw_rf_check_gainf_readback()
589 return (ah->ah_gain.g_current >= level[0] && in ath5k_hw_rf_check_gainf_readback()
590 ah->ah_gain.g_current <= level[1]) || in ath5k_hw_rf_check_gainf_readback()
591 (ah->ah_gain.g_current >= level[2] && in ath5k_hw_rf_check_gainf_readback()
592 ah->ah_gain.g_current <= level[3]); in ath5k_hw_rf_check_gainf_readback()
603 ath5k_hw_rf_gainf_adjust(struct ath5k_hw *ah) in ath5k_hw_rf_gainf_adjust() argument
609 switch (ah->ah_radio) { in ath5k_hw_rf_gainf_adjust()
620 g_step = &go->go_step[ah->ah_gain.g_step_idx]; in ath5k_hw_rf_gainf_adjust()
622 if (ah->ah_gain.g_current >= ah->ah_gain.g_high) { in ath5k_hw_rf_gainf_adjust()
625 if (ah->ah_gain.g_step_idx == 0) in ath5k_hw_rf_gainf_adjust()
628 for (ah->ah_gain.g_target = ah->ah_gain.g_current; in ath5k_hw_rf_gainf_adjust()
629 ah->ah_gain.g_target >= ah->ah_gain.g_high && in ath5k_hw_rf_gainf_adjust()
630 ah->ah_gain.g_step_idx > 0; in ath5k_hw_rf_gainf_adjust()
631 g_step = &go->go_step[ah->ah_gain.g_step_idx]) in ath5k_hw_rf_gainf_adjust()
632 ah->ah_gain.g_target -= 2 * in ath5k_hw_rf_gainf_adjust()
633 (go->go_step[--(ah->ah_gain.g_step_idx)].gos_gain - in ath5k_hw_rf_gainf_adjust()
640 if (ah->ah_gain.g_current <= ah->ah_gain.g_low) { in ath5k_hw_rf_gainf_adjust()
643 if (ah->ah_gain.g_step_idx == (go->go_steps_count - 1)) in ath5k_hw_rf_gainf_adjust()
646 for (ah->ah_gain.g_target = ah->ah_gain.g_current; in ath5k_hw_rf_gainf_adjust()
647 ah->ah_gain.g_target <= ah->ah_gain.g_low && in ath5k_hw_rf_gainf_adjust()
648 ah->ah_gain.g_step_idx < go->go_steps_count - 1; in ath5k_hw_rf_gainf_adjust()
649 g_step = &go->go_step[ah->ah_gain.g_step_idx]) in ath5k_hw_rf_gainf_adjust()
650 ah->ah_gain.g_target -= 2 * in ath5k_hw_rf_gainf_adjust()
651 (go->go_step[++ah->ah_gain.g_step_idx].gos_gain - in ath5k_hw_rf_gainf_adjust()
659 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, in ath5k_hw_rf_gainf_adjust()
661 ret, ah->ah_gain.g_step_idx, ah->ah_gain.g_current, in ath5k_hw_rf_gainf_adjust()
662 ah->ah_gain.g_target); in ath5k_hw_rf_gainf_adjust()
678 ath5k_hw_gainf_calibrate(struct ath5k_hw *ah) in ath5k_hw_gainf_calibrate() argument
681 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; in ath5k_hw_gainf_calibrate()
683 if (ah->ah_rf_banks == NULL || in ath5k_hw_gainf_calibrate()
684 ah->ah_gain.g_state == AR5K_RFGAIN_INACTIVE) in ath5k_hw_gainf_calibrate()
689 if (ah->ah_gain.g_state != AR5K_RFGAIN_READ_REQUESTED) in ath5k_hw_gainf_calibrate()
694 data = ath5k_hw_reg_read(ah, AR5K_PHY_PAPD_PROBE); in ath5k_hw_gainf_calibrate()
698 ah->ah_gain.g_current = data >> AR5K_PHY_PAPD_PROBE_GAINF_S; in ath5k_hw_gainf_calibrate()
704 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) in ath5k_hw_gainf_calibrate()
705 ah->ah_gain.g_current += in ath5k_hw_gainf_calibrate()
708 ah->ah_gain.g_current += in ath5k_hw_gainf_calibrate()
714 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) { in ath5k_hw_gainf_calibrate()
715 ath5k_hw_rf_gainf_corr(ah); in ath5k_hw_gainf_calibrate()
716 ah->ah_gain.g_current = in ath5k_hw_gainf_calibrate()
717 ah->ah_gain.g_current >= ah->ah_gain.g_f_corr ? in ath5k_hw_gainf_calibrate()
718 (ah->ah_gain.g_current - ah->ah_gain.g_f_corr) : in ath5k_hw_gainf_calibrate()
725 if (ath5k_hw_rf_check_gainf_readback(ah) && in ath5k_hw_gainf_calibrate()
726 AR5K_GAIN_CHECK_ADJUST(&ah->ah_gain) && in ath5k_hw_gainf_calibrate()
727 ath5k_hw_rf_gainf_adjust(ah)) { in ath5k_hw_gainf_calibrate()
728 ah->ah_gain.g_state = AR5K_RFGAIN_NEED_CHANGE; in ath5k_hw_gainf_calibrate()
730 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; in ath5k_hw_gainf_calibrate()
735 return ah->ah_gain.g_state; in ath5k_hw_gainf_calibrate()
749 ath5k_hw_rfgain_init(struct ath5k_hw *ah, enum nl80211_band band) in ath5k_hw_rfgain_init() argument
754 switch (ah->ah_radio) { in ath5k_hw_rfgain_init()
788 ath5k_hw_reg_write(ah, ath5k_rfg[i].rfg_value[index], in ath5k_hw_rfgain_init()
810 ath5k_hw_rfregs_init(struct ath5k_hw *ah, in ath5k_hw_rfregs_init() argument
818 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; in ath5k_hw_rfregs_init()
823 switch (ah->ah_radio) { in ath5k_hw_rfregs_init()
826 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111); in ath5k_hw_rfregs_init()
828 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5111); in ath5k_hw_rfregs_init()
832 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) { in ath5k_hw_rfregs_init()
834 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a); in ath5k_hw_rfregs_init()
836 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112a); in ath5k_hw_rfregs_init()
839 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112); in ath5k_hw_rfregs_init()
841 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112); in ath5k_hw_rfregs_init()
847 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2413); in ath5k_hw_rfregs_init()
849 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2413); in ath5k_hw_rfregs_init()
853 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2316); in ath5k_hw_rfregs_init()
855 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2316); in ath5k_hw_rfregs_init()
859 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5413); in ath5k_hw_rfregs_init()
861 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5413); in ath5k_hw_rfregs_init()
865 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425); in ath5k_hw_rfregs_init()
867 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2317); in ath5k_hw_rfregs_init()
871 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425); in ath5k_hw_rfregs_init()
872 if (ah->ah_mac_srev < AR5K_SREV_AR2417) { in ath5k_hw_rfregs_init()
874 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2425); in ath5k_hw_rfregs_init()
877 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2417); in ath5k_hw_rfregs_init()
887 if (ah->ah_rf_banks == NULL) { in ath5k_hw_rfregs_init()
888 ah->ah_rf_banks = kmalloc_array(ah->ah_rf_banks_size, in ath5k_hw_rfregs_init()
891 if (ah->ah_rf_banks == NULL) { in ath5k_hw_rfregs_init()
892 ATH5K_ERR(ah, "out of memory\n"); in ath5k_hw_rfregs_init()
898 rfb = ah->ah_rf_banks; in ath5k_hw_rfregs_init()
900 for (i = 0; i < ah->ah_rf_banks_size; i++) { in ath5k_hw_rfregs_init()
902 ATH5K_ERR(ah, "invalid bank\n"); in ath5k_hw_rfregs_init()
909 ah->ah_offset[bank] = i; in ath5k_hw_rfregs_init()
930 if ((ah->ah_radio == AR5K_RF5111) || in ath5k_hw_rfregs_init()
931 (ah->ah_radio == AR5K_RF5112)) in ath5k_hw_rfregs_init()
936 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb], in ath5k_hw_rfregs_init()
939 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb], in ath5k_hw_rfregs_init()
944 (ah->ah_radio == AR5K_RF5111)) { in ath5k_hw_rfregs_init()
957 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb], in ath5k_hw_rfregs_init()
960 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb], in ath5k_hw_rfregs_init()
964 g_step = &go->go_step[ah->ah_gain.g_step_idx]; in ath5k_hw_rfregs_init()
967 if ((ah->ah_bwmode == AR5K_BWMODE_40MHZ) && in ath5k_hw_rfregs_init()
968 (ah->ah_radio != AR5K_RF5413)) in ath5k_hw_rfregs_init()
969 ath5k_hw_rfb_op(ah, rf_regs, 1, AR5K_RF_TURBO, false); in ath5k_hw_rfregs_init()
972 if (ah->ah_radio == AR5K_RF5111) { in ath5k_hw_rfregs_init()
977 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_FRAME_CTL, in ath5k_hw_rfregs_init()
981 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1], in ath5k_hw_rfregs_init()
984 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2], in ath5k_hw_rfregs_init()
987 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3], in ath5k_hw_rfregs_init()
992 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; in ath5k_hw_rfregs_init()
998 ath5k_hw_rfb_op(ah, rf_regs, !ee->ee_xpd[ee_mode], in ath5k_hw_rfregs_init()
1001 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_x_gain[ee_mode], in ath5k_hw_rfregs_init()
1004 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode], in ath5k_hw_rfregs_init()
1007 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode], in ath5k_hw_rfregs_init()
1011 if (ah->ah_bwmode == AR5K_BWMODE_5MHZ || in ath5k_hw_rfregs_init()
1012 ah->ah_bwmode == AR5K_BWMODE_10MHZ) { in ath5k_hw_rfregs_init()
1015 ath5k_hw_rfb_op(ah, rf_regs, 0x1f, in ath5k_hw_rfregs_init()
1018 wait_i = (ah->ah_bwmode == AR5K_BWMODE_5MHZ) ? in ath5k_hw_rfregs_init()
1021 ath5k_hw_rfb_op(ah, rf_regs, wait_i, in ath5k_hw_rfregs_init()
1023 ath5k_hw_rfb_op(ah, rf_regs, 3, in ath5k_hw_rfregs_init()
1029 if (ah->ah_radio == AR5K_RF5112) { in ath5k_hw_rfregs_init()
1034 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[0], in ath5k_hw_rfregs_init()
1037 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1], in ath5k_hw_rfregs_init()
1040 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2], in ath5k_hw_rfregs_init()
1043 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3], in ath5k_hw_rfregs_init()
1046 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[4], in ath5k_hw_rfregs_init()
1049 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[5], in ath5k_hw_rfregs_init()
1052 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[6], in ath5k_hw_rfregs_init()
1057 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; in ath5k_hw_rfregs_init()
1062 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode], in ath5k_hw_rfregs_init()
1065 if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112A) { in ath5k_hw_rfregs_init()
1067 ath5k_hw_rfb_op(ah, rf_regs, in ath5k_hw_rfregs_init()
1074 ath5k_hw_rfb_op(ah, rf_regs, in ath5k_hw_rfregs_init()
1077 ath5k_hw_rfb_op(ah, rf_regs, in ath5k_hw_rfregs_init()
1081 ath5k_hw_rfb_op(ah, rf_regs, in ath5k_hw_rfregs_init()
1084 ath5k_hw_rfb_op(ah, rf_regs, in ath5k_hw_rfregs_init()
1090 if (ah->ah_radio == AR5K_RF5112 && in ath5k_hw_rfregs_init()
1091 (ah->ah_radio_5ghz_revision & AR5K_SREV_REV) > 0) { in ath5k_hw_rfregs_init()
1092 ath5k_hw_rfb_op(ah, rf_regs, 2, in ath5k_hw_rfregs_init()
1095 ath5k_hw_rfb_op(ah, rf_regs, 2, in ath5k_hw_rfregs_init()
1098 ath5k_hw_rfb_op(ah, rf_regs, 2, in ath5k_hw_rfregs_init()
1101 ath5k_hw_rfb_op(ah, rf_regs, 2, in ath5k_hw_rfregs_init()
1106 if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) { in ath5k_hw_rfregs_init()
1107 ath5k_hw_rfb_op(ah, rf_regs, 1, in ath5k_hw_rfregs_init()
1110 ath5k_hw_rfb_op(ah, rf_regs, 1, in ath5k_hw_rfregs_init()
1113 ath5k_hw_rfb_op(ah, rf_regs, 1, in ath5k_hw_rfregs_init()
1116 ath5k_hw_rfb_op(ah, rf_regs, 1, in ath5k_hw_rfregs_init()
1119 ath5k_hw_rfb_op(ah, rf_regs, 1, in ath5k_hw_rfregs_init()
1124 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode], in ath5k_hw_rfregs_init()
1128 if (ah->ah_bwmode == AR5K_BWMODE_5MHZ || in ath5k_hw_rfregs_init()
1129 ah->ah_bwmode == AR5K_BWMODE_10MHZ) { in ath5k_hw_rfregs_init()
1132 pd_delay = (ah->ah_bwmode == AR5K_BWMODE_5MHZ) ? in ath5k_hw_rfregs_init()
1135 ath5k_hw_rfb_op(ah, rf_regs, pd_delay, in ath5k_hw_rfregs_init()
1137 ath5k_hw_rfb_op(ah, rf_regs, 0xf, in ath5k_hw_rfregs_init()
1143 if (ah->ah_radio == AR5K_RF5413 && in ath5k_hw_rfregs_init()
1146 ath5k_hw_rfb_op(ah, rf_regs, 1, AR5K_RF_DERBY_CHAN_SEL_MODE, in ath5k_hw_rfregs_init()
1150 if (ah->ah_mac_srev >= AR5K_SREV_AR5424 && in ath5k_hw_rfregs_init()
1151 ah->ah_mac_srev < AR5K_SREV_AR5413) in ath5k_hw_rfregs_init()
1152 ath5k_hw_rfb_op(ah, rf_regs, ath5k_hw_bitswap(6, 3), in ath5k_hw_rfregs_init()
1158 for (i = 0; i < ah->ah_rf_banks_size; i++) { in ath5k_hw_rfregs_init()
1160 ath5k_hw_reg_write(ah, rfb[i], ini_rfb[i].rfb_ctrl_register); in ath5k_hw_rfregs_init()
1196 ath5k_hw_rf5110_channel(struct ath5k_hw *ah, in ath5k_hw_rf5110_channel() argument
1205 ath5k_hw_reg_write(ah, data, AR5K_RF_BUFFER); in ath5k_hw_rf5110_channel()
1206 ath5k_hw_reg_write(ah, 0, AR5K_RF_BUFFER_CONTROL_0); in ath5k_hw_rf5110_channel()
1255 ath5k_hw_rf5111_channel(struct ath5k_hw *ah, in ath5k_hw_rf5111_channel() argument
1292 ath5k_hw_reg_write(ah, (data1 & 0xff) | ((data0 & 0xff) << 8), in ath5k_hw_rf5111_channel()
1294 ath5k_hw_reg_write(ah, ((data1 >> 8) & 0xff) | (data0 & 0xff00), in ath5k_hw_rf5111_channel()
1313 ath5k_hw_rf5112_channel(struct ath5k_hw *ah, in ath5k_hw_rf5112_channel() argument
1372 ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER); in ath5k_hw_rf5112_channel()
1373 ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5); in ath5k_hw_rf5112_channel()
1387 ath5k_hw_rf2425_channel(struct ath5k_hw *ah, in ath5k_hw_rf2425_channel() argument
1417 ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER); in ath5k_hw_rf2425_channel()
1418 ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5); in ath5k_hw_rf2425_channel()
1432 ath5k_hw_channel(struct ath5k_hw *ah, in ath5k_hw_channel() argument
1440 if (!ath5k_channel_ok(ah, channel)) { in ath5k_hw_channel()
1441 ATH5K_ERR(ah, in ath5k_hw_channel()
1451 switch (ah->ah_radio) { in ath5k_hw_channel()
1453 ret = ath5k_hw_rf5110_channel(ah, channel); in ath5k_hw_channel()
1456 ret = ath5k_hw_rf5111_channel(ah, channel); in ath5k_hw_channel()
1460 ret = ath5k_hw_rf2425_channel(ah, channel); in ath5k_hw_channel()
1463 ret = ath5k_hw_rf5112_channel(ah, channel); in ath5k_hw_channel()
1472 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL, in ath5k_hw_channel()
1475 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL, in ath5k_hw_channel()
1479 ah->ah_current_channel = channel; in ath5k_hw_channel()
1523 ath5k_hw_read_measured_noise_floor(struct ath5k_hw *ah) in ath5k_hw_read_measured_noise_floor() argument
1527 val = ath5k_hw_reg_read(ah, AR5K_PHY_NF); in ath5k_hw_read_measured_noise_floor()
1536 ath5k_hw_init_nfcal_hist(struct ath5k_hw *ah) in ath5k_hw_init_nfcal_hist() argument
1540 ah->ah_nfcal_hist.index = 0; in ath5k_hw_init_nfcal_hist()
1542 ah->ah_nfcal_hist.nfval[i] = AR5K_TUNE_CCA_MAX_GOOD_VALUE; in ath5k_hw_init_nfcal_hist()
1550 static void ath5k_hw_update_nfcal_hist(struct ath5k_hw *ah, s16 noise_floor) in ath5k_hw_update_nfcal_hist() argument
1552 struct ath5k_nfcal_hist *hist = &ah->ah_nfcal_hist; in ath5k_hw_update_nfcal_hist()
1562 ath5k_hw_get_median_noise_floor(struct ath5k_hw *ah) in ath5k_hw_get_median_noise_floor() argument
1568 memcpy(sort, ah->ah_nfcal_hist.nfval, sizeof(sort)); in ath5k_hw_get_median_noise_floor()
1579 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, in ath5k_hw_get_median_noise_floor()
1594 ath5k_hw_update_noise_floor(struct ath5k_hw *ah) in ath5k_hw_update_noise_floor() argument
1596 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; in ath5k_hw_update_noise_floor()
1602 if (ath5k_hw_reg_read(ah, AR5K_PHY_AGCCTL) & AR5K_PHY_AGCCTL_NF) { in ath5k_hw_update_noise_floor()
1603 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, in ath5k_hw_update_noise_floor()
1609 ah->ah_cal_mask |= AR5K_CALIBRATION_NF; in ath5k_hw_update_noise_floor()
1611 ee_mode = ath5k_eeprom_mode_from_channel(ah, ah->ah_current_channel); in ath5k_hw_update_noise_floor()
1614 nf = ath5k_hw_read_measured_noise_floor(ah); in ath5k_hw_update_noise_floor()
1618 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, in ath5k_hw_update_noise_floor()
1626 ath5k_hw_update_nfcal_hist(ah, nf); in ath5k_hw_update_noise_floor()
1627 nf = ath5k_hw_get_median_noise_floor(ah); in ath5k_hw_update_noise_floor()
1630 val = ath5k_hw_reg_read(ah, AR5K_PHY_NF) & ~AR5K_PHY_NF_M; in ath5k_hw_update_noise_floor()
1632 ath5k_hw_reg_write(ah, val, AR5K_PHY_NF); in ath5k_hw_update_noise_floor()
1634 AR5K_REG_MASKED_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF, in ath5k_hw_update_noise_floor()
1637 ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF, in ath5k_hw_update_noise_floor()
1647 ath5k_hw_reg_write(ah, val, AR5K_PHY_NF); in ath5k_hw_update_noise_floor()
1648 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, in ath5k_hw_update_noise_floor()
1653 ah->ah_noise_floor = nf; in ath5k_hw_update_noise_floor()
1655 ah->ah_cal_mask &= ~AR5K_CALIBRATION_NF; in ath5k_hw_update_noise_floor()
1657 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, in ath5k_hw_update_noise_floor()
1669 ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah, in ath5k_hw_rf5110_calibrate() argument
1675 if (!(ah->ah_cal_mask & AR5K_CALIBRATION_FULL)) in ath5k_hw_rf5110_calibrate()
1681 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5210, in ath5k_hw_rf5110_calibrate()
1683 beacon = ath5k_hw_reg_read(ah, AR5K_BEACON_5210); in ath5k_hw_rf5110_calibrate()
1684 ath5k_hw_reg_write(ah, beacon & ~AR5K_BEACON_ENABLE, AR5K_BEACON_5210); in ath5k_hw_rf5110_calibrate()
1691 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); in ath5k_hw_rf5110_calibrate()
1693 ret = ath5k_hw_channel(ah, channel); in ath5k_hw_rf5110_calibrate()
1698 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT); in ath5k_hw_rf5110_calibrate()
1701 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); in ath5k_hw_rf5110_calibrate()
1711 phy_sig = ath5k_hw_reg_read(ah, AR5K_PHY_SIG); in ath5k_hw_rf5110_calibrate()
1712 phy_agc = ath5k_hw_reg_read(ah, AR5K_PHY_AGCCOARSE); in ath5k_hw_rf5110_calibrate()
1713 phy_sat = ath5k_hw_reg_read(ah, AR5K_PHY_ADCSAT); in ath5k_hw_rf5110_calibrate()
1716 ath5k_hw_reg_write(ah, (phy_sig & ~(AR5K_PHY_SIG_FIRPWR)) | in ath5k_hw_rf5110_calibrate()
1719 ath5k_hw_reg_write(ah, (phy_agc & ~(AR5K_PHY_AGCCOARSE_HI | in ath5k_hw_rf5110_calibrate()
1724 ath5k_hw_reg_write(ah, (phy_sat & ~(AR5K_PHY_ADCSAT_ICNT | in ath5k_hw_rf5110_calibrate()
1731 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); in ath5k_hw_rf5110_calibrate()
1733 ath5k_hw_reg_write(ah, AR5K_PHY_RFSTG_DISABLE, AR5K_PHY_RFSTG); in ath5k_hw_rf5110_calibrate()
1734 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); in ath5k_hw_rf5110_calibrate()
1741 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_CAL); in ath5k_hw_rf5110_calibrate()
1743 ret = ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, in ath5k_hw_rf5110_calibrate()
1747 ath5k_hw_reg_write(ah, phy_sig, AR5K_PHY_SIG); in ath5k_hw_rf5110_calibrate()
1748 ath5k_hw_reg_write(ah, phy_agc, AR5K_PHY_AGCCOARSE); in ath5k_hw_rf5110_calibrate()
1749 ath5k_hw_reg_write(ah, phy_sat, AR5K_PHY_ADCSAT); in ath5k_hw_rf5110_calibrate()
1752 ATH5K_ERR(ah, "calibration timeout (%uMHz)\n", in ath5k_hw_rf5110_calibrate()
1760 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW_5210, in ath5k_hw_rf5110_calibrate()
1762 ath5k_hw_reg_write(ah, beacon, AR5K_BEACON_5210); in ath5k_hw_rf5110_calibrate()
1772 ath5k_hw_rf511x_iq_calibrate(struct ath5k_hw *ah) in ath5k_hw_rf511x_iq_calibrate() argument
1779 if (!ah->ah_iq_cal_needed) in ath5k_hw_rf511x_iq_calibrate()
1781 else if (ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN) { in ath5k_hw_rf511x_iq_calibrate()
1782 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_CALIBRATE, in ath5k_hw_rf511x_iq_calibrate()
1792 iq_corr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_CORR); in ath5k_hw_rf511x_iq_calibrate()
1793 i_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_I); in ath5k_hw_rf511x_iq_calibrate()
1794 q_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_Q); in ath5k_hw_rf511x_iq_calibrate()
1795 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_CALIBRATE, in ath5k_hw_rf511x_iq_calibrate()
1803 if (ah->ah_version == AR5K_AR5211) in ath5k_hw_rf511x_iq_calibrate()
1819 if (ah->ah_version == AR5K_AR5211) in ath5k_hw_rf511x_iq_calibrate()
1825 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_CALIBRATE, in ath5k_hw_rf511x_iq_calibrate()
1830 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_I_COFF, i_coff); in ath5k_hw_rf511x_iq_calibrate()
1831 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_Q_COFF, q_coff); in ath5k_hw_rf511x_iq_calibrate()
1832 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE); in ath5k_hw_rf511x_iq_calibrate()
1836 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, in ath5k_hw_rf511x_iq_calibrate()
1838 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_RUN); in ath5k_hw_rf511x_iq_calibrate()
1853 ath5k_hw_phy_calibrate(struct ath5k_hw *ah, in ath5k_hw_phy_calibrate() argument
1858 if (ah->ah_radio == AR5K_RF5110) in ath5k_hw_phy_calibrate()
1859 return ath5k_hw_rf5110_calibrate(ah, channel); in ath5k_hw_phy_calibrate()
1861 ret = ath5k_hw_rf511x_iq_calibrate(ah); in ath5k_hw_phy_calibrate()
1863 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_CALIBRATE, in ath5k_hw_phy_calibrate()
1874 if ((ah->ah_cal_mask & AR5K_CALIBRATION_FULL) && in ath5k_hw_phy_calibrate()
1875 (ah->ah_radio == AR5K_RF5111 || in ath5k_hw_phy_calibrate()
1876 ah->ah_radio == AR5K_RF5112) && in ath5k_hw_phy_calibrate()
1878 ath5k_hw_request_rfgain_probe(ah); in ath5k_hw_phy_calibrate()
1881 if (!(ah->ah_cal_mask & AR5K_CALIBRATION_NF)) in ath5k_hw_phy_calibrate()
1882 ath5k_hw_update_noise_floor(ah); in ath5k_hw_phy_calibrate()
1903 ath5k_hw_set_spur_mitigation_filter(struct ath5k_hw *ah, in ath5k_hw_set_spur_mitigation_filter() argument
1906 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; in ath5k_hw_set_spur_mitigation_filter()
1931 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ) in ath5k_hw_set_spur_mitigation_filter()
1962 switch (ah->ah_bwmode) { in ath5k_hw_set_spur_mitigation_filter()
2056 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL, in ath5k_hw_set_spur_mitigation_filter()
2059 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, in ath5k_hw_set_spur_mitigation_filter()
2065 ath5k_hw_reg_write(ah, in ath5k_hw_set_spur_mitigation_filter()
2074 ath5k_hw_reg_write(ah, pilot_mask[0], AR5K_PHY_TIMING_7); in ath5k_hw_set_spur_mitigation_filter()
2075 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_8, in ath5k_hw_set_spur_mitigation_filter()
2079 ath5k_hw_reg_write(ah, pilot_mask[0], AR5K_PHY_TIMING_9); in ath5k_hw_set_spur_mitigation_filter()
2080 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_10, in ath5k_hw_set_spur_mitigation_filter()
2085 ath5k_hw_reg_write(ah, mag_mask[0], AR5K_PHY_BIN_MASK_1); in ath5k_hw_set_spur_mitigation_filter()
2086 ath5k_hw_reg_write(ah, mag_mask[1], AR5K_PHY_BIN_MASK_2); in ath5k_hw_set_spur_mitigation_filter()
2087 ath5k_hw_reg_write(ah, mag_mask[2], AR5K_PHY_BIN_MASK_3); in ath5k_hw_set_spur_mitigation_filter()
2088 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL, in ath5k_hw_set_spur_mitigation_filter()
2092 ath5k_hw_reg_write(ah, mag_mask[0], AR5K_PHY_BIN_MASK2_1); in ath5k_hw_set_spur_mitigation_filter()
2093 ath5k_hw_reg_write(ah, mag_mask[1], AR5K_PHY_BIN_MASK2_2); in ath5k_hw_set_spur_mitigation_filter()
2094 ath5k_hw_reg_write(ah, mag_mask[2], AR5K_PHY_BIN_MASK2_3); in ath5k_hw_set_spur_mitigation_filter()
2095 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK2_4, in ath5k_hw_set_spur_mitigation_filter()
2099 } else if (ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & in ath5k_hw_set_spur_mitigation_filter()
2102 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL, in ath5k_hw_set_spur_mitigation_filter()
2104 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_IQ, in ath5k_hw_set_spur_mitigation_filter()
2108 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_11); in ath5k_hw_set_spur_mitigation_filter()
2111 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_7); in ath5k_hw_set_spur_mitigation_filter()
2112 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_8, in ath5k_hw_set_spur_mitigation_filter()
2116 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_9); in ath5k_hw_set_spur_mitigation_filter()
2117 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_10, in ath5k_hw_set_spur_mitigation_filter()
2122 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_1); in ath5k_hw_set_spur_mitigation_filter()
2123 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_2); in ath5k_hw_set_spur_mitigation_filter()
2124 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_3); in ath5k_hw_set_spur_mitigation_filter()
2125 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL, in ath5k_hw_set_spur_mitigation_filter()
2129 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_1); in ath5k_hw_set_spur_mitigation_filter()
2130 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_2); in ath5k_hw_set_spur_mitigation_filter()
2131 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_3); in ath5k_hw_set_spur_mitigation_filter()
2132 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK2_4, in ath5k_hw_set_spur_mitigation_filter()
2199 ath5k_hw_set_def_antenna(struct ath5k_hw *ah, u8 ant) in ath5k_hw_set_def_antenna() argument
2201 if (ah->ah_version != AR5K_AR5210) in ath5k_hw_set_def_antenna()
2202 ath5k_hw_reg_write(ah, ant & 0x7, AR5K_DEFAULT_ANTENNA); in ath5k_hw_set_def_antenna()
2212 ath5k_hw_set_fast_div(struct ath5k_hw *ah, u8 ee_mode, bool enable) in ath5k_hw_set_fast_div() argument
2220 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGCCTL, in ath5k_hw_set_fast_div()
2223 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, in ath5k_hw_set_fast_div()
2227 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, in ath5k_hw_set_fast_div()
2235 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART, in ath5k_hw_set_fast_div()
2238 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV, in ath5k_hw_set_fast_div()
2241 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART, in ath5k_hw_set_fast_div()
2244 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV, in ath5k_hw_set_fast_div()
2258 ath5k_hw_set_antenna_switch(struct ath5k_hw *ah, u8 ee_mode) in ath5k_hw_set_antenna_switch() argument
2266 if (ah->ah_ant_mode == AR5K_ANTMODE_FIXED_A) in ath5k_hw_set_antenna_switch()
2268 else if (ah->ah_ant_mode == AR5K_ANTMODE_FIXED_B) in ath5k_hw_set_antenna_switch()
2276 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_ANT_CTL, in ath5k_hw_set_antenna_switch()
2278 (ah->ah_ant_ctl[ee_mode][AR5K_ANT_CTL] | in ath5k_hw_set_antenna_switch()
2282 ath5k_hw_reg_write(ah, ah->ah_ant_ctl[ee_mode][ant0], in ath5k_hw_set_antenna_switch()
2284 ath5k_hw_reg_write(ah, ah->ah_ant_ctl[ee_mode][ant1], in ath5k_hw_set_antenna_switch()
2294 ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode) in ath5k_hw_set_antenna_mode() argument
2296 struct ieee80211_channel *channel = ah->ah_current_channel; in ath5k_hw_set_antenna_mode()
2306 ah->ah_ant_mode = ant_mode; in ath5k_hw_set_antenna_mode()
2310 def_ant = ah->ah_def_ant; in ath5k_hw_set_antenna_mode()
2312 ee_mode = ath5k_eeprom_mode_from_channel(ah, channel); in ath5k_hw_set_antenna_mode()
2379 ah->ah_tx_ant = tx_ant; in ath5k_hw_set_antenna_mode()
2380 ah->ah_ant_mode = ant_mode; in ath5k_hw_set_antenna_mode()
2381 ah->ah_def_ant = def_ant; in ath5k_hw_set_antenna_mode()
2388 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_ANTENNA_SETTINGS); in ath5k_hw_set_antenna_mode()
2391 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, sta_id1); in ath5k_hw_set_antenna_mode()
2393 ath5k_hw_set_antenna_switch(ah, ee_mode); in ath5k_hw_set_antenna_mode()
2396 ath5k_hw_set_fast_div(ah, ee_mode, fast_div); in ath5k_hw_set_antenna_mode()
2397 ath5k_hw_set_def_antenna(ah, def_ant); in ath5k_hw_set_antenna_mode()
2580 ath5k_get_chan_pcal_surrounding_piers(struct ath5k_hw *ah, in ath5k_get_chan_pcal_surrounding_piers() argument
2585 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; in ath5k_get_chan_pcal_surrounding_piers()
2669 ath5k_get_rate_pcal_data(struct ath5k_hw *ah, in ath5k_get_rate_pcal_data() argument
2673 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; in ath5k_get_rate_pcal_data()
2764 ath5k_get_max_ctl_power(struct ath5k_hw *ah, in ath5k_get_max_ctl_power() argument
2767 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah); in ath5k_get_max_ctl_power()
2768 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; in ath5k_get_max_ctl_power()
2771 s16 max_chan_pwr = ah->ah_txpower.txp_max_pwr / 4; in ath5k_get_max_ctl_power()
2782 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ) in ath5k_get_max_ctl_power()
2788 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ) in ath5k_get_max_ctl_power()
2830 ah->ah_txpower.txp_max_pwr = 4 * min(edge_pwr, max_chan_pwr); in ath5k_get_max_ctl_power()
2877 ath5k_fill_pwr_to_pcdac_table(struct ath5k_hw *ah, s16* table_min, in ath5k_fill_pwr_to_pcdac_table() argument
2880 u8 *pcdac_out = ah->ah_txpower.txp_pd_table; in ath5k_fill_pwr_to_pcdac_table()
2881 u8 *pcdac_tmp = ah->ah_txpower.tmpL[0]; in ath5k_fill_pwr_to_pcdac_table()
2927 ath5k_combine_linear_pcdac_curves(struct ath5k_hw *ah, s16* table_min, in ath5k_combine_linear_pcdac_curves() argument
2930 u8 *pcdac_out = ah->ah_txpower.txp_pd_table; in ath5k_combine_linear_pcdac_curves()
2952 pcdac_low_pwr = ah->ah_txpower.tmpL[1]; in ath5k_combine_linear_pcdac_curves()
2953 pcdac_high_pwr = ah->ah_txpower.tmpL[0]; in ath5k_combine_linear_pcdac_curves()
2971 pcdac_low_pwr = ah->ah_txpower.tmpL[1]; /* Zeroed */ in ath5k_combine_linear_pcdac_curves()
2972 pcdac_high_pwr = ah->ah_txpower.tmpL[0]; in ath5k_combine_linear_pcdac_curves()
2980 ah->ah_txpower.txp_min_idx = min_pwr_idx / 2; in ath5k_combine_linear_pcdac_curves()
3025 ath5k_write_pcdac_table(struct ath5k_hw *ah) in ath5k_write_pcdac_table() argument
3027 u8 *pcdac_out = ah->ah_txpower.txp_pd_table; in ath5k_write_pcdac_table()
3034 ath5k_hw_reg_write(ah, in ath5k_write_pcdac_table()
3077 ath5k_combine_pwr_to_pdadc_curves(struct ath5k_hw *ah, in ath5k_combine_pwr_to_pdadc_curves() argument
3081 u8 *pdadc_out = ah->ah_txpower.txp_pd_table; in ath5k_combine_pwr_to_pdadc_curves()
3090 pd_gain_overlap = (u8) ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG5) & in ath5k_combine_pwr_to_pdadc_curves()
3095 pdadc_tmp = ah->ah_txpower.tmpL[pdg]; in ath5k_combine_pwr_to_pdadc_curves()
3177 ath5k_hw_reg_write(ah, in ath5k_combine_pwr_to_pdadc_curves()
3191 ah->ah_txpower.txp_min_idx = pwr_min[0]; in ath5k_combine_pwr_to_pdadc_curves()
3201 ath5k_write_pwr_to_pdadc_table(struct ath5k_hw *ah, u8 ee_mode) in ath5k_write_pwr_to_pdadc_table() argument
3203 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; in ath5k_write_pwr_to_pdadc_table()
3204 u8 *pdadc_out = ah->ah_txpower.txp_pd_table; in ath5k_write_pwr_to_pdadc_table()
3213 reg = ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG1); in ath5k_write_pwr_to_pdadc_table()
3240 ath5k_hw_reg_write(ah, reg, AR5K_PHY_TPC_RG1); in ath5k_write_pwr_to_pdadc_table()
3247 ath5k_hw_reg_write(ah, val, AR5K_PHY_PDADC_TXPOWER(i)); in ath5k_write_pwr_to_pdadc_table()
3270 ath5k_setup_channel_powertable(struct ath5k_hw *ah, in ath5k_setup_channel_powertable() argument
3277 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; in ath5k_setup_channel_powertable()
3287 ath5k_get_chan_pcal_surrounding_piers(ah, channel, in ath5k_setup_channel_powertable()
3306 tmpL = ah->ah_txpower.tmpL[pdg]; in ath5k_setup_channel_powertable()
3307 tmpR = ah->ah_txpower.tmpR[pdg]; in ath5k_setup_channel_powertable()
3408 ah->ah_txpower.txp_min_pwr = ath5k_get_interpolated_value(target, in ath5k_setup_channel_powertable()
3413 ah->ah_txpower.txp_max_pwr = ath5k_get_interpolated_value(target, in ath5k_setup_channel_powertable()
3424 ath5k_combine_linear_pcdac_curves(ah, table_min, table_max, in ath5k_setup_channel_powertable()
3430 ah->ah_txpower.txp_offset = 64 - (table_max[0] / 2); in ath5k_setup_channel_powertable()
3435 ath5k_fill_pwr_to_pcdac_table(ah, table_min, table_max); in ath5k_setup_channel_powertable()
3438 ah->ah_txpower.txp_min_idx = 0; in ath5k_setup_channel_powertable()
3439 ah->ah_txpower.txp_offset = 0; in ath5k_setup_channel_powertable()
3444 ath5k_combine_pwr_to_pdadc_curves(ah, table_min, table_max, in ath5k_setup_channel_powertable()
3449 ah->ah_txpower.txp_offset = table_min[0]; in ath5k_setup_channel_powertable()
3455 ah->ah_txpower.txp_setup = true; in ath5k_setup_channel_powertable()
3467 ath5k_write_channel_powertable(struct ath5k_hw *ah, u8 ee_mode, u8 type) in ath5k_write_channel_powertable() argument
3470 ath5k_write_pwr_to_pdadc_table(ah, ee_mode); in ath5k_write_channel_powertable()
3472 ath5k_write_pcdac_table(ah); in ath5k_write_channel_powertable()
3506 ath5k_setup_rate_powertable(struct ath5k_hw *ah, u16 max_pwr, in ath5k_setup_rate_powertable() argument
3517 max_pwr = min(max_pwr, (u16) ah->ah_txpower.txp_max_pwr) / 2; in ath5k_setup_rate_powertable()
3520 rates = ah->ah_txpower.txp_rates_power_table; in ath5k_setup_rate_powertable()
3555 (ah->ah_phy_revision < AR5K_SREV_PHY_5212A)) in ath5k_setup_rate_powertable()
3557 rates[i] -= ah->ah_txpower.txp_cck_ofdm_gainf_delta; in ath5k_setup_rate_powertable()
3565 ah->ah_txpower.txp_min_pwr = 2 * rates[7]; in ath5k_setup_rate_powertable()
3566 ah->ah_txpower.txp_cur_pwr = 2 * rates[0]; in ath5k_setup_rate_powertable()
3571 ah->ah_txpower.txp_ofdm = rates[7]; in ath5k_setup_rate_powertable()
3577 rate_idx_scaled = rates[i] + ah->ah_txpower.txp_offset; in ath5k_setup_rate_powertable()
3598 ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel, in ath5k_hw_txpower() argument
3602 struct ieee80211_channel *curr_channel = ah->ah_current_channel; in ath5k_hw_txpower()
3608 ATH5K_ERR(ah, "invalid tx power: %u\n", txpower); in ath5k_hw_txpower()
3612 ee_mode = ath5k_eeprom_mode_from_channel(ah, channel); in ath5k_hw_txpower()
3615 switch (ah->ah_radio) { in ath5k_hw_txpower()
3640 if (!ah->ah_txpower.txp_setup || in ath5k_hw_txpower()
3645 int requested_txpower = ah->ah_txpower.txp_requested; in ath5k_hw_txpower()
3647 memset(&ah->ah_txpower, 0, sizeof(ah->ah_txpower)); in ath5k_hw_txpower()
3650 ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER; in ath5k_hw_txpower()
3652 ah->ah_txpower.txp_requested = requested_txpower; in ath5k_hw_txpower()
3655 ret = ath5k_setup_channel_powertable(ah, channel, in ath5k_hw_txpower()
3662 ath5k_write_channel_powertable(ah, ee_mode, type); in ath5k_hw_txpower()
3665 ath5k_get_max_ctl_power(ah, channel); in ath5k_hw_txpower()
3675 ath5k_get_rate_pcal_data(ah, channel, &rate_info); in ath5k_hw_txpower()
3678 ath5k_setup_rate_powertable(ah, txpower, &rate_info, ee_mode); in ath5k_hw_txpower()
3681 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(3, 24) | in ath5k_hw_txpower()
3685 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(7, 24) | in ath5k_hw_txpower()
3689 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(10, 24) | in ath5k_hw_txpower()
3693 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(14, 24) | in ath5k_hw_txpower()
3698 if (ah->ah_txpower.txp_tpc) { in ath5k_hw_txpower()
3699 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE | in ath5k_hw_txpower()
3702 ath5k_hw_reg_write(ah, in ath5k_hw_txpower()
3708 ath5k_hw_reg_write(ah, AR5K_TUNE_MAX_TXPOWER, in ath5k_hw_txpower()
3724 ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower) in ath5k_hw_set_txpower_limit() argument
3726 ATH5K_DBG(ah, ATH5K_DEBUG_TXPOWER, in ath5k_hw_set_txpower_limit()
3729 return ath5k_hw_txpower(ah, ah->ah_current_channel, txpower); in ath5k_hw_set_txpower_limit()
3751 ath5k_hw_phy_init(struct ath5k_hw *ah, struct ieee80211_channel *channel, in ath5k_hw_phy_init() argument
3765 curr_channel = ah->ah_current_channel; in ath5k_hw_phy_init()
3774 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_RFBUS_REQ, in ath5k_hw_phy_init()
3777 if (ath5k_hw_reg_read(ah, AR5K_PHY_RFBUS_GRANT)) in ath5k_hw_phy_init()
3786 ret = ath5k_hw_channel(ah, channel); in ath5k_hw_phy_init()
3790 ath5k_hw_wait_for_synth(ah, channel); in ath5k_hw_phy_init()
3800 ret = ath5k_hw_txpower(ah, channel, ah->ah_txpower.txp_requested ? in ath5k_hw_phy_init()
3801 ah->ah_txpower.txp_requested * 2 : in ath5k_hw_phy_init()
3807 if (ah->ah_version == AR5K_AR5212 && in ath5k_hw_phy_init()
3810 ret = ath5k_hw_write_ofdm_timings(ah, channel); in ath5k_hw_phy_init()
3817 if (ah->ah_mac_srev >= AR5K_SREV_AR5424) in ath5k_hw_phy_init()
3818 ath5k_hw_set_spur_mitigation_filter(ah, in ath5k_hw_phy_init()
3834 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_RFBUS_REQ, in ath5k_hw_phy_init()
3840 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, in ath5k_hw_phy_init()
3852 if (ah->ah_version != AR5K_AR5210) { in ath5k_hw_phy_init()
3858 ret = ath5k_hw_rfgain_init(ah, channel->band); in ath5k_hw_phy_init()
3867 ret = ath5k_hw_rfregs_init(ah, channel, mode); in ath5k_hw_phy_init()
3873 if (ah->ah_radio == AR5K_RF5111) { in ath5k_hw_phy_init()
3875 AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG, in ath5k_hw_phy_init()
3878 AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG, in ath5k_hw_phy_init()
3882 } else if (ah->ah_version == AR5K_AR5210) { in ath5k_hw_phy_init()
3885 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT); in ath5k_hw_phy_init()
3890 ret = ath5k_hw_channel(ah, channel); in ath5k_hw_phy_init()
3899 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT); in ath5k_hw_phy_init()
3901 ath5k_hw_wait_for_synth(ah, channel); in ath5k_hw_phy_init()
3907 phy_tst1 = ath5k_hw_reg_read(ah, AR5K_PHY_TST1); in ath5k_hw_phy_init()
3908 ath5k_hw_reg_write(ah, AR5K_PHY_TST1_TXHOLD, AR5K_PHY_TST1); in ath5k_hw_phy_init()
3910 if (!(ath5k_hw_reg_read(ah, AR5K_PHY_ADC_TEST) & 0x10)) in ath5k_hw_phy_init()
3914 ath5k_hw_reg_write(ah, phy_tst1, AR5K_PHY_TST1); in ath5k_hw_phy_init()
3935 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, in ath5k_hw_phy_init()
3940 ah->ah_iq_cal_needed = false; in ath5k_hw_phy_init()
3942 ah->ah_iq_cal_needed = true; in ath5k_hw_phy_init()
3943 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, in ath5k_hw_phy_init()
3945 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, in ath5k_hw_phy_init()
3951 if (ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, in ath5k_hw_phy_init()
3953 ATH5K_ERR(ah, "gain calibration timeout (%uMHz)\n", in ath5k_hw_phy_init()
3958 ath5k_hw_set_antenna_mode(ah, ah->ah_ant_mode); in ath5k_hw_phy_init()