Lines Matching refs:ah
89 static void ar5008_write_bank6(struct ath_hw *ah, unsigned int *writecnt) in ar5008_write_bank6() argument
91 struct ar5416IniArray *array = &ah->iniBank6; in ar5008_write_bank6()
92 u32 *data = ah->analogBank6Data; in ar5008_write_bank6()
95 ENABLE_REGWRITE_BUFFER(ah); in ar5008_write_bank6()
98 REG_WRITE(ah, INI_RA(array, r, 0), data[r]); in ar5008_write_bank6()
102 REGWRITE_BUFFER_FLUSH(ah); in ar5008_write_bank6()
164 static void ar5008_hw_force_bias(struct ath_hw *ah, u16 synth_freq) in ar5008_hw_force_bias() argument
166 struct ath_common *common = ath9k_hw_common(ah); in ar5008_hw_force_bias()
171 if (!AR_SREV_5416(ah) || synth_freq >= 3000) in ar5008_hw_force_bias()
174 BUG_ON(AR_SREV_9280_20_OR_LATER(ah)); in ar5008_hw_force_bias()
190 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, tmp_reg, 3, 181, 3); in ar5008_hw_force_bias()
193 ar5008_write_bank6(ah, ®_writes); in ar5008_hw_force_bias()
203 static int ar5008_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan) in ar5008_hw_set_channel() argument
205 struct ath_common *common = ath9k_hw_common(ah); in ar5008_hw_set_channel()
213 ath9k_hw_get_channel_centers(ah, chan, ¢ers); in ar5008_hw_set_channel()
233 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL); in ar5008_hw_set_channel()
236 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, in ar5008_hw_set_channel()
239 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, in ar5008_hw_set_channel()
250 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) in ar5008_hw_set_channel()
262 ar5008_hw_force_bias(ah, freq); in ar5008_hw_set_channel()
268 REG_WRITE(ah, AR_PHY(0x37), reg32); in ar5008_hw_set_channel()
270 ah->curchan = chan; in ar5008_hw_set_channel()
275 void ar5008_hw_cmn_spur_mitigate(struct ath_hw *ah, in ar5008_hw_cmn_spur_mitigate() argument
312 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); in ar5008_hw_cmn_spur_mitigate()
313 REG_WRITE(ah, chan_mask_reg[i], chan_mask); in ar5008_hw_cmn_spur_mitigate()
345 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
346 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
356 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
357 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
367 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
368 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
378 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
379 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
389 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
390 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
400 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
401 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
411 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
412 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
422 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
423 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
432 static void ar5008_hw_spur_mitigate(struct ath_hw *ah, in ar5008_hw_spur_mitigate() argument
447 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz); in ar5008_hw_spur_mitigate()
462 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0)); in ar5008_hw_spur_mitigate()
468 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new); in ar5008_hw_spur_mitigate()
475 REG_WRITE(ah, AR_PHY_SPUR_REG, new); in ar5008_hw_spur_mitigate()
486 REG_WRITE(ah, AR_PHY_TIMING11, new); in ar5008_hw_spur_mitigate()
488 ar5008_hw_cmn_spur_mitigate(ah, chan, bin); in ar5008_hw_spur_mitigate()
497 static int ar5008_hw_rf_alloc_ext_banks(struct ath_hw *ah) in ar5008_hw_rf_alloc_ext_banks() argument
499 int size = ah->iniBank6.ia_rows * sizeof(u32); in ar5008_hw_rf_alloc_ext_banks()
501 if (AR_SREV_9280_20_OR_LATER(ah)) in ar5008_hw_rf_alloc_ext_banks()
504 ah->analogBank6Data = devm_kzalloc(ah->dev, size, GFP_KERNEL); in ar5008_hw_rf_alloc_ext_banks()
505 if (!ah->analogBank6Data) in ar5008_hw_rf_alloc_ext_banks()
524 static bool ar5008_hw_set_rf_regs(struct ath_hw *ah, in ar5008_hw_set_rf_regs() argument
539 if (AR_SREV_9280_20_OR_LATER(ah)) in ar5008_hw_set_rf_regs()
543 eepMinorRev = ah->eep_ops->get_eeprom_rev(ah); in ar5008_hw_set_rf_regs()
545 for (i = 0; i < ah->iniBank6.ia_rows; i++) in ar5008_hw_set_rf_regs()
546 ah->analogBank6Data[i] = INI_RA(&ah->iniBank6, i, modesIndex); in ar5008_hw_set_rf_regs()
551 ob2GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_2); in ar5008_hw_set_rf_regs()
552 db2GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_2); in ar5008_hw_set_rf_regs()
553 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, in ar5008_hw_set_rf_regs()
555 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, in ar5008_hw_set_rf_regs()
558 ob5GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_5); in ar5008_hw_set_rf_regs()
559 db5GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_5); in ar5008_hw_set_rf_regs()
560 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, in ar5008_hw_set_rf_regs()
562 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, in ar5008_hw_set_rf_regs()
572 ar5008_write_bank6(ah, ®Writes); in ar5008_hw_set_rf_regs()
578 static void ar5008_hw_init_bb(struct ath_hw *ah, in ar5008_hw_init_bb() argument
583 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; in ar5008_hw_init_bb()
585 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); in ar5008_hw_init_bb()
587 ath9k_hw_synth_delay(ah, chan, synthDelay); in ar5008_hw_init_bb()
590 static void ar5008_hw_init_chain_masks(struct ath_hw *ah) in ar5008_hw_init_chain_masks() argument
594 rx_chainmask = ah->rxchainmask; in ar5008_hw_init_chain_masks()
595 tx_chainmask = ah->txchainmask; in ar5008_hw_init_chain_masks()
600 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, in ar5008_hw_init_chain_masks()
604 if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) { in ar5008_hw_init_chain_masks()
605 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7); in ar5008_hw_init_chain_masks()
606 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7); in ar5008_hw_init_chain_masks()
613 ENABLE_REGWRITE_BUFFER(ah); in ar5008_hw_init_chain_masks()
614 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask); in ar5008_hw_init_chain_masks()
615 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask); in ar5008_hw_init_chain_masks()
618 ENABLE_REGWRITE_BUFFER(ah); in ar5008_hw_init_chain_masks()
622 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask); in ar5008_hw_init_chain_masks()
624 REGWRITE_BUFFER_FLUSH(ah); in ar5008_hw_init_chain_masks()
627 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, in ar5008_hw_init_chain_masks()
630 if (AR_SREV_9100(ah)) in ar5008_hw_init_chain_masks()
631 REG_WRITE(ah, AR_PHY_ANALOG_SWAP, in ar5008_hw_init_chain_masks()
632 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001); in ar5008_hw_init_chain_masks()
635 static void ar5008_hw_override_ini(struct ath_hw *ah, in ar5008_hw_override_ini() argument
645 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); in ar5008_hw_override_ini()
647 if (AR_SREV_9280_20_OR_LATER(ah)) { in ar5008_hw_override_ini()
655 val = REG_READ(ah, AR_PCU_MISC_MODE2) & in ar5008_hw_override_ini()
658 if (!AR_SREV_9271(ah)) in ar5008_hw_override_ini()
661 if (AR_SREV_9287_11_OR_LATER(ah)) in ar5008_hw_override_ini()
666 REG_WRITE(ah, AR_PCU_MISC_MODE2, val); in ar5008_hw_override_ini()
669 if (AR_SREV_9280_20_OR_LATER(ah)) in ar5008_hw_override_ini()
675 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11); in ar5008_hw_override_ini()
681 if (AR_SREV_9100(ah) || AR_SREV_9160(ah)) { in ar5008_hw_override_ini()
682 val = REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS); in ar5008_hw_override_ini()
684 REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val); in ar5008_hw_override_ini()
688 static void ar5008_hw_set_channel_regs(struct ath_hw *ah, in ar5008_hw_set_channel_regs() argument
694 if (AR_SREV_9285_12_OR_LATER(ah)) in ar5008_hw_set_channel_regs()
695 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) & in ar5008_hw_set_channel_regs()
708 ENABLE_REGWRITE_BUFFER(ah); in ar5008_hw_set_channel_regs()
709 REG_WRITE(ah, AR_PHY_TURBO, phymode); in ar5008_hw_set_channel_regs()
713 ath9k_hw_set11nmac2040(ah, chan); in ar5008_hw_set_channel_regs()
715 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S); in ar5008_hw_set_channel_regs()
716 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S); in ar5008_hw_set_channel_regs()
718 REGWRITE_BUFFER_FLUSH(ah); in ar5008_hw_set_channel_regs()
722 static int ar5008_hw_process_ini(struct ath_hw *ah, in ar5008_hw_process_ini() argument
725 struct ath_common *common = ath9k_hw_common(ah); in ar5008_hw_process_ini()
741 REG_WRITE(ah, AR_PHY(0), 0x00000007); in ar5008_hw_process_ini()
744 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO); in ar5008_hw_process_ini()
745 if (ah->eep_ops->set_addac) in ar5008_hw_process_ini()
746 ah->eep_ops->set_addac(ah, chan); in ar5008_hw_process_ini()
748 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites); in ar5008_hw_process_ini()
749 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); in ar5008_hw_process_ini()
751 ENABLE_REGWRITE_BUFFER(ah); in ar5008_hw_process_ini()
753 for (i = 0; i < ah->iniModes.ia_rows; i++) { in ar5008_hw_process_ini()
754 u32 reg = INI_RA(&ah->iniModes, i, 0); in ar5008_hw_process_ini()
755 u32 val = INI_RA(&ah->iniModes, i, modesIndex); in ar5008_hw_process_ini()
757 if (reg == AR_AN_TOP2 && ah->need_an_top2_fixup) in ar5008_hw_process_ini()
760 REG_WRITE(ah, reg, val); in ar5008_hw_process_ini()
763 && ah->config.analog_shiftreg in ar5008_hw_process_ini()
771 REGWRITE_BUFFER_FLUSH(ah); in ar5008_hw_process_ini()
773 if (AR_SREV_9280(ah) || AR_SREV_9287_11_OR_LATER(ah)) in ar5008_hw_process_ini()
774 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites); in ar5008_hw_process_ini()
776 if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) || in ar5008_hw_process_ini()
777 AR_SREV_9287_11_OR_LATER(ah)) in ar5008_hw_process_ini()
778 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites); in ar5008_hw_process_ini()
780 if (AR_SREV_9271_10(ah)) { in ar5008_hw_process_ini()
781 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, AR_PHY_SPECTRAL_SCAN_ENA); in ar5008_hw_process_ini()
782 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_ADC_ON, 0xa); in ar5008_hw_process_ini()
785 ENABLE_REGWRITE_BUFFER(ah); in ar5008_hw_process_ini()
788 for (i = 0; i < ah->iniCommon.ia_rows; i++) { in ar5008_hw_process_ini()
789 u32 reg = INI_RA(&ah->iniCommon, i, 0); in ar5008_hw_process_ini()
790 u32 val = INI_RA(&ah->iniCommon, i, 1); in ar5008_hw_process_ini()
792 REG_WRITE(ah, reg, val); in ar5008_hw_process_ini()
795 && ah->config.analog_shiftreg in ar5008_hw_process_ini()
803 REGWRITE_BUFFER_FLUSH(ah); in ar5008_hw_process_ini()
805 REG_WRITE_ARRAY(&ah->iniBB_RfGain, freqIndex, regWrites); in ar5008_hw_process_ini()
807 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) in ar5008_hw_process_ini()
808 REG_WRITE_ARRAY(&ah->iniModesFastClock, modesIndex, in ar5008_hw_process_ini()
811 ar5008_hw_override_ini(ah, chan); in ar5008_hw_process_ini()
812 ar5008_hw_set_channel_regs(ah, chan); in ar5008_hw_process_ini()
813 ar5008_hw_init_chain_masks(ah); in ar5008_hw_process_ini()
814 ath9k_olc_init(ah); in ar5008_hw_process_ini()
815 ath9k_hw_apply_txpower(ah, chan, false); in ar5008_hw_process_ini()
818 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) { in ar5008_hw_process_ini()
819 ath_err(ath9k_hw_common(ah), "ar5416SetRfRegs failed\n"); in ar5008_hw_process_ini()
826 static void ar5008_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan) in ar5008_hw_set_rfmode() argument
838 if (!AR_SREV_9280_20_OR_LATER(ah)) in ar5008_hw_set_rfmode()
842 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) in ar5008_hw_set_rfmode()
845 REG_WRITE(ah, AR_PHY_MODE, rfMode); in ar5008_hw_set_rfmode()
848 static void ar5008_hw_mark_phy_inactive(struct ath_hw *ah) in ar5008_hw_mark_phy_inactive() argument
850 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); in ar5008_hw_mark_phy_inactive()
853 static void ar5008_hw_set_delta_slope(struct ath_hw *ah, in ar5008_hw_set_delta_slope() argument
865 ath9k_hw_get_channel_centers(ah, chan, ¢ers); in ar5008_hw_set_delta_slope()
868 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man, in ar5008_hw_set_delta_slope()
871 REG_RMW_FIELD(ah, AR_PHY_TIMING3, in ar5008_hw_set_delta_slope()
873 REG_RMW_FIELD(ah, AR_PHY_TIMING3, in ar5008_hw_set_delta_slope()
878 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man, in ar5008_hw_set_delta_slope()
881 REG_RMW_FIELD(ah, AR_PHY_HALFGI, in ar5008_hw_set_delta_slope()
883 REG_RMW_FIELD(ah, AR_PHY_HALFGI, in ar5008_hw_set_delta_slope()
887 static bool ar5008_hw_rfbus_req(struct ath_hw *ah) in ar5008_hw_rfbus_req() argument
889 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN); in ar5008_hw_rfbus_req()
890 return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN, in ar5008_hw_rfbus_req()
894 static void ar5008_hw_rfbus_done(struct ath_hw *ah) in ar5008_hw_rfbus_done() argument
896 u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; in ar5008_hw_rfbus_done()
898 ath9k_hw_synth_delay(ah, ah->curchan, synthDelay); in ar5008_hw_rfbus_done()
900 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0); in ar5008_hw_rfbus_done()
903 static void ar5008_restore_chainmask(struct ath_hw *ah) in ar5008_restore_chainmask() argument
905 int rx_chainmask = ah->rxchainmask; in ar5008_restore_chainmask()
908 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask); in ar5008_restore_chainmask()
909 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask); in ar5008_restore_chainmask()
913 static u32 ar9160_hw_compute_pll_control(struct ath_hw *ah, in ar9160_hw_compute_pll_control() argument
933 static u32 ar5008_hw_compute_pll_control(struct ath_hw *ah, in ar5008_hw_compute_pll_control() argument
953 static bool ar5008_hw_ani_control_new(struct ath_hw *ah, in ar5008_hw_ani_control_new() argument
957 struct ath_common *common = ath9k_hw_common(ah); in ar5008_hw_ani_control_new()
958 struct ath9k_channel *chan = ah->curchan; in ar5008_hw_ani_control_new()
959 struct ar5416AniState *aniState = &ah->ani; in ar5008_hw_ani_control_new()
962 switch (cmd & ah->ani_function) { in ar5008_hw_ani_control_new()
997 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, in ar5008_hw_ani_control_new()
1000 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, in ar5008_hw_ani_control_new()
1003 REG_RMW_FIELD(ah, AR_PHY_SFCORR, in ar5008_hw_ani_control_new()
1005 REG_RMW_FIELD(ah, AR_PHY_SFCORR, in ar5008_hw_ani_control_new()
1007 REG_RMW_FIELD(ah, AR_PHY_SFCORR, in ar5008_hw_ani_control_new()
1009 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, in ar5008_hw_ani_control_new()
1013 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, in ar5008_hw_ani_control_new()
1015 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, in ar5008_hw_ani_control_new()
1017 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, in ar5008_hw_ani_control_new()
1019 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, in ar5008_hw_ani_control_new()
1023 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW, in ar5008_hw_ani_control_new()
1026 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW, in ar5008_hw_ani_control_new()
1037 ah->stats.ast_ani_ofdmon++; in ar5008_hw_ani_control_new()
1039 ah->stats.ast_ani_ofdmoff++; in ar5008_hw_ani_control_new()
1048 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG, in ar5008_hw_ani_control_new()
1050 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW, in ar5008_hw_ani_control_new()
1071 ah->stats.ast_ani_stepup++; in ar5008_hw_ani_control_new()
1073 ah->stats.ast_ani_stepdown++; in ar5008_hw_ani_control_new()
1082 REG_RMW_FIELD(ah, AR_PHY_TIMING5, in ar5008_hw_ani_control_new()
1085 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA, in ar5008_hw_ani_control_new()
1106 ah->stats.ast_ani_spurup++; in ar5008_hw_ani_control_new()
1108 ah->stats.ast_ani_spurdown++; in ar5008_hw_ani_control_new()
1137 static void ar5008_hw_do_getnf(struct ath_hw *ah, in ar5008_hw_do_getnf() argument
1142 nf = MS(REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR); in ar5008_hw_do_getnf()
1145 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR_PHY_CH1_MINCCA_PWR); in ar5008_hw_do_getnf()
1148 nf = MS(REG_READ(ah, AR_PHY_CH2_CCA), AR_PHY_CH2_MINCCA_PWR); in ar5008_hw_do_getnf()
1151 if (!IS_CHAN_HT40(ah->curchan)) in ar5008_hw_do_getnf()
1154 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR_PHY_EXT_MINCCA_PWR); in ar5008_hw_do_getnf()
1157 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR_PHY_CH1_EXT_MINCCA_PWR); in ar5008_hw_do_getnf()
1160 nf = MS(REG_READ(ah, AR_PHY_CH2_EXT_CCA), AR_PHY_CH2_EXT_MINCCA_PWR); in ar5008_hw_do_getnf()
1169 static void ar5008_hw_ani_cache_ini_regs(struct ath_hw *ah) in ar5008_hw_ani_cache_ini_regs() argument
1171 struct ath_common *common = ath9k_hw_common(ah); in ar5008_hw_ani_cache_ini_regs()
1172 struct ath9k_channel *chan = ah->curchan; in ar5008_hw_ani_cache_ini_regs()
1173 struct ar5416AniState *aniState = &ah->ani; in ar5008_hw_ani_cache_ini_regs()
1180 ah->hw_version.macVersion, in ar5008_hw_ani_cache_ini_regs()
1181 ah->hw_version.macRev, in ar5008_hw_ani_cache_ini_regs()
1182 ah->opmode, in ar5008_hw_ani_cache_ini_regs()
1185 val = REG_READ(ah, AR_PHY_SFCORR); in ar5008_hw_ani_cache_ini_regs()
1190 val = REG_READ(ah, AR_PHY_SFCORR_LOW); in ar5008_hw_ani_cache_ini_regs()
1195 val = REG_READ(ah, AR_PHY_SFCORR_EXT); in ar5008_hw_ani_cache_ini_regs()
1200 iniDef->firstep = REG_READ_FIELD(ah, in ar5008_hw_ani_cache_ini_regs()
1203 iniDef->firstepLow = REG_READ_FIELD(ah, in ar5008_hw_ani_cache_ini_regs()
1206 iniDef->cycpwrThr1 = REG_READ_FIELD(ah, in ar5008_hw_ani_cache_ini_regs()
1209 iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah, in ar5008_hw_ani_cache_ini_regs()
1220 static void ar5008_hw_set_nf_limits(struct ath_hw *ah) in ar5008_hw_set_nf_limits() argument
1222 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ; in ar5008_hw_set_nf_limits()
1223 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_2GHZ; in ar5008_hw_set_nf_limits()
1224 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_5416_2GHZ; in ar5008_hw_set_nf_limits()
1225 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ; in ar5008_hw_set_nf_limits()
1226 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_5GHZ; in ar5008_hw_set_nf_limits()
1227 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_5416_5GHZ; in ar5008_hw_set_nf_limits()
1230 static void ar5008_hw_set_radar_params(struct ath_hw *ah, in ar5008_hw_set_radar_params() argument
1236 REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA); in ar5008_hw_set_radar_params()
1247 radar_1 = REG_READ(ah, AR_PHY_RADAR_1); in ar5008_hw_set_radar_params()
1256 REG_WRITE(ah, AR_PHY_RADAR_0, radar_0); in ar5008_hw_set_radar_params()
1257 REG_WRITE(ah, AR_PHY_RADAR_1, radar_1); in ar5008_hw_set_radar_params()
1259 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA); in ar5008_hw_set_radar_params()
1261 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA); in ar5008_hw_set_radar_params()
1264 static void ar5008_hw_set_radar_conf(struct ath_hw *ah) in ar5008_hw_set_radar_conf() argument
1266 struct ath_hw_radar_conf *conf = &ah->radar_conf; in ar5008_hw_set_radar_conf()
1278 static void ar5008_hw_init_txpower_cck(struct ath_hw *ah, int16_t *rate_array) in ar5008_hw_init_txpower_cck() argument
1281 ah->tx_power[0] = CCK_DELTA(rate_array[rate1l]); in ar5008_hw_init_txpower_cck()
1282 ah->tx_power[1] = CCK_DELTA(min(rate_array[rate2l], in ar5008_hw_init_txpower_cck()
1284 ah->tx_power[2] = CCK_DELTA(min(rate_array[rate5_5l], in ar5008_hw_init_txpower_cck()
1286 ah->tx_power[3] = CCK_DELTA(min(rate_array[rate11l], in ar5008_hw_init_txpower_cck()
1291 static void ar5008_hw_init_txpower_ofdm(struct ath_hw *ah, int16_t *rate_array, in ar5008_hw_init_txpower_ofdm() argument
1297 ah->tx_power[i] = rate_array[idx]; in ar5008_hw_init_txpower_ofdm()
1302 static void ar5008_hw_init_txpower_ht(struct ath_hw *ah, int16_t *rate_array, in ar5008_hw_init_txpower_ht() argument
1309 ah->tx_power[i] = rate_array[mcs_idx] + ht40_delta; in ar5008_hw_init_txpower_ht()
1312 memcpy(&ah->tx_power[ds_offset], &ah->tx_power[ss_offset], in ar5008_hw_init_txpower_ht()
1316 void ar5008_hw_init_rate_txpower(struct ath_hw *ah, int16_t *rate_array, in ar5008_hw_init_rate_txpower() argument
1320 ar5008_hw_init_txpower_ofdm(ah, rate_array, in ar5008_hw_init_rate_txpower()
1323 ar5008_hw_init_txpower_ht(ah, rate_array, in ar5008_hw_init_rate_txpower()
1330 ar5008_hw_init_txpower_cck(ah, rate_array); in ar5008_hw_init_rate_txpower()
1331 ar5008_hw_init_txpower_ofdm(ah, rate_array, in ar5008_hw_init_rate_txpower()
1334 ar5008_hw_init_txpower_ht(ah, rate_array, in ar5008_hw_init_rate_txpower()
1343 int ar5008_hw_attach_phy_ops(struct ath_hw *ah) in ar5008_hw_attach_phy_ops() argument
1345 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); in ar5008_hw_attach_phy_ops()
1356 ret = ar5008_hw_rf_alloc_ext_banks(ah); in ar5008_hw_attach_phy_ops()
1379 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) in ar5008_hw_attach_phy_ops()
1384 ar5008_hw_set_nf_limits(ah); in ar5008_hw_attach_phy_ops()
1385 ar5008_hw_set_radar_conf(ah); in ar5008_hw_attach_phy_ops()
1386 memcpy(ah->nf_regs, ar5416_cca_regs, sizeof(ah->nf_regs)); in ar5008_hw_attach_phy_ops()