Lines Matching refs:ah
26 static int ar9002_hw_init_mode_regs(struct ath_hw *ah) in ar9002_hw_init_mode_regs() argument
28 if (AR_SREV_9271(ah)) { in ar9002_hw_init_mode_regs()
29 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271); in ar9002_hw_init_mode_regs()
30 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271); in ar9002_hw_init_mode_regs()
31 INIT_INI_ARRAY(&ah->iniModes_9271_ANI_reg, ar9271Modes_9271_ANI_reg); in ar9002_hw_init_mode_regs()
35 INIT_INI_ARRAY(&ah->iniPcieSerdes, in ar9002_hw_init_mode_regs()
38 if (AR_SREV_9287_11_OR_LATER(ah)) { in ar9002_hw_init_mode_regs()
39 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1); in ar9002_hw_init_mode_regs()
40 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1); in ar9002_hw_init_mode_regs()
41 } else if (AR_SREV_9285_12_OR_LATER(ah)) { in ar9002_hw_init_mode_regs()
42 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2); in ar9002_hw_init_mode_regs()
43 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2); in ar9002_hw_init_mode_regs()
44 } else if (AR_SREV_9280_20_OR_LATER(ah)) { in ar9002_hw_init_mode_regs()
45 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2); in ar9002_hw_init_mode_regs()
46 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2); in ar9002_hw_init_mode_regs()
48 INIT_INI_ARRAY(&ah->iniModesFastClock, in ar9002_hw_init_mode_regs()
50 } else if (AR_SREV_9160_10_OR_LATER(ah)) { in ar9002_hw_init_mode_regs()
51 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160); in ar9002_hw_init_mode_regs()
52 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160); in ar9002_hw_init_mode_regs()
53 if (AR_SREV_9160_11(ah)) { in ar9002_hw_init_mode_regs()
54 INIT_INI_ARRAY(&ah->iniAddac, in ar9002_hw_init_mode_regs()
57 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160); in ar9002_hw_init_mode_regs()
59 } else if (AR_SREV_9100_OR_LATER(ah)) { in ar9002_hw_init_mode_regs()
60 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100); in ar9002_hw_init_mode_regs()
61 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100); in ar9002_hw_init_mode_regs()
62 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100); in ar9002_hw_init_mode_regs()
64 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes); in ar9002_hw_init_mode_regs()
65 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common); in ar9002_hw_init_mode_regs()
66 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac); in ar9002_hw_init_mode_regs()
69 if (!AR_SREV_9280_20_OR_LATER(ah)) { in ar9002_hw_init_mode_regs()
71 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain); in ar9002_hw_init_mode_regs()
74 if (!AR_SREV_5416(ah)) in ar9002_hw_init_mode_regs()
75 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6TPC_9100); in ar9002_hw_init_mode_regs()
77 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6TPC); in ar9002_hw_init_mode_regs()
81 if (AR_SREV_9160(ah) || !AR_SREV_5416_22_OR_LATER(ah)) { in ar9002_hw_init_mode_regs()
82 struct ar5416IniArray *addac = &ah->iniAddac; in ar9002_hw_init_mode_regs()
86 data = devm_kzalloc(ah->dev, size, GFP_KERNEL); in ar9002_hw_init_mode_regs()
93 if (!AR_SREV_5416_22_OR_LATER(ah)) { in ar9002_hw_init_mode_regs()
98 if (AR_SREV_9287_11_OR_LATER(ah)) { in ar9002_hw_init_mode_regs()
99 INIT_INI_ARRAY(&ah->iniCckfirNormal, in ar9002_hw_init_mode_regs()
101 INIT_INI_ARRAY(&ah->iniCckfirJapan2484, in ar9002_hw_init_mode_regs()
107 static void ar9280_20_hw_init_rxgain_ini(struct ath_hw *ah) in ar9280_20_hw_init_rxgain_ini() argument
111 if (ah->eep_ops->get_eeprom_rev(ah) >= AR5416_EEP_MINOR_VER_17) { in ar9280_20_hw_init_rxgain_ini()
112 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE); in ar9280_20_hw_init_rxgain_ini()
115 INIT_INI_ARRAY(&ah->iniModesRxGain, in ar9280_20_hw_init_rxgain_ini()
118 INIT_INI_ARRAY(&ah->iniModesRxGain, in ar9280_20_hw_init_rxgain_ini()
121 INIT_INI_ARRAY(&ah->iniModesRxGain, in ar9280_20_hw_init_rxgain_ini()
124 INIT_INI_ARRAY(&ah->iniModesRxGain, in ar9280_20_hw_init_rxgain_ini()
129 static void ar9280_20_hw_init_txgain_ini(struct ath_hw *ah, u32 txgain_type) in ar9280_20_hw_init_txgain_ini() argument
131 if (ah->eep_ops->get_eeprom_rev(ah) >= AR5416_EEP_MINOR_VER_19) { in ar9280_20_hw_init_txgain_ini()
133 INIT_INI_ARRAY(&ah->iniModesTxGain, in ar9280_20_hw_init_txgain_ini()
136 INIT_INI_ARRAY(&ah->iniModesTxGain, in ar9280_20_hw_init_txgain_ini()
139 INIT_INI_ARRAY(&ah->iniModesTxGain, in ar9280_20_hw_init_txgain_ini()
144 static void ar9271_hw_init_txgain_ini(struct ath_hw *ah, u32 txgain_type) in ar9271_hw_init_txgain_ini() argument
147 INIT_INI_ARRAY(&ah->iniModesTxGain, in ar9271_hw_init_txgain_ini()
150 INIT_INI_ARRAY(&ah->iniModesTxGain, in ar9271_hw_init_txgain_ini()
154 static void ar9002_hw_init_mode_gain_regs(struct ath_hw *ah) in ar9002_hw_init_mode_gain_regs() argument
156 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE); in ar9002_hw_init_mode_gain_regs()
158 if (AR_SREV_9287_11_OR_LATER(ah)) in ar9002_hw_init_mode_gain_regs()
159 INIT_INI_ARRAY(&ah->iniModesRxGain, in ar9002_hw_init_mode_gain_regs()
161 else if (AR_SREV_9280_20(ah)) in ar9002_hw_init_mode_gain_regs()
162 ar9280_20_hw_init_rxgain_ini(ah); in ar9002_hw_init_mode_gain_regs()
164 if (AR_SREV_9271(ah)) { in ar9002_hw_init_mode_gain_regs()
165 ar9271_hw_init_txgain_ini(ah, txgain_type); in ar9002_hw_init_mode_gain_regs()
166 } else if (AR_SREV_9287_11_OR_LATER(ah)) { in ar9002_hw_init_mode_gain_regs()
167 INIT_INI_ARRAY(&ah->iniModesTxGain, in ar9002_hw_init_mode_gain_regs()
169 } else if (AR_SREV_9280_20(ah)) { in ar9002_hw_init_mode_gain_regs()
170 ar9280_20_hw_init_txgain_ini(ah, txgain_type); in ar9002_hw_init_mode_gain_regs()
171 } else if (AR_SREV_9285_12_OR_LATER(ah)) { in ar9002_hw_init_mode_gain_regs()
174 if (AR_SREV_9285E_20(ah)) { in ar9002_hw_init_mode_gain_regs()
175 INIT_INI_ARRAY(&ah->iniModesTxGain, in ar9002_hw_init_mode_gain_regs()
178 INIT_INI_ARRAY(&ah->iniModesTxGain, in ar9002_hw_init_mode_gain_regs()
182 if (AR_SREV_9285E_20(ah)) { in ar9002_hw_init_mode_gain_regs()
183 INIT_INI_ARRAY(&ah->iniModesTxGain, in ar9002_hw_init_mode_gain_regs()
186 INIT_INI_ARRAY(&ah->iniModesTxGain, in ar9002_hw_init_mode_gain_regs()
202 static void ar9002_hw_configpcipowersave(struct ath_hw *ah, in ar9002_hw_configpcipowersave() argument
210 if (AR_SREV_9280_20_OR_LATER(ah)) { in ar9002_hw_configpcipowersave()
216 for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) { in ar9002_hw_configpcipowersave()
217 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0), in ar9002_hw_configpcipowersave()
218 INI_RA(&ah->iniPcieSerdes, i, 1)); in ar9002_hw_configpcipowersave()
221 ENABLE_REGWRITE_BUFFER(ah); in ar9002_hw_configpcipowersave()
223 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); in ar9002_hw_configpcipowersave()
224 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); in ar9002_hw_configpcipowersave()
227 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039); in ar9002_hw_configpcipowersave()
228 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824); in ar9002_hw_configpcipowersave()
229 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579); in ar9002_hw_configpcipowersave()
235 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff); in ar9002_hw_configpcipowersave()
237 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); in ar9002_hw_configpcipowersave()
238 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); in ar9002_hw_configpcipowersave()
239 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007); in ar9002_hw_configpcipowersave()
242 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); in ar9002_hw_configpcipowersave()
244 REGWRITE_BUFFER_FLUSH(ah); in ar9002_hw_configpcipowersave()
252 REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); in ar9002_hw_configpcipowersave()
254 val = REG_READ(ah, AR_WA); in ar9002_hw_configpcipowersave()
262 if (ah->config.pcie_waen) { in ar9002_hw_configpcipowersave()
263 if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE) in ar9002_hw_configpcipowersave()
266 if (AR_SREV_9285(ah) || AR_SREV_9271(ah) || AR_SREV_9287(ah)) { in ar9002_hw_configpcipowersave()
269 } else if (AR_SREV_9280(ah)) { in ar9002_hw_configpcipowersave()
275 if (AR_SREV_9280(ah) || AR_SREV_9285(ah) || AR_SREV_9287(ah)) { in ar9002_hw_configpcipowersave()
283 if (AR_SREV_9280(ah)) in ar9002_hw_configpcipowersave()
286 if (AR_SREV_9285E_20(ah)) in ar9002_hw_configpcipowersave()
289 REG_WRITE(ah, AR_WA, val); in ar9002_hw_configpcipowersave()
291 if (ah->config.pcie_waen) { in ar9002_hw_configpcipowersave()
292 val = ah->config.pcie_waen; in ar9002_hw_configpcipowersave()
295 if (AR_SREV_9285(ah) || AR_SREV_9271(ah) || AR_SREV_9287(ah)) { in ar9002_hw_configpcipowersave()
298 } else if (AR_SREV_9280(ah)) { in ar9002_hw_configpcipowersave()
311 if (AR_SREV_9285(ah) || AR_SREV_9287(ah)) in ar9002_hw_configpcipowersave()
314 if (AR_SREV_9285E_20(ah)) in ar9002_hw_configpcipowersave()
317 REG_WRITE(ah, AR_WA, val); in ar9002_hw_configpcipowersave()
320 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); in ar9002_hw_configpcipowersave()
324 static int ar9002_hw_get_radiorev(struct ath_hw *ah) in ar9002_hw_get_radiorev() argument
329 ENABLE_REGWRITE_BUFFER(ah); in ar9002_hw_get_radiorev()
331 REG_WRITE(ah, AR_PHY(0x36), 0x00007058); in ar9002_hw_get_radiorev()
333 REG_WRITE(ah, AR_PHY(0x20), 0x00010000); in ar9002_hw_get_radiorev()
335 REGWRITE_BUFFER_FLUSH(ah); in ar9002_hw_get_radiorev()
337 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff; in ar9002_hw_get_radiorev()
343 int ar9002_hw_rf_claim(struct ath_hw *ah) in ar9002_hw_rf_claim() argument
347 REG_WRITE(ah, AR_PHY(0), 0x00000007); in ar9002_hw_rf_claim()
349 val = ar9002_hw_get_radiorev(ah); in ar9002_hw_rf_claim()
360 ath_err(ath9k_hw_common(ah), in ar9002_hw_rf_claim()
366 ah->hw_version.analog5GhzRev = val; in ar9002_hw_rf_claim()
371 void ar9002_hw_enable_async_fifo(struct ath_hw *ah) in ar9002_hw_enable_async_fifo() argument
373 if (AR_SREV_9287_13_OR_LATER(ah)) { in ar9002_hw_enable_async_fifo()
374 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3, in ar9002_hw_enable_async_fifo()
376 REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO); in ar9002_hw_enable_async_fifo()
377 REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3, in ar9002_hw_enable_async_fifo()
379 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3, in ar9002_hw_enable_async_fifo()
384 static void ar9002_hw_init_hang_checks(struct ath_hw *ah) in ar9002_hw_init_hang_checks() argument
386 if (AR_SREV_9100(ah) || AR_SREV_9160(ah)) { in ar9002_hw_init_hang_checks()
387 ah->config.hw_hang_checks |= HW_BB_RIFS_HANG; in ar9002_hw_init_hang_checks()
388 ah->config.hw_hang_checks |= HW_BB_DFS_HANG; in ar9002_hw_init_hang_checks()
391 if (AR_SREV_9280(ah)) in ar9002_hw_init_hang_checks()
392 ah->config.hw_hang_checks |= HW_BB_RX_CLEAR_STUCK_HANG; in ar9002_hw_init_hang_checks()
394 if (AR_SREV_5416(ah) || AR_SREV_9100(ah) || AR_SREV_9160(ah)) in ar9002_hw_init_hang_checks()
395 ah->config.hw_hang_checks |= HW_MAC_HANG; in ar9002_hw_init_hang_checks()
399 int ar9002_hw_attach_ops(struct ath_hw *ah) in ar9002_hw_attach_ops() argument
401 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); in ar9002_hw_attach_ops()
402 struct ath_hw_ops *ops = ath9k_hw_ops(ah); in ar9002_hw_attach_ops()
405 ret = ar9002_hw_init_mode_regs(ah); in ar9002_hw_attach_ops()
414 ret = ar5008_hw_attach_phy_ops(ah); in ar9002_hw_attach_ops()
418 if (AR_SREV_9280_20_OR_LATER(ah)) in ar9002_hw_attach_ops()
419 ar9002_hw_attach_phy_ops(ah); in ar9002_hw_attach_ops()
421 ar9002_hw_attach_calib_ops(ah); in ar9002_hw_attach_ops()
422 ar9002_hw_attach_mac_ops(ah); in ar9002_hw_attach_ops()
426 void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan) in ar9002_hw_load_ani_reg() argument
436 ENABLE_REGWRITE_BUFFER(ah); in ar9002_hw_load_ani_reg()
438 for (i = 0; i < ah->iniModes_9271_ANI_reg.ia_rows; i++) { in ar9002_hw_load_ani_reg()
439 u32 reg = INI_RA(&ah->iniModes_9271_ANI_reg, i, 0); in ar9002_hw_load_ani_reg()
440 u32 val = INI_RA(&ah->iniModes_9271_ANI_reg, i, modesIndex); in ar9002_hw_load_ani_reg()
444 val_orig = REG_READ(ah, reg); in ar9002_hw_load_ani_reg()
448 REG_WRITE(ah, reg, val|val_orig); in ar9002_hw_load_ani_reg()
450 REG_WRITE(ah, reg, val); in ar9002_hw_load_ani_reg()
453 REGWRITE_BUFFER_FLUSH(ah); in ar9002_hw_load_ani_reg()