Lines Matching refs:ah
149 static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan) in ar9003_hw_set_channel() argument
156 ath9k_hw_get_channel_centers(ah, chan, ¢ers); in ar9003_hw_set_channel()
160 if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || in ar9003_hw_set_channel()
161 AR_SREV_9531(ah) || AR_SREV_9550(ah) || in ar9003_hw_set_channel()
162 AR_SREV_9561(ah) || AR_SREV_9565(ah)) { in ar9003_hw_set_channel()
163 if (ah->is_clk_25mhz) in ar9003_hw_set_channel()
171 } else if (AR_SREV_9340(ah)) { in ar9003_hw_set_channel()
172 if (ah->is_clk_25mhz) { in ar9003_hw_set_channel()
185 if ((AR_SREV_9340(ah) || AR_SREV_9550(ah) || in ar9003_hw_set_channel()
186 AR_SREV_9531(ah) || AR_SREV_9561(ah)) && in ar9003_hw_set_channel()
187 ah->is_clk_25mhz) { in ar9003_hw_set_channel()
206 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32); in ar9003_hw_set_channel()
209 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH4, in ar9003_hw_set_channel()
215 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32); in ar9003_hw_set_channel()
221 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32); in ar9003_hw_set_channel()
223 ah->curchan = chan; in ar9003_hw_set_channel()
238 static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah, in ar9003_hw_spur_mitigate_mrc_cck() argument
245 u8 *spur_fbin_ptr = ar9003_get_spur_chan_ptr(ah, IS_CHAN_2GHZ(chan)); in ar9003_hw_spur_mitigate_mrc_cck()
252 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) || in ar9003_hw_spur_mitigate_mrc_cck()
253 AR_SREV_9550(ah) || AR_SREV_9561(ah)) { in ar9003_hw_spur_mitigate_mrc_cck()
259 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL, in ar9003_hw_spur_mitigate_mrc_cck()
269 range = AR_SREV_9462(ah) ? 5 : 10; in ar9003_hw_spur_mitigate_mrc_cck()
275 if (AR_SREV_9462(ah) && (i == 0 || i == 3)) in ar9003_hw_spur_mitigate_mrc_cck()
279 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) || in ar9003_hw_spur_mitigate_mrc_cck()
280 AR_SREV_9550(ah) || AR_SREV_9561(ah)) in ar9003_hw_spur_mitigate_mrc_cck()
299 REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL, in ar9003_hw_spur_mitigate_mrc_cck()
301 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, in ar9003_hw_spur_mitigate_mrc_cck()
303 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, in ar9003_hw_spur_mitigate_mrc_cck()
306 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, in ar9003_hw_spur_mitigate_mrc_cck()
309 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, in ar9003_hw_spur_mitigate_mrc_cck()
317 REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL, in ar9003_hw_spur_mitigate_mrc_cck()
319 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, in ar9003_hw_spur_mitigate_mrc_cck()
321 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, in ar9003_hw_spur_mitigate_mrc_cck()
326 static void ar9003_hw_spur_ofdm_clear(struct ath_hw *ah) in ar9003_hw_spur_ofdm_clear() argument
328 REG_RMW_FIELD(ah, AR_PHY_TIMING4, in ar9003_hw_spur_ofdm_clear()
330 REG_RMW_FIELD(ah, AR_PHY_TIMING11, in ar9003_hw_spur_ofdm_clear()
332 REG_RMW_FIELD(ah, AR_PHY_TIMING11, in ar9003_hw_spur_ofdm_clear()
334 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, in ar9003_hw_spur_ofdm_clear()
336 REG_RMW_FIELD(ah, AR_PHY_TIMING11, in ar9003_hw_spur_ofdm_clear()
338 REG_RMW_FIELD(ah, AR_PHY_TIMING11, in ar9003_hw_spur_ofdm_clear()
340 REG_RMW_FIELD(ah, AR_PHY_TIMING4, in ar9003_hw_spur_ofdm_clear()
342 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, in ar9003_hw_spur_ofdm_clear()
344 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, in ar9003_hw_spur_ofdm_clear()
347 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, in ar9003_hw_spur_ofdm_clear()
349 REG_RMW_FIELD(ah, AR_PHY_TIMING4, in ar9003_hw_spur_ofdm_clear()
351 REG_RMW_FIELD(ah, AR_PHY_TIMING4, in ar9003_hw_spur_ofdm_clear()
353 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK, in ar9003_hw_spur_ofdm_clear()
355 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A, in ar9003_hw_spur_ofdm_clear()
357 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK, in ar9003_hw_spur_ofdm_clear()
359 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK, in ar9003_hw_spur_ofdm_clear()
361 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK, in ar9003_hw_spur_ofdm_clear()
363 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A, in ar9003_hw_spur_ofdm_clear()
365 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, in ar9003_hw_spur_ofdm_clear()
369 static void ar9003_hw_spur_ofdm(struct ath_hw *ah, in ar9003_hw_spur_ofdm() argument
380 REG_RMW_FIELD(ah, AR_PHY_TIMING4, in ar9003_hw_spur_ofdm()
382 REG_RMW_FIELD(ah, AR_PHY_TIMING11, in ar9003_hw_spur_ofdm()
384 REG_RMW_FIELD(ah, AR_PHY_TIMING11, in ar9003_hw_spur_ofdm()
386 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, in ar9003_hw_spur_ofdm()
388 REG_RMW_FIELD(ah, AR_PHY_TIMING11, in ar9003_hw_spur_ofdm()
391 if (!(AR_SREV_9565(ah) && range == 10 && synth_freq == 2437)) in ar9003_hw_spur_ofdm()
392 REG_RMW_FIELD(ah, AR_PHY_TIMING11, in ar9003_hw_spur_ofdm()
395 REG_RMW_FIELD(ah, AR_PHY_TIMING4, in ar9003_hw_spur_ofdm()
397 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, in ar9003_hw_spur_ofdm()
399 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, in ar9003_hw_spur_ofdm()
402 if (!AR_SREV_9340(ah) && in ar9003_hw_spur_ofdm()
403 REG_READ_FIELD(ah, AR_PHY_MODE, in ar9003_hw_spur_ofdm()
405 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, in ar9003_hw_spur_ofdm()
414 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, in ar9003_hw_spur_ofdm()
416 REG_RMW_FIELD(ah, AR_PHY_TIMING4, in ar9003_hw_spur_ofdm()
418 REG_RMW_FIELD(ah, AR_PHY_TIMING4, in ar9003_hw_spur_ofdm()
420 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK, in ar9003_hw_spur_ofdm()
422 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A, in ar9003_hw_spur_ofdm()
424 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK, in ar9003_hw_spur_ofdm()
426 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK, in ar9003_hw_spur_ofdm()
428 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK, in ar9003_hw_spur_ofdm()
430 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A, in ar9003_hw_spur_ofdm()
432 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, in ar9003_hw_spur_ofdm()
436 static void ar9003_hw_spur_ofdm_9565(struct ath_hw *ah, in ar9003_hw_spur_ofdm_9565() argument
447 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK, in ar9003_hw_spur_ofdm_9565()
452 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_B, in ar9003_hw_spur_ofdm_9565()
456 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK, in ar9003_hw_spur_ofdm_9565()
459 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK, in ar9003_hw_spur_ofdm_9565()
461 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK, in ar9003_hw_spur_ofdm_9565()
465 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_B, in ar9003_hw_spur_ofdm_9565()
469 static void ar9003_hw_spur_ofdm_work(struct ath_hw *ah, in ar9003_hw_spur_ofdm_work() argument
481 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL, in ar9003_hw_spur_ofdm_work()
490 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL, in ar9003_hw_spur_ofdm_work()
511 ar9003_hw_spur_ofdm(ah, in ar9003_hw_spur_ofdm_work()
520 static void ar9003_hw_spur_mitigate_ofdm(struct ath_hw *ah, in ar9003_hw_spur_mitigate_ofdm() argument
529 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; in ar9003_hw_spur_mitigate_ofdm()
545 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL, in ar9003_hw_spur_mitigate_ofdm()
555 ar9003_hw_spur_ofdm_clear(ah); in ar9003_hw_spur_mitigate_ofdm()
561 ar9003_hw_spur_ofdm_work(ah, chan, freq_offset, in ar9003_hw_spur_mitigate_ofdm()
564 if (AR_SREV_9565(ah) && (i < 4)) { in ar9003_hw_spur_mitigate_ofdm()
569 ar9003_hw_spur_ofdm_9565(ah, freq_offset); in ar9003_hw_spur_mitigate_ofdm()
577 static void ar9003_hw_spur_mitigate(struct ath_hw *ah, in ar9003_hw_spur_mitigate() argument
580 if (!AR_SREV_9565(ah)) in ar9003_hw_spur_mitigate()
581 ar9003_hw_spur_mitigate_mrc_cck(ah, chan); in ar9003_hw_spur_mitigate()
582 ar9003_hw_spur_mitigate_ofdm(ah, chan); in ar9003_hw_spur_mitigate()
585 static u32 ar9003_hw_compute_pll_control_soc(struct ath_hw *ah, in ar9003_hw_compute_pll_control_soc() argument
602 static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah, in ar9003_hw_compute_pll_control() argument
619 static void ar9003_hw_set_channel_regs(struct ath_hw *ah, in ar9003_hw_set_channel_regs() argument
626 (REG_READ(ah, AR_PHY_GEN_CTRL) & AR_PHY_GC_ENABLE_DAC_FIFO); in ar9003_hw_set_channel_regs()
631 if (!AR_SREV_9561(ah)) in ar9003_hw_set_channel_regs()
644 phymode |= REG_READ(ah, AR_PHY_GEN_CTRL); in ar9003_hw_set_channel_regs()
648 REG_WRITE(ah, AR_PHY_GEN_CTRL, phymode); in ar9003_hw_set_channel_regs()
651 ath9k_hw_set11nmac2040(ah, chan); in ar9003_hw_set_channel_regs()
654 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S); in ar9003_hw_set_channel_regs()
656 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S); in ar9003_hw_set_channel_regs()
659 static void ar9003_hw_init_bb(struct ath_hw *ah, in ar9003_hw_init_bb() argument
669 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; in ar9003_hw_init_bb()
672 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); in ar9003_hw_init_bb()
673 ath9k_hw_synth_delay(ah, chan, synthDelay); in ar9003_hw_init_bb()
676 void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx) in ar9003_hw_set_chain_masks() argument
678 if (ah->caps.tx_chainmask == 5 || ah->caps.rx_chainmask == 5) in ar9003_hw_set_chain_masks()
679 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, in ar9003_hw_set_chain_masks()
682 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx); in ar9003_hw_set_chain_masks()
683 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx); in ar9003_hw_set_chain_masks()
685 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && (tx == 0x7)) in ar9003_hw_set_chain_masks()
688 REG_WRITE(ah, AR_SELFGEN_MASK, tx); in ar9003_hw_set_chain_masks()
694 static void ar9003_hw_override_ini(struct ath_hw *ah) in ar9003_hw_override_ini() argument
703 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); in ar9003_hw_override_ini()
712 val = REG_READ(ah, AR_PCU_MISC_MODE2) & (~AR_ADHOC_MCAST_KEYID_ENABLE); in ar9003_hw_override_ini()
716 REG_WRITE(ah, AR_PCU_MISC_MODE2, val); in ar9003_hw_override_ini()
718 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { in ar9003_hw_override_ini()
719 REG_WRITE(ah, AR_GLB_SWREG_DISCONT_MODE, in ar9003_hw_override_ini()
722 if (REG_READ_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_0, in ar9003_hw_override_ini()
724 ah->enabled_cals |= TX_IQ_CAL; in ar9003_hw_override_ini()
726 ah->enabled_cals &= ~TX_IQ_CAL; in ar9003_hw_override_ini()
730 if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE) in ar9003_hw_override_ini()
731 ah->enabled_cals |= TX_CL_CAL; in ar9003_hw_override_ini()
733 ah->enabled_cals &= ~TX_CL_CAL; in ar9003_hw_override_ini()
735 if (AR_SREV_9340(ah) || AR_SREV_9531(ah) || AR_SREV_9550(ah) || in ar9003_hw_override_ini()
736 AR_SREV_9561(ah)) { in ar9003_hw_override_ini()
737 if (ah->is_clk_25mhz) { in ar9003_hw_override_ini()
738 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1); in ar9003_hw_override_ini()
739 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7); in ar9003_hw_override_ini()
740 REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae); in ar9003_hw_override_ini()
742 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1); in ar9003_hw_override_ini()
743 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400); in ar9003_hw_override_ini()
744 REG_WRITE(ah, AR_SLP32_INC, 0x0001e800); in ar9003_hw_override_ini()
750 static void ar9003_hw_prog_ini(struct ath_hw *ah, in ar9003_hw_prog_ini() argument
772 REG_WRITE(ah, reg, val); in ar9003_hw_prog_ini()
778 static int ar9550_hw_get_modes_txgain_index(struct ath_hw *ah, in ar9550_hw_get_modes_txgain_index() argument
803 static int ar9561_hw_get_modes_txgain_index(struct ath_hw *ah, in ar9561_hw_get_modes_txgain_index() argument
816 static void ar9003_doubler_fix(struct ath_hw *ah) in ar9003_doubler_fix() argument
818 if (AR_SREV_9300(ah) || AR_SREV_9580(ah) || AR_SREV_9550(ah)) { in ar9003_doubler_fix()
819 REG_RMW(ah, AR_PHY_65NM_CH0_RXTX2, in ar9003_doubler_fix()
822 REG_RMW(ah, AR_PHY_65NM_CH1_RXTX2, in ar9003_doubler_fix()
825 REG_RMW(ah, AR_PHY_65NM_CH2_RXTX2, in ar9003_doubler_fix()
831 REG_CLR_BIT(ah, AR_PHY_65NM_CH0_RXTX2, in ar9003_doubler_fix()
833 REG_CLR_BIT(ah, AR_PHY_65NM_CH1_RXTX2, in ar9003_doubler_fix()
835 REG_CLR_BIT(ah, AR_PHY_65NM_CH2_RXTX2, in ar9003_doubler_fix()
840 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_RXTX2, in ar9003_doubler_fix()
842 REG_RMW_FIELD(ah, AR_PHY_65NM_CH1_RXTX2, in ar9003_doubler_fix()
844 REG_RMW_FIELD(ah, AR_PHY_65NM_CH2_RXTX2, in ar9003_doubler_fix()
849 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH12, in ar9003_doubler_fix()
852 REG_RMW(ah, AR_PHY_65NM_CH0_RXTX2, 0, in ar9003_doubler_fix()
855 REG_RMW(ah, AR_PHY_65NM_CH1_RXTX2, 0, in ar9003_doubler_fix()
858 REG_RMW(ah, AR_PHY_65NM_CH2_RXTX2, 0, in ar9003_doubler_fix()
864 static int ar9003_hw_process_ini(struct ath_hw *ah, in ar9003_hw_process_ini() argument
879 ar9003_hw_prog_ini(ah, &ah->iniSOC[i], modesIndex); in ar9003_hw_process_ini()
880 ar9003_hw_prog_ini(ah, &ah->iniMac[i], modesIndex); in ar9003_hw_process_ini()
881 ar9003_hw_prog_ini(ah, &ah->iniBB[i], modesIndex); in ar9003_hw_process_ini()
882 ar9003_hw_prog_ini(ah, &ah->iniRadio[i], modesIndex); in ar9003_hw_process_ini()
883 if (i == ATH_INI_POST && AR_SREV_9462_20_OR_LATER(ah)) in ar9003_hw_process_ini()
884 ar9003_hw_prog_ini(ah, in ar9003_hw_process_ini()
885 &ah->ini_radio_post_sys2ant, in ar9003_hw_process_ini()
889 ar9003_doubler_fix(ah); in ar9003_hw_process_ini()
894 REG_WRITE_ARRAY(&ah->iniModesRxGain, 1, regWrites); in ar9003_hw_process_ini()
896 if (AR_SREV_9462_20_OR_LATER(ah)) { in ar9003_hw_process_ini()
900 if (ar9003_hw_get_rx_gain_idx(ah) == 2) { in ar9003_hw_process_ini()
901 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_core, in ar9003_hw_process_ini()
903 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_postamble, in ar9003_hw_process_ini()
910 if ((ar9003_hw_get_rx_gain_idx(ah) == 2) || in ar9003_hw_process_ini()
911 (ar9003_hw_get_rx_gain_idx(ah) == 3)) { in ar9003_hw_process_ini()
912 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_xlna, in ar9003_hw_process_ini()
917 if (AR_SREV_9550(ah) || AR_SREV_9561(ah)) in ar9003_hw_process_ini()
918 REG_WRITE_ARRAY(&ah->ini_modes_rx_gain_bounds, modesIndex, in ar9003_hw_process_ini()
921 if (AR_SREV_9561(ah) && (ar9003_hw_get_rx_gain_idx(ah) == 0)) in ar9003_hw_process_ini()
922 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_xlna, in ar9003_hw_process_ini()
927 if (AR_SREV_9550(ah) || AR_SREV_9531(ah) || AR_SREV_9561(ah)) { in ar9003_hw_process_ini()
930 if (AR_SREV_9550(ah)) in ar9003_hw_process_ini()
931 modes_txgain_index = ar9550_hw_get_modes_txgain_index(ah, chan); in ar9003_hw_process_ini()
933 if (AR_SREV_9561(ah)) in ar9003_hw_process_ini()
935 ar9561_hw_get_modes_txgain_index(ah, chan); in ar9003_hw_process_ini()
940 REG_WRITE_ARRAY(&ah->iniModesTxGain, modes_txgain_index, in ar9003_hw_process_ini()
943 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites); in ar9003_hw_process_ini()
950 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) in ar9003_hw_process_ini()
951 REG_WRITE_ARRAY(&ah->iniModesFastClock, in ar9003_hw_process_ini()
957 REG_WRITE_ARRAY(&ah->iniAdditional, 1, regWrites); in ar9003_hw_process_ini()
963 ar9003_hw_prog_ini(ah, &ah->iniCckfirJapan2484, 1); in ar9003_hw_process_ini()
965 if (AR_SREV_9531(ah)) in ar9003_hw_process_ini()
966 REG_RMW_FIELD(ah, AR_PHY_FCAL_2_0, in ar9003_hw_process_ini()
970 ah->modes_index = modesIndex; in ar9003_hw_process_ini()
971 ar9003_hw_override_ini(ah); in ar9003_hw_process_ini()
972 ar9003_hw_set_channel_regs(ah, chan); in ar9003_hw_process_ini()
973 ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask); in ar9003_hw_process_ini()
974 ath9k_hw_apply_txpower(ah, chan, false); in ar9003_hw_process_ini()
979 static void ar9003_hw_set_rfmode(struct ath_hw *ah, in ar9003_hw_set_rfmode() argument
992 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) in ar9003_hw_set_rfmode()
996 REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL, in ar9003_hw_set_rfmode()
999 REG_WRITE(ah, AR_PHY_MODE, rfMode); in ar9003_hw_set_rfmode()
1002 static void ar9003_hw_mark_phy_inactive(struct ath_hw *ah) in ar9003_hw_mark_phy_inactive() argument
1004 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); in ar9003_hw_mark_phy_inactive()
1007 static void ar9003_hw_set_delta_slope(struct ath_hw *ah, in ar9003_hw_set_delta_slope() argument
1027 ath9k_hw_get_channel_centers(ah, chan, ¢ers); in ar9003_hw_set_delta_slope()
1030 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man, in ar9003_hw_set_delta_slope()
1033 REG_RMW_FIELD(ah, AR_PHY_TIMING3, in ar9003_hw_set_delta_slope()
1035 REG_RMW_FIELD(ah, AR_PHY_TIMING3, in ar9003_hw_set_delta_slope()
1044 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man, in ar9003_hw_set_delta_slope()
1048 REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA, in ar9003_hw_set_delta_slope()
1050 REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA, in ar9003_hw_set_delta_slope()
1054 static bool ar9003_hw_rfbus_req(struct ath_hw *ah) in ar9003_hw_rfbus_req() argument
1056 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN); in ar9003_hw_rfbus_req()
1057 return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN, in ar9003_hw_rfbus_req()
1065 static void ar9003_hw_rfbus_done(struct ath_hw *ah) in ar9003_hw_rfbus_done() argument
1067 u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; in ar9003_hw_rfbus_done()
1069 ath9k_hw_synth_delay(ah, ah->curchan, synthDelay); in ar9003_hw_rfbus_done()
1071 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0); in ar9003_hw_rfbus_done()
1074 static bool ar9003_hw_ani_control(struct ath_hw *ah, in ar9003_hw_ani_control() argument
1077 struct ath_common *common = ath9k_hw_common(ah); in ar9003_hw_ani_control()
1078 struct ath9k_channel *chan = ah->curchan; in ar9003_hw_ani_control()
1079 struct ar5416AniState *aniState = &ah->ani; in ar9003_hw_ani_control()
1087 switch (cmd & ah->ani_function) { in ar9003_hw_ani_control()
1098 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) in ar9003_hw_ani_control()
1122 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, in ar9003_hw_ani_control()
1125 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, in ar9003_hw_ani_control()
1128 REG_RMW_FIELD(ah, AR_PHY_SFCORR, in ar9003_hw_ani_control()
1131 REG_RMW_FIELD(ah, AR_PHY_SFCORR, in ar9003_hw_ani_control()
1134 REG_RMW_FIELD(ah, AR_PHY_SFCORR, in ar9003_hw_ani_control()
1137 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, in ar9003_hw_ani_control()
1140 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, in ar9003_hw_ani_control()
1143 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, in ar9003_hw_ani_control()
1146 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, in ar9003_hw_ani_control()
1149 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, in ar9003_hw_ani_control()
1154 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW, in ar9003_hw_ani_control()
1157 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW, in ar9003_hw_ani_control()
1168 ah->stats.ast_ani_ofdmon++; in ar9003_hw_ani_control()
1170 ah->stats.ast_ani_ofdmoff++; in ar9003_hw_ani_control()
1196 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG, in ar9003_hw_ani_control()
1212 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW, in ar9003_hw_ani_control()
1233 ah->stats.ast_ani_stepup++; in ar9003_hw_ani_control()
1235 ah->stats.ast_ani_stepdown++; in ar9003_hw_ani_control()
1260 REG_RMW_FIELD(ah, AR_PHY_TIMING5, in ar9003_hw_ani_control()
1276 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA, in ar9003_hw_ani_control()
1297 ah->stats.ast_ani_spurup++; in ar9003_hw_ani_control()
1299 ah->stats.ast_ani_spurdown++; in ar9003_hw_ani_control()
1311 if (ah->caps.rx_chainmask == 1) in ar9003_hw_ani_control()
1314 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL, in ar9003_hw_ani_control()
1316 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL, in ar9003_hw_ani_control()
1324 ah->stats.ast_ani_ccklow++; in ar9003_hw_ani_control()
1326 ah->stats.ast_ani_cckhigh++; in ar9003_hw_ani_control()
1348 static void ar9003_hw_do_getnf(struct ath_hw *ah, in ar9003_hw_do_getnf() argument
1360 if (ah->rxchainmask & BIT(i)) { in ar9003_hw_do_getnf()
1361 nf = MS(REG_READ(ah, ah->nf_regs[i]), in ar9003_hw_do_getnf()
1365 if (IS_CHAN_HT40(ah->curchan)) { in ar9003_hw_do_getnf()
1368 nf = MS(REG_READ(ah, ah->nf_regs[ext_idx]), in ar9003_hw_do_getnf()
1376 static void ar9003_hw_set_nf_limits(struct ath_hw *ah) in ar9003_hw_set_nf_limits() argument
1378 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ; in ar9003_hw_set_nf_limits()
1379 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ; in ar9003_hw_set_nf_limits()
1380 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9300_2GHZ; in ar9003_hw_set_nf_limits()
1381 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ; in ar9003_hw_set_nf_limits()
1382 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ; in ar9003_hw_set_nf_limits()
1383 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9300_5GHZ; in ar9003_hw_set_nf_limits()
1385 if (AR_SREV_9330(ah)) in ar9003_hw_set_nf_limits()
1386 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9330_2GHZ; in ar9003_hw_set_nf_limits()
1388 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { in ar9003_hw_set_nf_limits()
1389 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_2GHZ; in ar9003_hw_set_nf_limits()
1390 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9462_2GHZ; in ar9003_hw_set_nf_limits()
1391 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_5GHZ; in ar9003_hw_set_nf_limits()
1392 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9462_5GHZ; in ar9003_hw_set_nf_limits()
1401 static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah) in ar9003_hw_ani_cache_ini_regs() argument
1404 struct ath_common *common = ath9k_hw_common(ah); in ar9003_hw_ani_cache_ini_regs()
1405 struct ath9k_channel *chan = ah->curchan; in ar9003_hw_ani_cache_ini_regs()
1409 aniState = &ah->ani; in ar9003_hw_ani_cache_ini_regs()
1413 ah->hw_version.macVersion, in ar9003_hw_ani_cache_ini_regs()
1414 ah->hw_version.macRev, in ar9003_hw_ani_cache_ini_regs()
1415 ah->opmode, in ar9003_hw_ani_cache_ini_regs()
1418 val = REG_READ(ah, AR_PHY_SFCORR); in ar9003_hw_ani_cache_ini_regs()
1423 val = REG_READ(ah, AR_PHY_SFCORR_LOW); in ar9003_hw_ani_cache_ini_regs()
1428 val = REG_READ(ah, AR_PHY_SFCORR_EXT); in ar9003_hw_ani_cache_ini_regs()
1433 iniDef->firstep = REG_READ_FIELD(ah, in ar9003_hw_ani_cache_ini_regs()
1436 iniDef->firstepLow = REG_READ_FIELD(ah, in ar9003_hw_ani_cache_ini_regs()
1439 iniDef->cycpwrThr1 = REG_READ_FIELD(ah, in ar9003_hw_ani_cache_ini_regs()
1442 iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah, in ar9003_hw_ani_cache_ini_regs()
1453 static void ar9003_hw_set_radar_params(struct ath_hw *ah, in ar9003_hw_set_radar_params() argument
1460 REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA); in ar9003_hw_set_radar_params()
1471 radar_1 = REG_READ(ah, AR_PHY_RADAR_1); in ar9003_hw_set_radar_params()
1480 REG_WRITE(ah, AR_PHY_RADAR_0, radar_0); in ar9003_hw_set_radar_params()
1481 REG_WRITE(ah, AR_PHY_RADAR_1, radar_1); in ar9003_hw_set_radar_params()
1483 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA); in ar9003_hw_set_radar_params()
1485 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA); in ar9003_hw_set_radar_params()
1487 if (AR_SREV_9300(ah) || AR_SREV_9340(ah) || AR_SREV_9580(ah)) { in ar9003_hw_set_radar_params()
1488 REG_WRITE_ARRAY(&ah->ini_dfs, in ar9003_hw_set_radar_params()
1489 IS_CHAN_HT40(ah->curchan) ? 2 : 1, regWrites); in ar9003_hw_set_radar_params()
1493 static void ar9003_hw_set_radar_conf(struct ath_hw *ah) in ar9003_hw_set_radar_conf() argument
1495 struct ath_hw_radar_conf *conf = &ah->radar_conf; in ar9003_hw_set_radar_conf()
1507 static void ar9003_hw_antdiv_comb_conf_get(struct ath_hw *ah, in ar9003_hw_antdiv_comb_conf_get() argument
1512 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); in ar9003_hw_antdiv_comb_conf_get()
1520 if (AR_SREV_9330_11(ah)) { in ar9003_hw_antdiv_comb_conf_get()
1524 } else if (AR_SREV_9485(ah)) { in ar9003_hw_antdiv_comb_conf_get()
1528 } else if (AR_SREV_9565(ah)) { in ar9003_hw_antdiv_comb_conf_get()
1539 static void ar9003_hw_antdiv_comb_conf_set(struct ath_hw *ah, in ar9003_hw_antdiv_comb_conf_set() argument
1544 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); in ar9003_hw_antdiv_comb_conf_set()
1561 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); in ar9003_hw_antdiv_comb_conf_set()
1566 static void ar9003_hw_set_bt_ant_diversity(struct ath_hw *ah, bool enable) in ar9003_hw_set_bt_ant_diversity() argument
1568 struct ath9k_hw_capabilities *pCap = &ah->caps; in ar9003_hw_set_bt_ant_diversity()
1572 if (!AR_SREV_9485(ah) && !AR_SREV_9565(ah)) in ar9003_hw_set_bt_ant_diversity()
1575 if (AR_SREV_9485(ah)) { in ar9003_hw_set_bt_ant_diversity()
1576 regval = ar9003_hw_ant_ctrl_common_2_get(ah, in ar9003_hw_set_bt_ant_diversity()
1577 IS_CHAN_2GHZ(ah->curchan)); in ar9003_hw_set_bt_ant_diversity()
1580 regval |= ah->config.ant_ctrl_comm2g_switch_enable; in ar9003_hw_set_bt_ant_diversity()
1582 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2, in ar9003_hw_set_bt_ant_diversity()
1586 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); in ar9003_hw_set_bt_ant_diversity()
1592 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); in ar9003_hw_set_bt_ant_diversity()
1595 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); in ar9003_hw_set_bt_ant_diversity()
1597 if (AR_SREV_9485_11_OR_LATER(ah)) { in ar9003_hw_set_bt_ant_diversity()
1601 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); in ar9003_hw_set_bt_ant_diversity()
1607 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); in ar9003_hw_set_bt_ant_diversity()
1612 regval = REG_READ(ah, AR_PHY_CCK_DETECT); in ar9003_hw_set_bt_ant_diversity()
1618 REG_WRITE(ah, AR_PHY_CCK_DETECT, regval); in ar9003_hw_set_bt_ant_diversity()
1621 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); in ar9003_hw_set_bt_ant_diversity()
1634 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); in ar9003_hw_set_bt_ant_diversity()
1636 } else if (AR_SREV_9565(ah)) { in ar9003_hw_set_bt_ant_diversity()
1638 REG_SET_BIT(ah, AR_PHY_MC_GAIN_CTRL, in ar9003_hw_set_bt_ant_diversity()
1640 REG_SET_BIT(ah, AR_PHY_MC_GAIN_CTRL, in ar9003_hw_set_bt_ant_diversity()
1642 REG_SET_BIT(ah, AR_PHY_CCK_DETECT, in ar9003_hw_set_bt_ant_diversity()
1644 REG_SET_BIT(ah, AR_PHY_RESTART, in ar9003_hw_set_bt_ant_diversity()
1646 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, in ar9003_hw_set_bt_ant_diversity()
1649 REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL, in ar9003_hw_set_bt_ant_diversity()
1651 REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL, in ar9003_hw_set_bt_ant_diversity()
1653 REG_CLR_BIT(ah, AR_PHY_CCK_DETECT, in ar9003_hw_set_bt_ant_diversity()
1655 REG_CLR_BIT(ah, AR_PHY_RESTART, in ar9003_hw_set_bt_ant_diversity()
1657 REG_CLR_BIT(ah, AR_BTCOEX_WL_LNADIV, in ar9003_hw_set_bt_ant_diversity()
1660 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); in ar9003_hw_set_bt_ant_diversity()
1669 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); in ar9003_hw_set_bt_ant_diversity()
1676 static int ar9003_hw_fast_chan_change(struct ath_hw *ah, in ar9003_hw_fast_chan_change() argument
1688 txgain_index = AR_SREV_9531(ah) ? 1 : modesIndex; in ar9003_hw_fast_chan_change()
1690 if (modesIndex == ah->modes_index) { in ar9003_hw_fast_chan_change()
1695 ar9003_hw_prog_ini(ah, &ah->iniSOC[ATH_INI_POST], modesIndex); in ar9003_hw_fast_chan_change()
1696 ar9003_hw_prog_ini(ah, &ah->iniMac[ATH_INI_POST], modesIndex); in ar9003_hw_fast_chan_change()
1697 ar9003_hw_prog_ini(ah, &ah->iniBB[ATH_INI_POST], modesIndex); in ar9003_hw_fast_chan_change()
1698 ar9003_hw_prog_ini(ah, &ah->iniRadio[ATH_INI_POST], modesIndex); in ar9003_hw_fast_chan_change()
1700 if (AR_SREV_9462_20_OR_LATER(ah)) in ar9003_hw_fast_chan_change()
1701 ar9003_hw_prog_ini(ah, &ah->ini_radio_post_sys2ant, in ar9003_hw_fast_chan_change()
1704 REG_WRITE_ARRAY(&ah->iniModesTxGain, txgain_index, regWrites); in ar9003_hw_fast_chan_change()
1706 if (AR_SREV_9462_20_OR_LATER(ah)) { in ar9003_hw_fast_chan_change()
1710 if (ar9003_hw_get_rx_gain_idx(ah) == 2) { in ar9003_hw_fast_chan_change()
1711 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_core, in ar9003_hw_fast_chan_change()
1713 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_postamble, in ar9003_hw_fast_chan_change()
1722 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) in ar9003_hw_fast_chan_change()
1723 REG_WRITE_ARRAY(&ah->iniModesFastClock, modesIndex, regWrites); in ar9003_hw_fast_chan_change()
1725 if (AR_SREV_9565(ah)) in ar9003_hw_fast_chan_change()
1726 REG_WRITE_ARRAY(&ah->iniModesFastClock, 1, regWrites); in ar9003_hw_fast_chan_change()
1732 ar9003_hw_prog_ini(ah, &ah->iniCckfirJapan2484, 1); in ar9003_hw_fast_chan_change()
1734 ah->modes_index = modesIndex; in ar9003_hw_fast_chan_change()
1738 ar9003_hw_set_rfmode(ah, chan); in ar9003_hw_fast_chan_change()
1742 static void ar9003_hw_spectral_scan_config(struct ath_hw *ah, in ar9003_hw_spectral_scan_config() argument
1748 REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN, in ar9003_hw_spectral_scan_config()
1753 REG_SET_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_FFT_ENA); in ar9003_hw_spectral_scan_config()
1754 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, AR_PHY_SPECTRAL_SCAN_ENABLE); in ar9003_hw_spectral_scan_config()
1767 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, in ar9003_hw_spectral_scan_config()
1770 REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN, in ar9003_hw_spectral_scan_config()
1773 REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN, in ar9003_hw_spectral_scan_config()
1775 REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN, in ar9003_hw_spectral_scan_config()
1777 REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN, in ar9003_hw_spectral_scan_config()
1783 static void ar9003_hw_spectral_scan_trigger(struct ath_hw *ah) in ar9003_hw_spectral_scan_trigger() argument
1785 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, in ar9003_hw_spectral_scan_trigger()
1788 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, in ar9003_hw_spectral_scan_trigger()
1792 static void ar9003_hw_spectral_scan_wait(struct ath_hw *ah) in ar9003_hw_spectral_scan_wait() argument
1794 struct ath_common *common = ath9k_hw_common(ah); in ar9003_hw_spectral_scan_wait()
1797 if (!ath9k_hw_wait(ah, AR_PHY_SPECTRAL_SCAN, in ar9003_hw_spectral_scan_wait()
1805 static void ar9003_hw_tx99_start(struct ath_hw *ah, u32 qnum) in ar9003_hw_tx99_start() argument
1807 REG_SET_BIT(ah, AR_PHY_TEST, PHY_AGC_CLR); in ar9003_hw_tx99_start()
1808 REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS); in ar9003_hw_tx99_start()
1809 REG_WRITE(ah, AR_CR, AR_CR_RXD); in ar9003_hw_tx99_start()
1810 REG_WRITE(ah, AR_DLCL_IFS(qnum), 0); in ar9003_hw_tx99_start()
1811 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, 20); /* 50 OK */ in ar9003_hw_tx99_start()
1812 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, 20); in ar9003_hw_tx99_start()
1813 REG_WRITE(ah, AR_TIME_OUT, 0x00000400); in ar9003_hw_tx99_start()
1814 REG_WRITE(ah, AR_DRETRY_LIMIT(qnum), 0xffffffff); in ar9003_hw_tx99_start()
1815 REG_SET_BIT(ah, AR_QMISC(qnum), AR_Q_MISC_DCU_EARLY_TERM_REQ); in ar9003_hw_tx99_start()
1818 static void ar9003_hw_tx99_stop(struct ath_hw *ah) in ar9003_hw_tx99_stop() argument
1820 REG_CLR_BIT(ah, AR_PHY_TEST, PHY_AGC_CLR); in ar9003_hw_tx99_stop()
1821 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS); in ar9003_hw_tx99_stop()
1824 static void ar9003_hw_tx99_set_txpower(struct ath_hw *ah, u8 txpower) in ar9003_hw_tx99_set_txpower() argument
1833 ar9003_hw_tx_power_regwrite(ah, p_pwr_array); in ar9003_hw_tx99_set_txpower()
1836 static void ar9003_hw_init_txpower_cck(struct ath_hw *ah, u8 *rate_array) in ar9003_hw_init_txpower_cck() argument
1838 ah->tx_power[0] = rate_array[ALL_TARGET_LEGACY_1L_5L]; in ar9003_hw_init_txpower_cck()
1839 ah->tx_power[1] = rate_array[ALL_TARGET_LEGACY_1L_5L]; in ar9003_hw_init_txpower_cck()
1840 ah->tx_power[2] = min(rate_array[ALL_TARGET_LEGACY_1L_5L], in ar9003_hw_init_txpower_cck()
1842 ah->tx_power[3] = min(rate_array[ALL_TARGET_LEGACY_11L], in ar9003_hw_init_txpower_cck()
1846 static void ar9003_hw_init_txpower_ofdm(struct ath_hw *ah, u8 *rate_array, in ar9003_hw_init_txpower_ofdm() argument
1854 ah->tx_power[i] = rate_array[j]; in ar9003_hw_init_txpower_ofdm()
1858 static void ar9003_hw_init_txpower_ht(struct ath_hw *ah, u8 *rate_array, in ar9003_hw_init_txpower_ht() argument
1867 ah->tx_power[i] = rate_array[j]; in ar9003_hw_init_txpower_ht()
1873 ah->tx_power[i] = rate_array[j]; in ar9003_hw_init_txpower_ht()
1879 ah->tx_power[i] = rate_array[j]; in ar9003_hw_init_txpower_ht()
1884 static void ar9003_hw_init_txpower_stbc(struct ath_hw *ah, int ss_offset, in ar9003_hw_init_txpower_stbc() argument
1887 memcpy(&ah->tx_power_stbc[ss_offset], &ah->tx_power[ss_offset], in ar9003_hw_init_txpower_stbc()
1889 memcpy(&ah->tx_power_stbc[ds_offset], &ah->tx_power[ds_offset], in ar9003_hw_init_txpower_stbc()
1891 memcpy(&ah->tx_power_stbc[ts_offset], &ah->tx_power[ts_offset], in ar9003_hw_init_txpower_stbc()
1895 void ar9003_hw_init_rate_txpower(struct ath_hw *ah, u8 *rate_array, in ar9003_hw_init_rate_txpower() argument
1899 ar9003_hw_init_txpower_ofdm(ah, rate_array, in ar9003_hw_init_rate_txpower()
1902 ar9003_hw_init_txpower_ht(ah, rate_array, in ar9003_hw_init_rate_txpower()
1907 ar9003_hw_init_txpower_stbc(ah, in ar9003_hw_init_rate_txpower()
1913 ar9003_hw_init_txpower_cck(ah, rate_array); in ar9003_hw_init_rate_txpower()
1914 ar9003_hw_init_txpower_ofdm(ah, rate_array, in ar9003_hw_init_rate_txpower()
1917 ar9003_hw_init_txpower_ht(ah, rate_array, in ar9003_hw_init_rate_txpower()
1922 ar9003_hw_init_txpower_stbc(ah, in ar9003_hw_init_rate_txpower()
1930 void ar9003_hw_attach_phy_ops(struct ath_hw *ah) in ar9003_hw_attach_phy_ops() argument
1932 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); in ar9003_hw_attach_phy_ops()
1933 struct ath_hw_ops *ops = ath9k_hw_ops(ah); in ar9003_hw_attach_phy_ops()
1946 if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah) || in ar9003_hw_attach_phy_ops()
1947 AR_SREV_9561(ah)) in ar9003_hw_attach_phy_ops()
1979 ar9003_hw_set_nf_limits(ah); in ar9003_hw_attach_phy_ops()
1980 ar9003_hw_set_radar_conf(ah); in ar9003_hw_attach_phy_ops()
1981 memcpy(ah->nf_regs, ar9300_cca_regs, sizeof(ah->nf_regs)); in ar9003_hw_attach_phy_ops()
2010 bool ar9003_hw_bb_watchdog_check(struct ath_hw *ah) in ar9003_hw_bb_watchdog_check() argument
2014 switch(ah->bb_watchdog_last_status) { in ar9003_hw_bb_watchdog_check()
2016 val = REG_READ(ah, AR_PHY_RADAR_0); in ar9003_hw_bb_watchdog_check()
2019 REG_WRITE(ah, AR_PHY_RADAR_0, val); in ar9003_hw_bb_watchdog_check()
2021 val = REG_READ(ah, AR_PHY_RADAR_0); in ar9003_hw_bb_watchdog_check()
2024 REG_WRITE(ah, AR_PHY_RADAR_0, val); in ar9003_hw_bb_watchdog_check()
2033 if (AR_SREV_9340(ah) || AR_SREV_9531(ah) || AR_SREV_9561(ah)) in ar9003_hw_bb_watchdog_check()
2047 void ar9003_hw_bb_watchdog_config(struct ath_hw *ah) in ar9003_hw_bb_watchdog_config() argument
2049 struct ath_common *common = ath9k_hw_common(ah); in ar9003_hw_bb_watchdog_config()
2050 u32 idle_tmo_ms = ah->bb_watchdog_timeout_ms; in ar9003_hw_bb_watchdog_config()
2055 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2, in ar9003_hw_bb_watchdog_config()
2056 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) & in ar9003_hw_bb_watchdog_config()
2061 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1, in ar9003_hw_bb_watchdog_config()
2062 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1) & in ar9003_hw_bb_watchdog_config()
2071 val = REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) & AR_PHY_WATCHDOG_CNTL2_MASK; in ar9003_hw_bb_watchdog_config()
2072 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2, in ar9003_hw_bb_watchdog_config()
2090 if (ah->curchan && IS_CHAN_HT40(ah->curchan)) in ar9003_hw_bb_watchdog_config()
2097 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1, in ar9003_hw_bb_watchdog_config()
2106 void ar9003_hw_bb_watchdog_read(struct ath_hw *ah) in ar9003_hw_bb_watchdog_read() argument
2112 ah->bb_watchdog_last_status = REG_READ(ah, AR_PHY_WATCHDOG_STATUS); in ar9003_hw_bb_watchdog_read()
2118 REG_WRITE(ah, AR_PHY_WATCHDOG_STATUS, in ar9003_hw_bb_watchdog_read()
2119 ah->bb_watchdog_last_status & ~AR_PHY_WATCHDOG_STATUS_CLR); in ar9003_hw_bb_watchdog_read()
2122 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah) in ar9003_hw_bb_watchdog_dbg_info() argument
2124 struct ath_common *common = ath9k_hw_common(ah); in ar9003_hw_bb_watchdog_dbg_info()
2130 status = ah->bb_watchdog_last_status; in ar9003_hw_bb_watchdog_dbg_info()
2146 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1), in ar9003_hw_bb_watchdog_dbg_info()
2147 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2)); in ar9003_hw_bb_watchdog_dbg_info()
2149 REG_READ(ah, AR_PHY_GEN_CTRL)); in ar9003_hw_bb_watchdog_dbg_info()
2161 void ar9003_hw_disable_phy_restart(struct ath_hw *ah) in ar9003_hw_disable_phy_restart() argument
2171 result = MS(ah->bb_watchdog_last_status, AR_PHY_WATCHDOG_RX_OFDM_SM); in ar9003_hw_disable_phy_restart()
2173 if ((result == 0xb) || ah->bb_hang_rx_ofdm) { in ar9003_hw_disable_phy_restart()
2174 ah->bb_hang_rx_ofdm = true; in ar9003_hw_disable_phy_restart()
2175 val = REG_READ(ah, AR_PHY_RESTART); in ar9003_hw_disable_phy_restart()
2177 REG_WRITE(ah, AR_PHY_RESTART, val); in ar9003_hw_disable_phy_restart()