Lines Matching refs:ah
23 static void ath9k_hw_set_sta_powersave(struct ath_hw *ah) in ath9k_hw_set_sta_powersave() argument
25 if (!ath9k_hw_mci_is_enabled(ah)) in ath9k_hw_set_sta_powersave()
31 if (ar9003_mci_state(ah, MCI_STATE_GET_WLAN_PS_STATE) != MCI_PS_DISABLE) in ath9k_hw_set_sta_powersave()
34 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); in ath9k_hw_set_sta_powersave()
37 static void ath9k_hw_set_powermode_wow_sleep(struct ath_hw *ah) in ath9k_hw_set_powermode_wow_sleep() argument
39 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_set_powermode_wow_sleep()
41 ath9k_hw_set_sta_powersave(ah); in ath9k_hw_set_powermode_wow_sleep()
44 REG_WRITE(ah, AR_CR, AR_CR_RXD); in ath9k_hw_set_powermode_wow_sleep()
46 if (!ath9k_hw_wait(ah, AR_CR, AR_CR_RXE, 0, AH_WAIT_TIMEOUT)) { in ath9k_hw_set_powermode_wow_sleep()
48 REG_READ(ah, AR_CR), REG_READ(ah, AR_DIAG_SW)); in ath9k_hw_set_powermode_wow_sleep()
52 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { in ath9k_hw_set_powermode_wow_sleep()
53 if (!REG_READ(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL)) in ath9k_hw_set_powermode_wow_sleep()
54 REG_CLR_BIT(ah, AR_DIRECT_CONNECT, AR_DC_TSF2_ENABLE); in ath9k_hw_set_powermode_wow_sleep()
55 } else if (AR_SREV_9485(ah)){ in ath9k_hw_set_powermode_wow_sleep()
56 if (!(REG_READ(ah, AR_NDP2_TIMER_MODE) & in ath9k_hw_set_powermode_wow_sleep()
58 REG_CLR_BIT(ah, AR_DIRECT_CONNECT, AR_DC_TSF2_ENABLE); in ath9k_hw_set_powermode_wow_sleep()
61 if (ath9k_hw_mci_is_enabled(ah)) in ath9k_hw_set_powermode_wow_sleep()
62 REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2); in ath9k_hw_set_powermode_wow_sleep()
64 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_ON_INT); in ath9k_hw_set_powermode_wow_sleep()
67 static void ath9k_wow_create_keep_alive_pattern(struct ath_hw *ah) in ath9k_wow_create_keep_alive_pattern() argument
69 struct ath_common *common = ath9k_hw_common(ah); in ath9k_wow_create_keep_alive_pattern()
83 ctl[7] = (ah->txchainmask) << 2; in ath9k_wow_create_keep_alive_pattern()
86 if (IS_CHAN_2GHZ(ah->curchan)) in ath9k_wow_create_keep_alive_pattern()
92 REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + i * 4), ctl[i]); in ath9k_wow_create_keep_alive_pattern()
106 if (AR_SREV_9462_20_OR_LATER(ah) || AR_SREV_9565(ah)) { in ath9k_wow_create_keep_alive_pattern()
111 REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + (12 * 4)), 0); in ath9k_wow_create_keep_alive_pattern()
118 REG_WRITE(ah, (wow_ka_data_word0 + i*4), data_word[i]); in ath9k_wow_create_keep_alive_pattern()
121 int ath9k_hw_wow_apply_pattern(struct ath_hw *ah, u8 *user_pattern, in ath9k_hw_wow_apply_pattern() argument
129 if (pattern_count >= ah->wow.max_patterns) in ath9k_hw_wow_apply_pattern()
133 REG_SET_BIT(ah, AR_WOW_PATTERN, BIT(pattern_count)); in ath9k_hw_wow_apply_pattern()
135 REG_SET_BIT(ah, AR_MAC_PCU_WOW4, BIT(pattern_count - 8)); in ath9k_hw_wow_apply_pattern()
139 REG_WRITE(ah, (AR_WOW_TB_PATTERN(pattern_count) + i), in ath9k_hw_wow_apply_pattern()
146 REG_WRITE(ah, (AR_WOW_TB_MASK(pattern_count) + i), mask_val); in ath9k_hw_wow_apply_pattern()
151 ah->wow.wow_event_mask |= in ath9k_hw_wow_apply_pattern()
154 ah->wow.wow_event_mask2 |= in ath9k_hw_wow_apply_pattern()
161 REG_RMW(ah, AR_WOW_LENGTH1, set, clr); in ath9k_hw_wow_apply_pattern()
166 REG_RMW(ah, AR_WOW_LENGTH2, set, clr); in ath9k_hw_wow_apply_pattern()
171 REG_RMW(ah, AR_WOW_LENGTH3, set, clr); in ath9k_hw_wow_apply_pattern()
176 REG_RMW(ah, AR_WOW_LENGTH4, set, clr); in ath9k_hw_wow_apply_pattern()
183 u32 ath9k_hw_wow_wakeup(struct ath_hw *ah) in ath9k_hw_wow_wakeup() argument
192 rval = REG_READ(ah, AR_WOW_PATTERN); in ath9k_hw_wow_wakeup()
200 val &= ah->wow.wow_event_mask; in ath9k_hw_wow_wakeup()
213 rval = REG_READ(ah, AR_MAC_PCU_WOW4); in ath9k_hw_wow_wakeup()
215 val &= ah->wow.wow_event_mask2; in ath9k_hw_wow_wakeup()
229 REG_RMW(ah, AR_PCIE_PM_CTRL, AR_PMCTRL_WOW_PME_CLR, in ath9k_hw_wow_wakeup()
235 REG_WRITE(ah, AR_WOW_PATTERN, in ath9k_hw_wow_wakeup()
236 AR_WOW_CLEAR_EVENTS(REG_READ(ah, AR_WOW_PATTERN))); in ath9k_hw_wow_wakeup()
237 REG_WRITE(ah, AR_MAC_PCU_WOW4, in ath9k_hw_wow_wakeup()
238 AR_WOW_CLEAR_EVENTS2(REG_READ(ah, AR_MAC_PCU_WOW4))); in ath9k_hw_wow_wakeup()
243 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR); in ath9k_hw_wow_wakeup()
252 if (ah->is_pciexpress) in ath9k_hw_wow_wakeup()
253 ath9k_hw_configpcipowersave(ah, false); in ath9k_hw_wow_wakeup()
255 if (AR_SREV_9462(ah) || AR_SREV_9565(ah) || AR_SREV_9485(ah)) { in ath9k_hw_wow_wakeup()
256 u32 dc = REG_READ(ah, AR_DIRECT_CONNECT); in ath9k_hw_wow_wakeup()
259 ath9k_hw_gen_timer_start_tsf2(ah); in ath9k_hw_wow_wakeup()
262 ah->wow.wow_event_mask = 0; in ath9k_hw_wow_wakeup()
263 ah->wow.wow_event_mask2 = 0; in ath9k_hw_wow_wakeup()
269 static void ath9k_hw_wow_set_arwr_reg(struct ath_hw *ah) in ath9k_hw_wow_set_arwr_reg() argument
273 if (!ah->is_pciexpress) in ath9k_hw_wow_set_arwr_reg()
281 wa_reg = REG_READ(ah, AR_WA); in ath9k_hw_wow_set_arwr_reg()
286 REG_WRITE(ah, AR_WA, wa_reg); in ath9k_hw_wow_set_arwr_reg()
289 void ath9k_hw_wow_enable(struct ath_hw *ah, u32 pattern_enable) in ath9k_hw_wow_enable() argument
294 wow_event_mask = ah->wow.wow_event_mask; in ath9k_hw_wow_enable()
312 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PMCTRL_HOST_PME_EN | in ath9k_hw_wow_enable()
316 REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, AR_PMCTRL_WOW_PME_CLR); in ath9k_hw_wow_enable()
326 REG_SET_BIT(ah, AR_WOW_PATTERN, in ath9k_hw_wow_enable()
332 REG_SET_BIT(ah, AR_WOW_COUNT, AR_WOW_AIFS_CNT(AR_WOW_CNT_AIFS_CNT) | in ath9k_hw_wow_enable()
339 REG_WRITE(ah, AR_WOW_BCN_TIMO, AR_WOW_BEACON_TIMO); in ath9k_hw_wow_enable()
341 REG_WRITE(ah, AR_WOW_BCN_TIMO, AR_WOW_BEACON_TIMO_MAX); in ath9k_hw_wow_enable()
347 REG_WRITE(ah, AR_WOW_KEEP_ALIVE_TIMO, AR_WOW_KEEP_ALIVE_NEVER); in ath9k_hw_wow_enable()
349 REG_WRITE(ah, AR_WOW_KEEP_ALIVE_TIMO, KAL_TIMEOUT * 32); in ath9k_hw_wow_enable()
354 REG_WRITE(ah, AR_WOW_KEEP_ALIVE_DELAY, KAL_DELAY * 1000); in ath9k_hw_wow_enable()
359 ath9k_wow_create_keep_alive_pattern(ah); in ath9k_hw_wow_enable()
364 keep_alive = REG_READ(ah, AR_WOW_KEEP_ALIVE); in ath9k_hw_wow_enable()
376 REG_WRITE(ah, AR_WOW_KEEP_ALIVE, keep_alive); in ath9k_hw_wow_enable()
382 REG_RMW_FIELD(ah, AR_RSSI_THR, AR_RSSI_THR_BM_THR, in ath9k_hw_wow_enable()
387 REG_SET_BIT(ah, AR_WOW_BCN_EN, AR_WOW_BEACON_FAIL_EN); in ath9k_hw_wow_enable()
389 REG_CLR_BIT(ah, AR_WOW_BCN_EN, AR_WOW_BEACON_FAIL_EN); in ath9k_hw_wow_enable()
395 magic_pattern = REG_READ(ah, AR_WOW_PATTERN); in ath9k_hw_wow_enable()
405 REG_WRITE(ah, AR_WOW_PATTERN, magic_pattern); in ath9k_hw_wow_enable()
411 REG_WRITE(ah, AR_WOW_PATTERN_MATCH_LT_256B, in ath9k_hw_wow_enable()
417 host_pm_ctrl = REG_READ(ah, AR_PCIE_PM_CTRL); in ath9k_hw_wow_enable()
423 if (AR_SREV_9462(ah)) { in ath9k_hw_wow_enable()
433 REG_WRITE(ah, AR_PCIE_PM_CTRL, host_pm_ctrl); in ath9k_hw_wow_enable()
438 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM); in ath9k_hw_wow_enable()
441 REG_SET_BIT(ah, AR_PCIE_PHY_REG3, BIT(13)); in ath9k_hw_wow_enable()
443 ath9k_hw_wow_set_arwr_reg(ah); in ath9k_hw_wow_enable()
445 if (ath9k_hw_mci_is_enabled(ah)) in ath9k_hw_wow_enable()
446 REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2); in ath9k_hw_wow_enable()
449 REG_CLR_BIT(ah, AR_PCU_MISC_MODE3, BIT(5)); in ath9k_hw_wow_enable()
451 ath9k_hw_set_powermode_wow_sleep(ah); in ath9k_hw_wow_enable()
452 ah->wow.wow_event_mask = wow_event_mask; in ath9k_hw_wow_enable()