Lines Matching refs:REG_WRITE
117 REG_WRITE(ah, INI_RA(array, r, 0), in ath9k_hw_write_array()
330 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); in ath9k_hw_disablepcie()
331 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); in ath9k_hw_disablepcie()
332 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); in ath9k_hw_disablepcie()
333 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824); in ath9k_hw_disablepcie()
334 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579); in ath9k_hw_disablepcie()
335 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000); in ath9k_hw_disablepcie()
336 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); in ath9k_hw_disablepcie()
337 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); in ath9k_hw_disablepcie()
338 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007); in ath9k_hw_disablepcie()
340 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); in ath9k_hw_disablepcie()
367 REG_WRITE(ah, addr, wrData); in ath9k_hw_chip_test()
378 REG_WRITE(ah, addr, wrData); in ath9k_hw_chip_test()
387 REG_WRITE(ah, regAddr[i], regHold[i]); in ath9k_hw_chip_test()
621 REG_WRITE(ah, AR_WA, ah->WARegVal); in __ath9k_hw_init()
718 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa); in ath9k_hw_init_qos()
719 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210); in ath9k_hw_init_qos()
721 REG_WRITE(ah, AR_QOS_NO_ACK, in ath9k_hw_init_qos()
726 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL); in ath9k_hw_init_qos()
727 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF); in ath9k_hw_init_qos()
728 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF); in ath9k_hw_init_qos()
729 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF); in ath9k_hw_init_qos()
730 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); in ath9k_hw_init_qos()
811 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2); in ath9k_hw_init_pll()
817 REG_WRITE(ah, AR_RTC_PLL_CONTROL, in ath9k_hw_init_pll()
822 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2); in ath9k_hw_init_pll()
835 REG_WRITE(ah, AR_RTC_PLL_CONTROL, in ath9k_hw_init_pll()
871 REG_WRITE(ah, AR_PHY_PLL_MODE, regval); in ath9k_hw_init_pll()
874 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) | in ath9k_hw_init_pll()
900 REG_WRITE(ah, AR_PHY_PLL_MODE, regval); in ath9k_hw_init_pll()
903 REG_WRITE(ah, AR_PHY_PLL_MODE, in ath9k_hw_init_pll()
906 REG_WRITE(ah, AR_PHY_PLL_MODE, in ath9k_hw_init_pll()
914 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); in ath9k_hw_init_pll()
923 REG_WRITE(ah, 0x50040, 0x304); in ath9k_hw_init_pll()
928 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); in ath9k_hw_init_pll()
975 REG_WRITE(ah, AR_IMR, imr_reg); in ath9k_hw_init_interrupt_masks()
977 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); in ath9k_hw_init_interrupt_masks()
983 REG_WRITE(ah, AR_INTCFG, msi_cfg); in ath9k_hw_init_interrupt_masks()
990 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF); in ath9k_hw_init_interrupt_masks()
991 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default); in ath9k_hw_init_interrupt_masks()
992 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0); in ath9k_hw_init_interrupt_masks()
998 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0); in ath9k_hw_init_interrupt_masks()
999 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0); in ath9k_hw_init_interrupt_masks()
1000 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0); in ath9k_hw_init_interrupt_masks()
1001 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0); in ath9k_hw_init_interrupt_masks()
1009 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val); in ath9k_hw_set_sifs_time()
1016 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val); in ath9k_hw_setslottime()
1147 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs)); in ath9k_hw_init_global_settings()
1230 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200); in ath9k_hw_set_dma()
1258 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, txbuf_size); in ath9k_hw_set_dma()
1344 REG_WRITE(ah, AR_RTC_RESET, 1); in ath9k_hw_ar9330_reset_war()
1364 REG_WRITE(ah, AR_WA, ah->WARegVal); in ath9k_hw_set_reset()
1368 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | in ath9k_hw_set_reset()
1384 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); in ath9k_hw_set_reset()
1389 REG_WRITE(ah, AR_RC, val); in ath9k_hw_set_reset()
1392 REG_WRITE(ah, AR_RC, AR_RC_AHB); in ath9k_hw_set_reset()
1417 REG_WRITE(ah, AR_RTC_RC, rst_flags); in ath9k_hw_set_reset()
1428 REG_WRITE(ah, AR_RTC_RC, 0); in ath9k_hw_set_reset()
1435 REG_WRITE(ah, AR_RC, 0); in ath9k_hw_set_reset()
1448 REG_WRITE(ah, AR_WA, ah->WARegVal); in ath9k_hw_set_reset_power_on()
1452 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | in ath9k_hw_set_reset_power_on()
1456 REG_WRITE(ah, AR_RC, AR_RC_AHB); in ath9k_hw_set_reset_power_on()
1458 REG_WRITE(ah, AR_RTC_RESET, 0); in ath9k_hw_set_reset_power_on()
1465 REG_WRITE(ah, AR_RC, 0); in ath9k_hw_set_reset_power_on()
1467 REG_WRITE(ah, AR_RTC_RESET, 1); in ath9k_hw_set_reset_power_on()
1486 REG_WRITE(ah, AR_WA, ah->WARegVal); in ath9k_hw_set_reset_reg()
1490 REG_WRITE(ah, AR_RTC_FORCE_WAKE, in ath9k_hw_set_reset_reg()
1635 REG_WRITE(ah, AR_NAV, 0); in ath9k_hw_check_nav()
1719 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); in ath9k_hw_reset_opmode()
1721 REG_WRITE(ah, AR_ISR, ~0); in ath9k_hw_reset_opmode()
1722 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR); in ath9k_hw_reset_opmode()
1736 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); in ath9k_hw_init_queues()
1760 REG_WRITE(ah, AR_CFG, mask); in ath9k_hw_init_desc()
1768 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB); in ath9k_hw_init_desc()
1770 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); in ath9k_hw_init_desc()
1778 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); in ath9k_hw_init_desc()
1933 REG_WRITE(ah, in ath9k_hw_reset()
1947 REG_WRITE(ah, in ath9k_hw_reset()
2020 REG_WRITE(ah, AR_OBS, 8); in ath9k_hw_reset()
2049 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ); in ath9k_hw_reset()
2106 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0); in ath9k_set_power_sleep()
2120 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); in ath9k_set_power_sleep()
2130 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); in ath9k_set_power_sleep()
2146 REG_WRITE(ah, AR_RTC_FORCE_WAKE, in ath9k_set_power_network_sleep()
2174 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); in ath9k_set_power_network_sleep()
2184 REG_WRITE(ah, AR_WA, ah->WARegVal); in ath9k_hw_set_power_awake()
2297 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon); in ath9k_hw_beaconinit()
2298 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon - in ath9k_hw_beaconinit()
2300 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon - in ath9k_hw_beaconinit()
2311 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period); in ath9k_hw_beaconinit()
2312 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period); in ath9k_hw_beaconinit()
2313 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period); in ath9k_hw_beaconinit()
2330 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, bs->bs_nexttbtt); in ath9k_hw_set_sta_beacon_timers()
2331 REG_WRITE(ah, AR_BEACON_PERIOD, bs->bs_intval); in ath9k_hw_set_sta_beacon_timers()
2332 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, bs->bs_intval); in ath9k_hw_set_sta_beacon_timers()
2360 REG_WRITE(ah, AR_NEXT_DTIM, bs->bs_nextdtim - SLEEP_SLOP); in ath9k_hw_set_sta_beacon_timers()
2361 REG_WRITE(ah, AR_NEXT_TIM, nextTbtt - SLEEP_SLOP); in ath9k_hw_set_sta_beacon_timers()
2363 REG_WRITE(ah, AR_SLEEP1, in ath9k_hw_set_sta_beacon_timers()
2372 REG_WRITE(ah, AR_SLEEP2, in ath9k_hw_set_sta_beacon_timers()
2375 REG_WRITE(ah, AR_TIM_PERIOD, beaconintval); in ath9k_hw_set_sta_beacon_timers()
2376 REG_WRITE(ah, AR_DTIM_PERIOD, dtimperiod); in ath9k_hw_set_sta_beacon_timers()
2385 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold); in ath9k_hw_set_sta_beacon_timers()
2721 REG_WRITE(ah, addr, tmp); in ath9k_hw_gpio_cfg_output_mux()
2869 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); in ath9k_hw_setantenna()
2897 REG_WRITE(ah, AR_RX_FILTER, bits); in ath9k_hw_setrxfilter()
2904 REG_WRITE(ah, AR_PHY_ERR, phybits); in ath9k_hw_setrxfilter()
3001 REG_WRITE(ah, AR_MCAST_FIL0, filter0); in ath9k_hw_setmcastfilter()
3002 REG_WRITE(ah, AR_MCAST_FIL1, filter1); in ath9k_hw_setmcastfilter()
3010 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid)); in ath9k_hw_write_associd()
3011 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) | in ath9k_hw_write_associd()
3040 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff); in ath9k_hw_settsf64()
3041 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff); in ath9k_hw_settsf64()
3052 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); in ath9k_hw_reset_tsf()
3074 REG_WRITE(ah, AR_2040_MODE, macmode); in ath9k_hw_set11nmac2040()
3174 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr, in ath9k_hw_gen_timer_start()
3176 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr, in ath9k_hw_gen_timer_start()