Lines Matching refs:ah
21 static void ath9k_hw_set_txq_interrupts(struct ath_hw *ah, in ath9k_hw_set_txq_interrupts() argument
24 ath_dbg(ath9k_hw_common(ah), INTERRUPT, in ath9k_hw_set_txq_interrupts()
26 ah->txok_interrupt_mask, ah->txerr_interrupt_mask, in ath9k_hw_set_txq_interrupts()
27 ah->txdesc_interrupt_mask, ah->txeol_interrupt_mask, in ath9k_hw_set_txq_interrupts()
28 ah->txurn_interrupt_mask); in ath9k_hw_set_txq_interrupts()
30 ENABLE_REGWRITE_BUFFER(ah); in ath9k_hw_set_txq_interrupts()
32 REG_WRITE(ah, AR_IMR_S0, in ath9k_hw_set_txq_interrupts()
33 SM(ah->txok_interrupt_mask, AR_IMR_S0_QCU_TXOK) in ath9k_hw_set_txq_interrupts()
34 | SM(ah->txdesc_interrupt_mask, AR_IMR_S0_QCU_TXDESC)); in ath9k_hw_set_txq_interrupts()
35 REG_WRITE(ah, AR_IMR_S1, in ath9k_hw_set_txq_interrupts()
36 SM(ah->txerr_interrupt_mask, AR_IMR_S1_QCU_TXERR) in ath9k_hw_set_txq_interrupts()
37 | SM(ah->txeol_interrupt_mask, AR_IMR_S1_QCU_TXEOL)); in ath9k_hw_set_txq_interrupts()
39 ah->imrs2_reg &= ~AR_IMR_S2_QCU_TXURN; in ath9k_hw_set_txq_interrupts()
40 ah->imrs2_reg |= (ah->txurn_interrupt_mask & AR_IMR_S2_QCU_TXURN); in ath9k_hw_set_txq_interrupts()
41 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); in ath9k_hw_set_txq_interrupts()
43 REGWRITE_BUFFER_FLUSH(ah); in ath9k_hw_set_txq_interrupts()
46 u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q) in ath9k_hw_gettxbuf() argument
48 return REG_READ(ah, AR_QTXDP(q)); in ath9k_hw_gettxbuf()
52 void ath9k_hw_puttxbuf(struct ath_hw *ah, u32 q, u32 txdp) in ath9k_hw_puttxbuf() argument
54 REG_WRITE(ah, AR_QTXDP(q), txdp); in ath9k_hw_puttxbuf()
58 void ath9k_hw_txstart(struct ath_hw *ah, u32 q) in ath9k_hw_txstart() argument
60 ath_dbg(ath9k_hw_common(ah), QUEUE, "Enable TXE on queue: %u\n", q); in ath9k_hw_txstart()
61 REG_WRITE(ah, AR_Q_TXE, 1 << q); in ath9k_hw_txstart()
65 u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q) in ath9k_hw_numtxpending() argument
69 npend = REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT; in ath9k_hw_numtxpending()
72 if (REG_READ(ah, AR_Q_TXE) & (1 << q)) in ath9k_hw_numtxpending()
105 bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel) in ath9k_hw_updatetxtriglevel() argument
109 if (ah->tx_trig_level >= ah->config.max_txtrig_level) in ath9k_hw_updatetxtriglevel()
112 ath9k_hw_disable_interrupts(ah); in ath9k_hw_updatetxtriglevel()
114 txcfg = REG_READ(ah, AR_TXCFG); in ath9k_hw_updatetxtriglevel()
118 if (curLevel < ah->config.max_txtrig_level) in ath9k_hw_updatetxtriglevel()
123 REG_WRITE(ah, AR_TXCFG, in ath9k_hw_updatetxtriglevel()
126 ath9k_hw_enable_interrupts(ah); in ath9k_hw_updatetxtriglevel()
128 ah->tx_trig_level = newLevel; in ath9k_hw_updatetxtriglevel()
134 void ath9k_hw_abort_tx_dma(struct ath_hw *ah) in ath9k_hw_abort_tx_dma() argument
139 if (ah->curchan) { in ath9k_hw_abort_tx_dma()
140 if (IS_CHAN_HALF_RATE(ah->curchan)) in ath9k_hw_abort_tx_dma()
142 else if (IS_CHAN_QUARTER_RATE(ah->curchan)) in ath9k_hw_abort_tx_dma()
146 REG_WRITE(ah, AR_Q_TXD, AR_Q_TXD_M); in ath9k_hw_abort_tx_dma()
148 REG_SET_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF); in ath9k_hw_abort_tx_dma()
149 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); in ath9k_hw_abort_tx_dma()
150 REG_SET_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF); in ath9k_hw_abort_tx_dma()
157 if (!ath9k_hw_numtxpending(ah, q)) in ath9k_hw_abort_tx_dma()
162 REG_CLR_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF); in ath9k_hw_abort_tx_dma()
163 REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); in ath9k_hw_abort_tx_dma()
164 REG_CLR_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF); in ath9k_hw_abort_tx_dma()
166 REG_WRITE(ah, AR_Q_TXD, 0); in ath9k_hw_abort_tx_dma()
170 bool ath9k_hw_stop_dma_queue(struct ath_hw *ah, u32 q) in ath9k_hw_stop_dma_queue() argument
177 REG_WRITE(ah, AR_Q_TXD, 1 << q); in ath9k_hw_stop_dma_queue()
183 if (ath9k_hw_numtxpending(ah, q) == 0) in ath9k_hw_stop_dma_queue()
187 REG_WRITE(ah, AR_Q_TXD, 0); in ath9k_hw_stop_dma_queue()
196 bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q, in ath9k_hw_set_txq_props() argument
200 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_set_txq_props()
203 qi = &ah->txq[q]; in ath9k_hw_set_txq_props()
261 bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q, in ath9k_hw_get_txq_props() argument
264 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_get_txq_props()
267 qi = &ah->txq[q]; in ath9k_hw_get_txq_props()
293 int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type, in ath9k_hw_setuptxqueue() argument
296 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_setuptxqueue()
323 qi = &ah->txq[q]; in ath9k_hw_setuptxqueue()
331 (void) ath9k_hw_set_txq_props(ah, q, qinfo); in ath9k_hw_setuptxqueue()
337 static void ath9k_hw_clear_queue_interrupts(struct ath_hw *ah, u32 q) in ath9k_hw_clear_queue_interrupts() argument
339 ah->txok_interrupt_mask &= ~(1 << q); in ath9k_hw_clear_queue_interrupts()
340 ah->txerr_interrupt_mask &= ~(1 << q); in ath9k_hw_clear_queue_interrupts()
341 ah->txdesc_interrupt_mask &= ~(1 << q); in ath9k_hw_clear_queue_interrupts()
342 ah->txeol_interrupt_mask &= ~(1 << q); in ath9k_hw_clear_queue_interrupts()
343 ah->txurn_interrupt_mask &= ~(1 << q); in ath9k_hw_clear_queue_interrupts()
346 bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q) in ath9k_hw_releasetxqueue() argument
348 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_releasetxqueue()
351 qi = &ah->txq[q]; in ath9k_hw_releasetxqueue()
360 ath9k_hw_clear_queue_interrupts(ah, q); in ath9k_hw_releasetxqueue()
361 ath9k_hw_set_txq_interrupts(ah, qi); in ath9k_hw_releasetxqueue()
367 bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q) in ath9k_hw_resettxqueue() argument
369 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_resettxqueue()
373 qi = &ah->txq[q]; in ath9k_hw_resettxqueue()
388 ENABLE_REGWRITE_BUFFER(ah); in ath9k_hw_resettxqueue()
390 REG_WRITE(ah, AR_DLCL_IFS(q), in ath9k_hw_resettxqueue()
395 REG_WRITE(ah, AR_DRETRY_LIMIT(q), in ath9k_hw_resettxqueue()
400 REG_WRITE(ah, AR_QMISC(q), AR_Q_MISC_DCU_EARLY_TERM_REQ); in ath9k_hw_resettxqueue()
402 if (AR_SREV_9340(ah) && !AR_SREV_9340_13_OR_LATER(ah)) in ath9k_hw_resettxqueue()
403 REG_WRITE(ah, AR_DMISC(q), in ath9k_hw_resettxqueue()
406 REG_WRITE(ah, AR_DMISC(q), in ath9k_hw_resettxqueue()
410 REG_WRITE(ah, AR_QCBRCFG(q), in ath9k_hw_resettxqueue()
413 REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_FSP_CBR | in ath9k_hw_resettxqueue()
418 REG_WRITE(ah, AR_QRDYTIMECFG(q), in ath9k_hw_resettxqueue()
423 REG_WRITE(ah, AR_DCHNTIME(q), in ath9k_hw_resettxqueue()
429 REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_RDYTIME_EXP_POLICY); in ath9k_hw_resettxqueue()
432 REG_SET_BIT(ah, AR_DMISC(q), AR_D_MISC_POST_FR_BKOFF_DIS); in ath9k_hw_resettxqueue()
434 REGWRITE_BUFFER_FLUSH(ah); in ath9k_hw_resettxqueue()
437 REG_SET_BIT(ah, AR_DMISC(q), AR_D_MISC_FRAG_BKOFF_EN); in ath9k_hw_resettxqueue()
441 ENABLE_REGWRITE_BUFFER(ah); in ath9k_hw_resettxqueue()
443 REG_SET_BIT(ah, AR_QMISC(q), in ath9k_hw_resettxqueue()
448 REG_SET_BIT(ah, AR_DMISC(q), in ath9k_hw_resettxqueue()
454 REGWRITE_BUFFER_FLUSH(ah); in ath9k_hw_resettxqueue()
461 if (AR_SREV_9300_20_OR_LATER(ah) && in ath9k_hw_resettxqueue()
462 ah->opmode != NL80211_IFTYPE_ADHOC) { in ath9k_hw_resettxqueue()
463 REG_WRITE(ah, AR_DLCL_IFS(q), SM(0, AR_D_LCL_IFS_CWMIN) in ath9k_hw_resettxqueue()
469 ENABLE_REGWRITE_BUFFER(ah); in ath9k_hw_resettxqueue()
471 REG_SET_BIT(ah, AR_QMISC(q), in ath9k_hw_resettxqueue()
476 (ah->config.sw_beacon_response_time - in ath9k_hw_resettxqueue()
477 ah->config.dma_beacon_response_time)) * 1024; in ath9k_hw_resettxqueue()
478 REG_WRITE(ah, AR_QRDYTIMECFG(q), in ath9k_hw_resettxqueue()
480 REG_SET_BIT(ah, AR_DMISC(q), in ath9k_hw_resettxqueue()
484 REGWRITE_BUFFER_FLUSH(ah); in ath9k_hw_resettxqueue()
488 REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_CBR_INCR_DIS1); in ath9k_hw_resettxqueue()
491 REG_SET_BIT(ah, AR_DMISC(q), AR_D_MISC_POST_FR_BKOFF_DIS); in ath9k_hw_resettxqueue()
498 REG_SET_BIT(ah, AR_DMISC(q), in ath9k_hw_resettxqueue()
504 if (AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_resettxqueue()
505 REG_WRITE(ah, AR_Q_DESC_CRCCHK, AR_Q_DESC_CRCCHK_EN); in ath9k_hw_resettxqueue()
507 ath9k_hw_clear_queue_interrupts(ah, q); in ath9k_hw_resettxqueue()
509 ah->txok_interrupt_mask |= 1 << q; in ath9k_hw_resettxqueue()
510 ah->txerr_interrupt_mask |= 1 << q; in ath9k_hw_resettxqueue()
513 ah->txdesc_interrupt_mask |= 1 << q; in ath9k_hw_resettxqueue()
515 ah->txeol_interrupt_mask |= 1 << q; in ath9k_hw_resettxqueue()
517 ah->txurn_interrupt_mask |= 1 << q; in ath9k_hw_resettxqueue()
518 ath9k_hw_set_txq_interrupts(ah, qi); in ath9k_hw_resettxqueue()
524 int ath9k_hw_rxprocdesc(struct ath_hw *ah, struct ath_desc *ds, in ath9k_hw_rxprocdesc() argument
585 if (AR_SREV_9280_20_OR_LATER(ah)) in ath9k_hw_rxprocdesc()
639 bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set) in ath9k_hw_setrxabort() argument
644 REG_SET_BIT(ah, AR_DIAG_SW, in ath9k_hw_setrxabort()
647 if (!ath9k_hw_wait(ah, AR_OBS_BUS_1, AR_OBS_BUS_1_RX_STATE, in ath9k_hw_setrxabort()
649 REG_CLR_BIT(ah, AR_DIAG_SW, in ath9k_hw_setrxabort()
653 reg = REG_READ(ah, AR_OBS_BUS_1); in ath9k_hw_setrxabort()
654 ath_err(ath9k_hw_common(ah), in ath9k_hw_setrxabort()
661 REG_CLR_BIT(ah, AR_DIAG_SW, in ath9k_hw_setrxabort()
669 void ath9k_hw_putrxbuf(struct ath_hw *ah, u32 rxdp) in ath9k_hw_putrxbuf() argument
671 REG_WRITE(ah, AR_RXDP, rxdp); in ath9k_hw_putrxbuf()
675 void ath9k_hw_startpcureceive(struct ath_hw *ah, bool is_scanning) in ath9k_hw_startpcureceive() argument
677 ath9k_enable_mib_counters(ah); in ath9k_hw_startpcureceive()
679 ath9k_ani_reset(ah, is_scanning); in ath9k_hw_startpcureceive()
681 REG_CLR_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); in ath9k_hw_startpcureceive()
685 void ath9k_hw_abortpcurecv(struct ath_hw *ah) in ath9k_hw_abortpcurecv() argument
687 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_ABORT | AR_DIAG_RX_DIS); in ath9k_hw_abortpcurecv()
689 ath9k_hw_disable_mib_counters(ah); in ath9k_hw_abortpcurecv()
693 bool ath9k_hw_stopdmarecv(struct ath_hw *ah, bool *reset) in ath9k_hw_stopdmarecv() argument
696 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_stopdmarecv()
701 REG_WRITE(ah, AR_MACMISC, in ath9k_hw_stopdmarecv()
706 REG_WRITE(ah, AR_CR, AR_CR_RXD); in ath9k_hw_stopdmarecv()
710 if ((REG_READ(ah, AR_CR) & AR_CR_RXE) == 0) in ath9k_hw_stopdmarecv()
713 if (!AR_SREV_9300_20_OR_LATER(ah)) { in ath9k_hw_stopdmarecv()
714 mac_status = REG_READ(ah, AR_DMADBG_7) & 0x7f0; in ath9k_hw_stopdmarecv()
730 REG_READ(ah, AR_CR), in ath9k_hw_stopdmarecv()
731 REG_READ(ah, AR_DIAG_SW), in ath9k_hw_stopdmarecv()
732 REG_READ(ah, AR_DMADBG_7)); in ath9k_hw_stopdmarecv()
742 int ath9k_hw_beaconq_setup(struct ath_hw *ah) in ath9k_hw_beaconq_setup() argument
751 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) in ath9k_hw_beaconq_setup()
754 return ath9k_hw_setuptxqueue(ah, ATH9K_TX_QUEUE_BEACON, &qi); in ath9k_hw_beaconq_setup()
758 bool ath9k_hw_intrpend(struct ath_hw *ah) in ath9k_hw_intrpend() argument
762 if (AR_SREV_9100(ah)) in ath9k_hw_intrpend()
765 host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE); in ath9k_hw_intrpend()
772 host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE); in ath9k_hw_intrpend()
781 void ath9k_hw_kill_interrupts(struct ath_hw *ah) in ath9k_hw_kill_interrupts() argument
783 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_kill_interrupts()
786 REG_WRITE(ah, AR_IER, AR_IER_DISABLE); in ath9k_hw_kill_interrupts()
787 (void) REG_READ(ah, AR_IER); in ath9k_hw_kill_interrupts()
788 if (!AR_SREV_9100(ah)) { in ath9k_hw_kill_interrupts()
789 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0); in ath9k_hw_kill_interrupts()
790 (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE); in ath9k_hw_kill_interrupts()
792 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); in ath9k_hw_kill_interrupts()
793 (void) REG_READ(ah, AR_INTR_SYNC_ENABLE); in ath9k_hw_kill_interrupts()
798 void ath9k_hw_disable_interrupts(struct ath_hw *ah) in ath9k_hw_disable_interrupts() argument
800 if (!(ah->imask & ATH9K_INT_GLOBAL)) in ath9k_hw_disable_interrupts()
801 atomic_set(&ah->intr_ref_cnt, -1); in ath9k_hw_disable_interrupts()
803 atomic_dec(&ah->intr_ref_cnt); in ath9k_hw_disable_interrupts()
805 ath9k_hw_kill_interrupts(ah); in ath9k_hw_disable_interrupts()
809 static void __ath9k_hw_enable_interrupts(struct ath_hw *ah) in __ath9k_hw_enable_interrupts() argument
811 struct ath_common *common = ath9k_hw_common(ah); in __ath9k_hw_enable_interrupts()
815 if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah) || in __ath9k_hw_enable_interrupts()
816 AR_SREV_9561(ah)) in __ath9k_hw_enable_interrupts()
821 if (ah->imask & ATH9K_INT_MCI) in __ath9k_hw_enable_interrupts()
825 REG_WRITE(ah, AR_IER, AR_IER_ENABLE); in __ath9k_hw_enable_interrupts()
826 if (!AR_SREV_9100(ah)) { in __ath9k_hw_enable_interrupts()
827 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, async_mask); in __ath9k_hw_enable_interrupts()
828 REG_WRITE(ah, AR_INTR_ASYNC_MASK, async_mask); in __ath9k_hw_enable_interrupts()
830 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default); in __ath9k_hw_enable_interrupts()
831 REG_WRITE(ah, AR_INTR_SYNC_MASK, sync_default); in __ath9k_hw_enable_interrupts()
834 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER)); in __ath9k_hw_enable_interrupts()
836 if (ah->msi_enabled) { in __ath9k_hw_enable_interrupts()
841 ath_dbg(ath9k_hw_common(ah), INTERRUPT, in __ath9k_hw_enable_interrupts()
842 "Enabling MSI, msi_mask=0x%X\n", ah->msi_mask); in __ath9k_hw_enable_interrupts()
844 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, ah->msi_mask); in __ath9k_hw_enable_interrupts()
845 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, ah->msi_mask); in __ath9k_hw_enable_interrupts()
846 ath_dbg(ath9k_hw_common(ah), INTERRUPT, in __ath9k_hw_enable_interrupts()
848 REG_READ(ah, AR_INTR_PRIO_ASYNC_ENABLE), in __ath9k_hw_enable_interrupts()
849 REG_READ(ah, AR_INTR_PRIO_ASYNC_MASK)); in __ath9k_hw_enable_interrupts()
851 if (ah->msi_reg == 0) in __ath9k_hw_enable_interrupts()
852 ah->msi_reg = REG_READ(ah, AR_PCIE_MSI); in __ath9k_hw_enable_interrupts()
854 ath_dbg(ath9k_hw_common(ah), INTERRUPT, in __ath9k_hw_enable_interrupts()
856 AR_PCIE_MSI, ah->msi_reg); in __ath9k_hw_enable_interrupts()
860 REG_WRITE(ah, AR_PCIE_MSI, in __ath9k_hw_enable_interrupts()
861 (ah->msi_reg | AR_PCIE_MSI_ENABLE) in __ath9k_hw_enable_interrupts()
863 _msi_reg = REG_READ(ah, AR_PCIE_MSI); in __ath9k_hw_enable_interrupts()
868 ath_err(ath9k_hw_common(ah), in __ath9k_hw_enable_interrupts()
874 void ath9k_hw_resume_interrupts(struct ath_hw *ah) in ath9k_hw_resume_interrupts() argument
876 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_resume_interrupts()
878 if (!(ah->imask & ATH9K_INT_GLOBAL)) in ath9k_hw_resume_interrupts()
881 if (atomic_read(&ah->intr_ref_cnt) != 0) { in ath9k_hw_resume_interrupts()
883 atomic_read(&ah->intr_ref_cnt)); in ath9k_hw_resume_interrupts()
887 __ath9k_hw_enable_interrupts(ah); in ath9k_hw_resume_interrupts()
891 void ath9k_hw_enable_interrupts(struct ath_hw *ah) in ath9k_hw_enable_interrupts() argument
893 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_enable_interrupts()
895 if (!(ah->imask & ATH9K_INT_GLOBAL)) in ath9k_hw_enable_interrupts()
898 if (!atomic_inc_and_test(&ah->intr_ref_cnt)) { in ath9k_hw_enable_interrupts()
900 atomic_read(&ah->intr_ref_cnt)); in ath9k_hw_enable_interrupts()
904 __ath9k_hw_enable_interrupts(ah); in ath9k_hw_enable_interrupts()
908 void ath9k_hw_set_interrupts(struct ath_hw *ah) in ath9k_hw_set_interrupts() argument
910 enum ath9k_int ints = ah->imask; in ath9k_hw_set_interrupts()
912 struct ath9k_hw_capabilities *pCap = &ah->caps; in ath9k_hw_set_interrupts()
913 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_set_interrupts()
916 ath9k_hw_disable_interrupts(ah); in ath9k_hw_set_interrupts()
918 if (ah->msi_enabled) { in ath9k_hw_set_interrupts()
921 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0); in ath9k_hw_set_interrupts()
922 REG_READ(ah, AR_INTR_PRIO_ASYNC_ENABLE); in ath9k_hw_set_interrupts()
930 ah->msi_mask = 0; in ath9k_hw_set_interrupts()
932 ah->msi_mask |= AR_INTR_PRIO_TX; in ath9k_hw_set_interrupts()
933 if (ah->config.tx_intr_mitigation) in ath9k_hw_set_interrupts()
936 if (ah->txok_interrupt_mask) in ath9k_hw_set_interrupts()
938 if (ah->txdesc_interrupt_mask) in ath9k_hw_set_interrupts()
941 if (ah->txerr_interrupt_mask) in ath9k_hw_set_interrupts()
943 if (ah->txeol_interrupt_mask) in ath9k_hw_set_interrupts()
947 ah->msi_mask |= AR_INTR_PRIO_RXLP | AR_INTR_PRIO_RXHP; in ath9k_hw_set_interrupts()
948 if (AR_SREV_9300_20_OR_LATER(ah)) { in ath9k_hw_set_interrupts()
950 if (ah->config.rx_intr_mitigation) { in ath9k_hw_set_interrupts()
957 if (ah->config.rx_intr_mitigation) in ath9k_hw_set_interrupts()
991 if (ah->config.hw_hang_checks & HW_BB_WATCHDOG) { in ath9k_hw_set_interrupts()
999 REG_WRITE(ah, AR_IMR, mask); in ath9k_hw_set_interrupts()
1000 ah->imrs2_reg &= ~(AR_IMR_S2_TIM | in ath9k_hw_set_interrupts()
1009 if (ah->config.hw_hang_checks & HW_BB_WATCHDOG) { in ath9k_hw_set_interrupts()
1011 ah->imrs2_reg &= ~AR_IMR_S2_BB_WATCHDOG; in ath9k_hw_set_interrupts()
1014 ah->imrs2_reg |= mask2; in ath9k_hw_set_interrupts()
1015 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); in ath9k_hw_set_interrupts()
1019 REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER); in ath9k_hw_set_interrupts()
1021 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER); in ath9k_hw_set_interrupts()
1031 void ath9k_hw_set_tx_filter(struct ath_hw *ah, u8 destidx, bool set) in ath9k_hw_set_tx_filter() argument
1042 ath_dbg(ath9k_hw_common(ah), PS, in ath9k_hw_set_tx_filter()
1045 REG_WRITE(ah, AR_D_TXBLK_BASE, filter); in ath9k_hw_set_tx_filter()