Lines Matching refs:cpu_to_le32
381 #define UCODE_VALID_OK cpu_to_le32(0x1)
568 #define RXON_FLG_BAND_24G_MSK cpu_to_le32(1 << 0)
569 #define RXON_FLG_CCK_MSK cpu_to_le32(1 << 1)
571 #define RXON_FLG_AUTO_DETECT_MSK cpu_to_le32(1 << 2)
573 #define RXON_FLG_TGG_PROTECT_MSK cpu_to_le32(1 << 3)
575 #define RXON_FLG_SHORT_SLOT_MSK cpu_to_le32(1 << 4)
576 #define RXON_FLG_SHORT_PREAMBLE_MSK cpu_to_le32(1 << 5)
578 #define RXON_FLG_DIS_DIV_MSK cpu_to_le32(1 << 7)
579 #define RXON_FLG_ANT_SEL_MSK cpu_to_le32(0x0f00)
580 #define RXON_FLG_ANT_A_MSK cpu_to_le32(1 << 8)
581 #define RXON_FLG_ANT_B_MSK cpu_to_le32(1 << 9)
583 #define RXON_FLG_RADAR_DETECT_MSK cpu_to_le32(1 << 12)
584 #define RXON_FLG_TGJ_NARROW_BAND_MSK cpu_to_le32(1 << 13)
587 #define RXON_FLG_TSF2HOST_MSK cpu_to_le32(1 << 15)
591 #define RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK cpu_to_le32(0x1 << 22)
595 #define RXON_FLG_HT_PROT_MSK cpu_to_le32(0x1 << 23)
596 #define RXON_FLG_HT40_PROT_MSK cpu_to_le32(0x2 << 23)
599 #define RXON_FLG_CHANNEL_MODE_MSK cpu_to_le32(0x3 << 25)
609 cpu_to_le32(CHANNEL_MODE_LEGACY << RXON_FLG_CHANNEL_MODE_POS)
611 cpu_to_le32(CHANNEL_MODE_PURE_40 << RXON_FLG_CHANNEL_MODE_POS)
613 cpu_to_le32(CHANNEL_MODE_MIXED << RXON_FLG_CHANNEL_MODE_POS)
616 #define RXON_FLG_SELF_CTS_EN cpu_to_le32(0x1<<30)
620 #define RXON_FILTER_PROMISC_MSK cpu_to_le32(1 << 0)
622 #define RXON_FILTER_CTL2HOST_MSK cpu_to_le32(1 << 1)
624 #define RXON_FILTER_ACCEPT_GRP_MSK cpu_to_le32(1 << 2)
626 #define RXON_FILTER_DIS_DECRYPT_MSK cpu_to_le32(1 << 3)
628 #define RXON_FILTER_DIS_GRP_DECRYPT_MSK cpu_to_le32(1 << 4)
630 #define RXON_FILTER_ASSOC_MSK cpu_to_le32(1 << 5)
632 #define RXON_FILTER_BCON_AWARE_MSK cpu_to_le32(1 << 6)
818 #define QOS_PARAM_FLG_UPDATE_EDCA_MSK cpu_to_le32(0x01)
819 #define QOS_PARAM_FLG_TGN_MSK cpu_to_le32(0x02)
820 #define QOS_PARAM_FLG_TXOP_TYPE_MSK cpu_to_le32(0x10)
856 #define STA_FLG_TX_RATE_MSK cpu_to_le32(1 << 2)
857 #define STA_FLG_PWR_SAVE_MSK cpu_to_le32(1 << 8)
858 #define STA_FLG_RTS_MIMO_PROT_MSK cpu_to_le32(1 << 17)
859 #define STA_FLG_AGG_MPDU_8US_MSK cpu_to_le32(1 << 18)
861 #define STA_FLG_MAX_AGG_SIZE_MSK cpu_to_le32(3 << 19)
862 #define STA_FLG_HT40_EN_MSK cpu_to_le32(1 << 21)
863 #define STA_FLG_MIMO_DIS_MSK cpu_to_le32(1 << 22)
865 #define STA_FLG_AGG_MPDU_DENSITY_MSK cpu_to_le32(7 << 23)
1088 #define IL_TX_FIFO_BK_MSK cpu_to_le32(BIT(0))
1089 #define IL_TX_FIFO_BE_MSK cpu_to_le32(BIT(1))
1090 #define IL_TX_FIFO_VI_MSK cpu_to_le32(BIT(2))
1091 #define IL_TX_FIFO_VO_MSK cpu_to_le32(BIT(3))
1092 #define IL_AGG_TX_QUEUE_MSK cpu_to_le32(0xffc00)
1130 #define RX_RES_STATUS_NO_CRC32_ERROR cpu_to_le32(1 << 0)
1131 #define RX_RES_STATUS_NO_RXE_OVERFLOW cpu_to_le32(1 << 1)
1272 #define TX_CMD_FLG_RTS_MSK cpu_to_le32(1 << 1)
1279 #define TX_CMD_FLG_CTS_MSK cpu_to_le32(1 << 2)
1284 #define TX_CMD_FLG_ACK_MSK cpu_to_le32(1 << 3)
1292 #define TX_CMD_FLG_STA_RATE_MSK cpu_to_le32(1 << 4)
1296 #define TX_CMD_FLG_IMM_BA_RSP_MASK cpu_to_le32(1 << 6)
1302 #define TX_CMD_FLG_FULL_TXOP_PROT_MSK cpu_to_le32(1 << 7)
1306 #define TX_CMD_FLG_ANT_SEL_MSK cpu_to_le32(0xf00)
1307 #define TX_CMD_FLG_ANT_A_MSK cpu_to_le32(1 << 8)
1308 #define TX_CMD_FLG_ANT_B_MSK cpu_to_le32(1 << 9)
1314 #define TX_CMD_FLG_SEQ_CTL_MSK cpu_to_le32(1 << 13)
1318 #define TX_CMD_FLG_MORE_FRAG_MSK cpu_to_le32(1 << 14)
1323 #define TX_CMD_FLG_TSF_MSK cpu_to_le32(1 << 16)
1331 #define TX_CMD_FLG_MH_PAD_MSK cpu_to_le32(1 << 20)
1335 #define TX_CMD_FLG_AGG_CCMP_MSK cpu_to_le32(1 << 22)
1338 #define TX_CMD_FLG_DUR_MSK cpu_to_le32(1 << 25)
2349 #define SCAN_CHANNEL_TYPE_PASSIVE cpu_to_le32(0)
2350 #define SCAN_CHANNEL_TYPE_ACTIVE cpu_to_le32(1)
2406 #define IL_SCAN_PROBE_MASK(n) cpu_to_le32((BIT(n) | (BIT(n) - BIT(1))))
2424 #define TX_CMD_LIFE_TIME_INFINITE cpu_to_le32(0xFFFFFFFF)
2573 #define CAN_ABORT_STATUS cpu_to_le32(0x1)
2815 #define INTERFERENCE_DATA_AVAILABLE cpu_to_le32(1)
2955 #define IL_STATS_CONF_CLEAR_STATS cpu_to_le32(0x1) /* see above */
2956 #define IL_STATS_CONF_DISABLE_NOTIF cpu_to_le32(0x2) /* see above */
2976 #define STATS_REPLY_FLG_BAND_24G_MSK cpu_to_le32(0x2)
2977 #define STATS_REPLY_FLG_HT40_MODE_MSK cpu_to_le32(0x8)