Lines Matching refs:mt76_rr
15 mt76_rr(dev, MT_RX_STAT_0); in mt76x02_mac_reset_counters()
16 mt76_rr(dev, MT_RX_STAT_1); in mt76x02_mac_reset_counters()
17 mt76_rr(dev, MT_RX_STAT_2); in mt76x02_mac_reset_counters()
18 mt76_rr(dev, MT_TX_STA_0); in mt76x02_mac_reset_counters()
19 mt76_rr(dev, MT_TX_STA_1); in mt76x02_mac_reset_counters()
20 mt76_rr(dev, MT_TX_STA_2); in mt76x02_mac_reset_counters()
23 mt76_rr(dev, MT_TX_AGG_CNT(i)); in mt76x02_mac_reset_counters()
26 mt76_rr(dev, MT_TX_STAT_FIFO); in mt76x02_mac_reset_counters()
69 val = mt76_rr(dev, MT_SKEY_MODE(vif_idx)); in mt76x02_mac_shared_key_setup()
90 iv = mt76_rr(dev, MT_WCID_IV(idx)); in mt76x02_mac_wcid_sync_pn()
91 eiv = mt76_rr(dev, MT_WCID_IV(idx) + 4); in mt76x02_mac_wcid_sync_pn()
171 u32 val = mt76_rr(dev, MT_WCID_DROP(idx)); in mt76x02_mac_wcid_set_drop()
257 stat2 = mt76_rr(dev, MT_TX_STAT_FIFO_EXT); in mt76x02_mac_load_tx_status()
258 stat1 = mt76_rr(dev, MT_TX_STAT_FIFO); in mt76x02_mac_load_tx_status()
954 prot[i] = mt76_rr(dev, MT_CCK_PROT_CFG + i * 4); in mt76x02_mac_set_tx_protection()
961 vht_prot[i] = mt76_rr(dev, MT_TX_PROT_CFG6 + i * 4); in mt76x02_mac_set_tx_protection()
1032 state->cc_busy += mt76_rr(dev, MT_CH_BUSY); in mt76x02_update_channel()
1043 u32 val = mt76_rr(dev, 0x10f4); in mt76x02_check_mac_err()
1065 data = mt76_rr(dev, MT_TX_PIN_CFG); in mt76x02_edcca_tx_enable()
1112 mt76_rr(dev, MT_ED_CCA_TIMER); in mt76x02_edcca_init()
1129 val = mt76_rr(dev, MT_ED_CCA_TIMER); in mt76x02_edcca_check()
1175 u32 val = mt76_rr(dev, MT_TX_AGG_CNT(i)); in mt76x02_mac_work()
1209 mt76_rr(dev, MT_CH_BUSY); in mt76x02_mac_cc_reset()
1210 mt76_rr(dev, MT_CH_IDLE); in mt76x02_mac_cc_reset()