Lines Matching refs:rt2x00_set_field32
58 rt2x00_set_field32(®, BBPCSR_VALUE, value); in rt2400pci_bbp_write()
59 rt2x00_set_field32(®, BBPCSR_REGNUM, word); in rt2400pci_bbp_write()
60 rt2x00_set_field32(®, BBPCSR_BUSY, 1); in rt2400pci_bbp_write()
61 rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 1); in rt2400pci_bbp_write()
87 rt2x00_set_field32(®, BBPCSR_REGNUM, word); in rt2400pci_bbp_read()
88 rt2x00_set_field32(®, BBPCSR_BUSY, 1); in rt2400pci_bbp_read()
89 rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 0); in rt2400pci_bbp_read()
116 rt2x00_set_field32(®, RFCSR_VALUE, value); in rt2400pci_rf_write()
117 rt2x00_set_field32(®, RFCSR_NUMBER_OF_BITS, 20); in rt2400pci_rf_write()
118 rt2x00_set_field32(®, RFCSR_IF_SELECT, 0); in rt2400pci_rf_write()
119 rt2x00_set_field32(®, RFCSR_BUSY, 1); in rt2400pci_rf_write()
148 rt2x00_set_field32(®, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in); in rt2400pci_eepromregister_write()
149 rt2x00_set_field32(®, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out); in rt2400pci_eepromregister_write()
150 rt2x00_set_field32(®, CSR21_EEPROM_DATA_CLOCK, in rt2400pci_eepromregister_write()
152 rt2x00_set_field32(®, CSR21_EEPROM_CHIP_SELECT, in rt2400pci_eepromregister_write()
213 rt2x00_set_field32(®, LEDCSR_LINK, enabled); in rt2400pci_brightness_set()
215 rt2x00_set_field32(®, LEDCSR_ACTIVITY, enabled); in rt2400pci_brightness_set()
229 rt2x00_set_field32(®, LEDCSR_ON_PERIOD, *delay_on); in rt2400pci_blink_set()
230 rt2x00_set_field32(®, LEDCSR_OFF_PERIOD, *delay_off); in rt2400pci_blink_set()
262 rt2x00_set_field32(®, RXCSR0_DROP_CRC, in rt2400pci_config_filter()
264 rt2x00_set_field32(®, RXCSR0_DROP_PHYSICAL, in rt2400pci_config_filter()
266 rt2x00_set_field32(®, RXCSR0_DROP_CONTROL, in rt2400pci_config_filter()
268 rt2x00_set_field32(®, RXCSR0_DROP_NOT_TO_ME, in rt2400pci_config_filter()
270 rt2x00_set_field32(®, RXCSR0_DROP_TODS, in rt2400pci_config_filter()
273 rt2x00_set_field32(®, RXCSR0_DROP_VERSION_ERROR, 1); in rt2400pci_config_filter()
291 rt2x00_set_field32(®, BCNCSR1_PRELOAD, bcn_preload); in rt2400pci_config_intf()
298 rt2x00_set_field32(®, CSR14_TSF_SYNC, conf->sync); in rt2400pci_config_intf()
326 rt2x00_set_field32(®, TXCSR1_ACK_TIMEOUT, 0x1ff); in rt2400pci_config_erp()
327 rt2x00_set_field32(®, TXCSR1_ACK_CONSUME_TIME, 0x13a); in rt2400pci_config_erp()
328 rt2x00_set_field32(®, TXCSR1_TSF_OFFSET, IEEE80211_HEADER); in rt2400pci_config_erp()
329 rt2x00_set_field32(®, TXCSR1_AUTORESPONDER, 1); in rt2400pci_config_erp()
333 rt2x00_set_field32(®, ARCSR2_SIGNAL, 0x00); in rt2400pci_config_erp()
334 rt2x00_set_field32(®, ARCSR2_SERVICE, 0x04); in rt2400pci_config_erp()
335 rt2x00_set_field32(®, ARCSR2_LENGTH, in rt2400pci_config_erp()
340 rt2x00_set_field32(®, ARCSR3_SIGNAL, 0x01 | preamble_mask); in rt2400pci_config_erp()
341 rt2x00_set_field32(®, ARCSR3_SERVICE, 0x04); in rt2400pci_config_erp()
342 rt2x00_set_field32(®, ARCSR2_LENGTH, in rt2400pci_config_erp()
347 rt2x00_set_field32(®, ARCSR4_SIGNAL, 0x02 | preamble_mask); in rt2400pci_config_erp()
348 rt2x00_set_field32(®, ARCSR4_SERVICE, 0x04); in rt2400pci_config_erp()
349 rt2x00_set_field32(®, ARCSR2_LENGTH, in rt2400pci_config_erp()
354 rt2x00_set_field32(®, ARCSR5_SIGNAL, 0x03 | preamble_mask); in rt2400pci_config_erp()
355 rt2x00_set_field32(®, ARCSR5_SERVICE, 0x84); in rt2400pci_config_erp()
356 rt2x00_set_field32(®, ARCSR2_LENGTH, in rt2400pci_config_erp()
366 rt2x00_set_field32(®, CSR11_SLOT_TIME, erp->slot_time); in rt2400pci_config_erp()
370 rt2x00_set_field32(®, CSR18_SIFS, erp->sifs); in rt2400pci_config_erp()
371 rt2x00_set_field32(®, CSR18_PIFS, erp->pifs); in rt2400pci_config_erp()
375 rt2x00_set_field32(®, CSR19_DIFS, erp->difs); in rt2400pci_config_erp()
376 rt2x00_set_field32(®, CSR19_EIFS, erp->eifs); in rt2400pci_config_erp()
382 rt2x00_set_field32(®, CSR12_BEACON_INTERVAL, in rt2400pci_config_erp()
384 rt2x00_set_field32(®, CSR12_CFP_MAX_DURATION, in rt2400pci_config_erp()
448 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1); in rt2400pci_config_channel()
449 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1); in rt2400pci_config_channel()
481 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0); in rt2400pci_config_channel()
482 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0); in rt2400pci_config_channel()
504 rt2x00_set_field32(®, CSR11_LONG_RETRY, in rt2400pci_config_retry_limit()
506 rt2x00_set_field32(®, CSR11_SHORT_RETRY, in rt2400pci_config_retry_limit()
521 rt2x00_set_field32(®, CSR20_DELAY_AFTER_TBCN, in rt2400pci_config_ps()
523 rt2x00_set_field32(®, CSR20_TBCN_BEFORE_WAKEUP, in rt2400pci_config_ps()
527 rt2x00_set_field32(®, CSR20_AUTOWAKE, 0); in rt2400pci_config_ps()
530 rt2x00_set_field32(®, CSR20_AUTOWAKE, 1); in rt2400pci_config_ps()
534 rt2x00_set_field32(®, CSR20_AUTOWAKE, 0); in rt2400pci_config_ps()
562 rt2x00_set_field32(®, CSR11_CWMIN, cw_min); in rt2400pci_config_cw()
563 rt2x00_set_field32(®, CSR11_CWMAX, cw_max); in rt2400pci_config_cw()
635 rt2x00_set_field32(®, RXCSR0_DISABLE_RX, 0); in rt2400pci_start_queue()
640 rt2x00_set_field32(®, CSR14_TSF_COUNT, 1); in rt2400pci_start_queue()
641 rt2x00_set_field32(®, CSR14_TBCN, 1); in rt2400pci_start_queue()
642 rt2x00_set_field32(®, CSR14_BEACON_GEN, 1); in rt2400pci_start_queue()
658 rt2x00_set_field32(®, TXCSR0_KICK_PRIO, 1); in rt2400pci_kick_queue()
663 rt2x00_set_field32(®, TXCSR0_KICK_TX, 1); in rt2400pci_kick_queue()
668 rt2x00_set_field32(®, TXCSR0_KICK_ATIM, 1); in rt2400pci_kick_queue()
686 rt2x00_set_field32(®, TXCSR0_ABORT, 1); in rt2400pci_stop_queue()
691 rt2x00_set_field32(®, RXCSR0_DISABLE_RX, 1); in rt2400pci_stop_queue()
696 rt2x00_set_field32(®, CSR14_TSF_COUNT, 0); in rt2400pci_stop_queue()
697 rt2x00_set_field32(®, CSR14_TBCN, 0); in rt2400pci_stop_queue()
698 rt2x00_set_field32(®, CSR14_BEACON_GEN, 0); in rt2400pci_stop_queue()
739 rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH, entry->skb->len); in rt2400pci_clear_entry()
743 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma); in rt2400pci_clear_entry()
747 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1); in rt2400pci_clear_entry()
751 rt2x00_set_field32(&word, TXD_W0_VALID, 0); in rt2400pci_clear_entry()
752 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0); in rt2400pci_clear_entry()
766 rt2x00_set_field32(®, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size); in rt2400pci_init_queues()
767 rt2x00_set_field32(®, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit); in rt2400pci_init_queues()
768 rt2x00_set_field32(®, TXCSR2_NUM_ATIM, rt2x00dev->atim->limit); in rt2400pci_init_queues()
769 rt2x00_set_field32(®, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit); in rt2400pci_init_queues()
774 rt2x00_set_field32(®, TXCSR3_TX_RING_REGISTER, in rt2400pci_init_queues()
780 rt2x00_set_field32(®, TXCSR5_PRIO_RING_REGISTER, in rt2400pci_init_queues()
786 rt2x00_set_field32(®, TXCSR4_ATIM_RING_REGISTER, in rt2400pci_init_queues()
792 rt2x00_set_field32(®, TXCSR6_BEACON_RING_REGISTER, in rt2400pci_init_queues()
797 rt2x00_set_field32(®, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size); in rt2400pci_init_queues()
798 rt2x00_set_field32(®, RXCSR1_NUM_RXD, rt2x00dev->rx->limit); in rt2400pci_init_queues()
803 rt2x00_set_field32(®, RXCSR2_RX_RING_REGISTER, in rt2400pci_init_queues()
820 rt2x00_set_field32(®, TIMECSR_US_COUNT, 33); in rt2400pci_init_registers()
821 rt2x00_set_field32(®, TIMECSR_US_64_COUNT, 63); in rt2400pci_init_registers()
822 rt2x00_set_field32(®, TIMECSR_BEACON_EXPECT, 0); in rt2400pci_init_registers()
826 rt2x00_set_field32(®, CSR9_MAX_FRAME_UNIT, in rt2400pci_init_registers()
831 rt2x00_set_field32(®, CSR14_TSF_COUNT, 0); in rt2400pci_init_registers()
832 rt2x00_set_field32(®, CSR14_TSF_SYNC, 0); in rt2400pci_init_registers()
833 rt2x00_set_field32(®, CSR14_TBCN, 0); in rt2400pci_init_registers()
834 rt2x00_set_field32(®, CSR14_TCFP, 0); in rt2400pci_init_registers()
835 rt2x00_set_field32(®, CSR14_TATIMW, 0); in rt2400pci_init_registers()
836 rt2x00_set_field32(®, CSR14_BEACON_GEN, 0); in rt2400pci_init_registers()
837 rt2x00_set_field32(®, CSR14_CFP_COUNT_PRELOAD, 0); in rt2400pci_init_registers()
838 rt2x00_set_field32(®, CSR14_TBCM_PRELOAD, 0); in rt2400pci_init_registers()
844 rt2x00_set_field32(®, ARCSR0_AR_BBP_DATA0, 133); in rt2400pci_init_registers()
845 rt2x00_set_field32(®, ARCSR0_AR_BBP_ID0, 134); in rt2400pci_init_registers()
846 rt2x00_set_field32(®, ARCSR0_AR_BBP_DATA1, 136); in rt2400pci_init_registers()
847 rt2x00_set_field32(®, ARCSR0_AR_BBP_ID1, 135); in rt2400pci_init_registers()
851 rt2x00_set_field32(®, RXCSR3_BBP_ID0, 3); /* Tx power.*/ in rt2400pci_init_registers()
852 rt2x00_set_field32(®, RXCSR3_BBP_ID0_VALID, 1); in rt2400pci_init_registers()
853 rt2x00_set_field32(®, RXCSR3_BBP_ID1, 32); /* Signal */ in rt2400pci_init_registers()
854 rt2x00_set_field32(®, RXCSR3_BBP_ID1_VALID, 1); in rt2400pci_init_registers()
855 rt2x00_set_field32(®, RXCSR3_BBP_ID2, 36); /* Rssi */ in rt2400pci_init_registers()
856 rt2x00_set_field32(®, RXCSR3_BBP_ID2_VALID, 1); in rt2400pci_init_registers()
868 rt2x00_set_field32(®, MACCSR2_DELAY, 64); in rt2400pci_init_registers()
872 rt2x00_set_field32(®, RALINKCSR_AR_BBP_DATA0, 17); in rt2400pci_init_registers()
873 rt2x00_set_field32(®, RALINKCSR_AR_BBP_ID0, 154); in rt2400pci_init_registers()
874 rt2x00_set_field32(®, RALINKCSR_AR_BBP_DATA1, 0); in rt2400pci_init_registers()
875 rt2x00_set_field32(®, RALINKCSR_AR_BBP_ID1, 154); in rt2400pci_init_registers()
879 rt2x00_set_field32(®, CSR1_SOFT_RESET, 1); in rt2400pci_init_registers()
880 rt2x00_set_field32(®, CSR1_BBP_RESET, 0); in rt2400pci_init_registers()
881 rt2x00_set_field32(®, CSR1_HOST_READY, 0); in rt2400pci_init_registers()
885 rt2x00_set_field32(®, CSR1_SOFT_RESET, 0); in rt2400pci_init_registers()
886 rt2x00_set_field32(®, CSR1_HOST_READY, 1); in rt2400pci_init_registers()
980 rt2x00_set_field32(®, CSR8_TBCN_EXPIRE, mask); in rt2400pci_toggle_irq()
981 rt2x00_set_field32(®, CSR8_TXDONE_TXRING, mask); in rt2400pci_toggle_irq()
982 rt2x00_set_field32(®, CSR8_TXDONE_ATIMRING, mask); in rt2400pci_toggle_irq()
983 rt2x00_set_field32(®, CSR8_TXDONE_PRIORING, mask); in rt2400pci_toggle_irq()
984 rt2x00_set_field32(®, CSR8_RXDONE, mask); in rt2400pci_toggle_irq()
1033 rt2x00_set_field32(®, PWRCSR1_SET_STATE, 1); in rt2400pci_set_state()
1034 rt2x00_set_field32(®, PWRCSR1_BBP_DESIRE_STATE, state); in rt2400pci_set_state()
1035 rt2x00_set_field32(®, PWRCSR1_RF_DESIRE_STATE, state); in rt2400pci_set_state()
1036 rt2x00_set_field32(®, PWRCSR1_PUT_TO_SLEEP, put_to_sleep); in rt2400pci_set_state()
1106 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma); in rt2400pci_write_tx_desc()
1110 rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH, txdesc->length); in rt2400pci_write_tx_desc()
1111 rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, txdesc->length); in rt2400pci_write_tx_desc()
1115 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->u.plcp.signal); in rt2400pci_write_tx_desc()
1116 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_REGNUM, 5); in rt2400pci_write_tx_desc()
1117 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_BUSY, 1); in rt2400pci_write_tx_desc()
1118 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->u.plcp.service); in rt2400pci_write_tx_desc()
1119 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_REGNUM, 6); in rt2400pci_write_tx_desc()
1120 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_BUSY, 1); in rt2400pci_write_tx_desc()
1124 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW, in rt2400pci_write_tx_desc()
1126 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_REGNUM, 8); in rt2400pci_write_tx_desc()
1127 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_BUSY, 1); in rt2400pci_write_tx_desc()
1128 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH, in rt2400pci_write_tx_desc()
1130 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_REGNUM, 7); in rt2400pci_write_tx_desc()
1131 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_BUSY, 1); in rt2400pci_write_tx_desc()
1140 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1); in rt2400pci_write_tx_desc()
1141 rt2x00_set_field32(&word, TXD_W0_VALID, 1); in rt2400pci_write_tx_desc()
1142 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG, in rt2400pci_write_tx_desc()
1144 rt2x00_set_field32(&word, TXD_W0_ACK, in rt2400pci_write_tx_desc()
1146 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP, in rt2400pci_write_tx_desc()
1148 rt2x00_set_field32(&word, TXD_W0_RTS, in rt2400pci_write_tx_desc()
1150 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->u.plcp.ifs); in rt2400pci_write_tx_desc()
1151 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE, in rt2400pci_write_tx_desc()
1176 rt2x00_set_field32(®, CSR14_BEACON_GEN, 0); in rt2400pci_write_beacon()
1186 rt2x00_set_field32(®, CSR14_BEACON_GEN, 1); in rt2400pci_write_beacon()
1200 rt2x00_set_field32(®, CSR14_BEACON_GEN, 1); in rt2400pci_write_beacon()
1316 rt2x00_set_field32(®, irq_field, 0); in rt2400pci_enable_interrupt()
1342 rt2x00_set_field32(®, CSR8_TXDONE_TXRING, 0); in rt2400pci_txstatus_tasklet()
1343 rt2x00_set_field32(®, CSR8_TXDONE_ATIMRING, 0); in rt2400pci_txstatus_tasklet()
1344 rt2x00_set_field32(®, CSR8_TXDONE_PRIORING, 0); in rt2400pci_txstatus_tasklet()
1405 rt2x00_set_field32(&mask, CSR8_TXDONE_TXRING, 1); in rt2400pci_interrupt()
1406 rt2x00_set_field32(&mask, CSR8_TXDONE_ATIMRING, 1); in rt2400pci_interrupt()
1407 rt2x00_set_field32(&mask, CSR8_TXDONE_PRIORING, 1); in rt2400pci_interrupt()
1628 rt2x00_set_field32(®, GPIOCSR_DIR0, 1); in rt2400pci_probe_hw()