Lines Matching refs:FIELD32
55 #define CSR0_REVISION FIELD32(0x0000ffff)
64 #define CSR1_SOFT_RESET FIELD32(0x00000001)
65 #define CSR1_BBP_RESET FIELD32(0x00000002)
66 #define CSR1_HOST_READY FIELD32(0x00000004)
77 #define CSR3_BYTE0 FIELD32(0x000000ff)
78 #define CSR3_BYTE1 FIELD32(0x0000ff00)
79 #define CSR3_BYTE2 FIELD32(0x00ff0000)
80 #define CSR3_BYTE3 FIELD32(0xff000000)
86 #define CSR4_BYTE4 FIELD32(0x000000ff)
87 #define CSR4_BYTE5 FIELD32(0x0000ff00)
93 #define CSR5_BYTE0 FIELD32(0x000000ff)
94 #define CSR5_BYTE1 FIELD32(0x0000ff00)
95 #define CSR5_BYTE2 FIELD32(0x00ff0000)
96 #define CSR5_BYTE3 FIELD32(0xff000000)
102 #define CSR6_BYTE4 FIELD32(0x000000ff)
103 #define CSR6_BYTE5 FIELD32(0x0000ff00)
117 #define CSR7_TBCN_EXPIRE FIELD32(0x00000001)
118 #define CSR7_TWAKE_EXPIRE FIELD32(0x00000002)
119 #define CSR7_TATIMW_EXPIRE FIELD32(0x00000004)
120 #define CSR7_TXDONE_TXRING FIELD32(0x00000008)
121 #define CSR7_TXDONE_ATIMRING FIELD32(0x00000010)
122 #define CSR7_TXDONE_PRIORING FIELD32(0x00000020)
123 #define CSR7_RXDONE FIELD32(0x00000040)
137 #define CSR8_TBCN_EXPIRE FIELD32(0x00000001)
138 #define CSR8_TWAKE_EXPIRE FIELD32(0x00000002)
139 #define CSR8_TATIMW_EXPIRE FIELD32(0x00000004)
140 #define CSR8_TXDONE_TXRING FIELD32(0x00000008)
141 #define CSR8_TXDONE_ATIMRING FIELD32(0x00000010)
142 #define CSR8_TXDONE_PRIORING FIELD32(0x00000020)
143 #define CSR8_RXDONE FIELD32(0x00000040)
150 #define CSR9_MAX_FRAME_UNIT FIELD32(0x00000f80)
161 #define CSR11_CWMIN FIELD32(0x0000000f)
162 #define CSR11_CWMAX FIELD32(0x000000f0)
163 #define CSR11_SLOT_TIME FIELD32(0x00001f00)
164 #define CSR11_LONG_RETRY FIELD32(0x00ff0000)
165 #define CSR11_SHORT_RETRY FIELD32(0xff000000)
174 #define CSR12_BEACON_INTERVAL FIELD32(0x0000ffff)
175 #define CSR12_CFP_MAX_DURATION FIELD32(0xffff0000)
184 #define CSR13_ATIMW_DURATION FIELD32(0x0000ffff)
185 #define CSR13_CFP_PERIOD FIELD32(0x00ff0000)
199 #define CSR14_TSF_COUNT FIELD32(0x00000001)
200 #define CSR14_TSF_SYNC FIELD32(0x00000006)
201 #define CSR14_TBCN FIELD32(0x00000008)
202 #define CSR14_TCFP FIELD32(0x00000010)
203 #define CSR14_TATIMW FIELD32(0x00000020)
204 #define CSR14_BEACON_GEN FIELD32(0x00000040)
205 #define CSR14_CFP_COUNT_PRELOAD FIELD32(0x0000ff00)
206 #define CSR14_TBCM_PRELOAD FIELD32(0xffff0000)
215 #define CSR15_CFP FIELD32(0x00000001)
216 #define CSR15_ATIMW FIELD32(0x00000002)
217 #define CSR15_BEACON_SENT FIELD32(0x00000004)
223 #define CSR16_LOW_TSFTIMER FIELD32(0xffffffff)
229 #define CSR17_HIGH_TSFTIMER FIELD32(0xffffffff)
237 #define CSR18_SIFS FIELD32(0x0000ffff)
238 #define CSR18_PIFS FIELD32(0xffff0000)
246 #define CSR19_DIFS FIELD32(0x0000ffff)
247 #define CSR19_EIFS FIELD32(0xffff0000)
256 #define CSR20_DELAY_AFTER_TBCN FIELD32(0x0000ffff)
257 #define CSR20_TBCN_BEFORE_WAKEUP FIELD32(0x00ff0000)
258 #define CSR20_AUTOWAKE FIELD32(0x01000000)
266 #define CSR21_RELOAD FIELD32(0x00000001)
267 #define CSR21_EEPROM_DATA_CLOCK FIELD32(0x00000002)
268 #define CSR21_EEPROM_CHIP_SELECT FIELD32(0x00000004)
269 #define CSR21_EEPROM_DATA_IN FIELD32(0x00000008)
270 #define CSR21_EEPROM_DATA_OUT FIELD32(0x00000010)
271 #define CSR21_TYPE_93C46 FIELD32(0x00000020)
279 #define CSR22_CFP_DURATION_REMAIN FIELD32(0x0000ffff)
280 #define CSR22_RELOAD_CFP_DURATION FIELD32(0x00010000)
295 #define TXCSR0_KICK_TX FIELD32(0x00000001)
296 #define TXCSR0_KICK_ATIM FIELD32(0x00000002)
297 #define TXCSR0_KICK_PRIO FIELD32(0x00000004)
298 #define TXCSR0_ABORT FIELD32(0x00000008)
308 #define TXCSR1_ACK_TIMEOUT FIELD32(0x000001ff)
309 #define TXCSR1_ACK_CONSUME_TIME FIELD32(0x0003fe00)
310 #define TXCSR1_TSF_OFFSET FIELD32(0x00fc0000)
311 #define TXCSR1_AUTORESPONDER FIELD32(0x01000000)
321 #define TXCSR2_TXD_SIZE FIELD32(0x000000ff)
322 #define TXCSR2_NUM_TXD FIELD32(0x0000ff00)
323 #define TXCSR2_NUM_ATIM FIELD32(0x00ff0000)
324 #define TXCSR2_NUM_PRIO FIELD32(0xff000000)
330 #define TXCSR3_TX_RING_REGISTER FIELD32(0xffffffff)
336 #define TXCSR4_ATIM_RING_REGISTER FIELD32(0xffffffff)
342 #define TXCSR5_PRIO_RING_REGISTER FIELD32(0xffffffff)
348 #define TXCSR6_BEACON_RING_REGISTER FIELD32(0xffffffff)
355 #define TXCSR7_AR_POWERMANAGEMENT FIELD32(0x00000001)
374 #define RXCSR0_DISABLE_RX FIELD32(0x00000001)
375 #define RXCSR0_DROP_CRC FIELD32(0x00000002)
376 #define RXCSR0_DROP_PHYSICAL FIELD32(0x00000004)
377 #define RXCSR0_DROP_CONTROL FIELD32(0x00000008)
378 #define RXCSR0_DROP_NOT_TO_ME FIELD32(0x00000010)
379 #define RXCSR0_DROP_TODS FIELD32(0x00000020)
380 #define RXCSR0_DROP_VERSION_ERROR FIELD32(0x00000040)
381 #define RXCSR0_PASS_CRC FIELD32(0x00000080)
389 #define RXCSR1_RXD_SIZE FIELD32(0x000000ff)
390 #define RXCSR1_NUM_RXD FIELD32(0x0000ff00)
396 #define RXCSR2_RX_RING_REGISTER FIELD32(0xffffffff)
404 #define RXCSR3_BBP_ID0 FIELD32(0x0000007f)
405 #define RXCSR3_BBP_ID0_VALID FIELD32(0x00000080)
406 #define RXCSR3_BBP_ID1 FIELD32(0x00007f00)
407 #define RXCSR3_BBP_ID1_VALID FIELD32(0x00008000)
408 #define RXCSR3_BBP_ID2 FIELD32(0x007f0000)
409 #define RXCSR3_BBP_ID2_VALID FIELD32(0x00800000)
410 #define RXCSR3_BBP_ID3 FIELD32(0x7f000000)
411 #define RXCSR3_BBP_ID3_VALID FIELD32(0x80000000)
419 #define RXCSR4_BBP_ID4 FIELD32(0x0000007f)
420 #define RXCSR4_BBP_ID4_VALID FIELD32(0x00000080)
421 #define RXCSR4_BBP_ID5 FIELD32(0x00007f00)
422 #define RXCSR4_BBP_ID5_VALID FIELD32(0x00008000)
430 #define ARCSR0_AR_BBP_DATA0 FIELD32(0x000000ff)
431 #define ARCSR0_AR_BBP_ID0 FIELD32(0x0000ff00)
432 #define ARCSR0_AR_BBP_DATA1 FIELD32(0x00ff0000)
433 #define ARCSR0_AR_BBP_ID1 FIELD32(0xff000000)
441 #define ARCSR1_AR_BBP_DATA2 FIELD32(0x000000ff)
442 #define ARCSR1_AR_BBP_ID2 FIELD32(0x0000ff00)
443 #define ARCSR1_AR_BBP_DATA3 FIELD32(0x00ff0000)
444 #define ARCSR1_AR_BBP_ID3 FIELD32(0xff000000)
462 #define PCICSR_BIG_ENDIAN FIELD32(0x00000001)
463 #define PCICSR_RX_TRESHOLD FIELD32(0x00000006)
464 #define PCICSR_TX_TRESHOLD FIELD32(0x00000018)
465 #define PCICSR_BURST_LENTH FIELD32(0x00000060)
466 #define PCICSR_ENABLE_CLK FIELD32(0x00000080)
473 #define CNT0_FCS_ERROR FIELD32(0x0000ffff)
519 #define PWRCSR1_SET_STATE FIELD32(0x00000001)
520 #define PWRCSR1_BBP_DESIRE_STATE FIELD32(0x00000006)
521 #define PWRCSR1_RF_DESIRE_STATE FIELD32(0x00000018)
522 #define PWRCSR1_BBP_CURR_STATE FIELD32(0x00000060)
523 #define PWRCSR1_RF_CURR_STATE FIELD32(0x00000180)
524 #define PWRCSR1_PUT_TO_SLEEP FIELD32(0x00000200)
533 #define TIMECSR_US_COUNT FIELD32(0x000000ff)
534 #define TIMECSR_US_64_COUNT FIELD32(0x0000ff00)
535 #define TIMECSR_BEACON_EXPECT FIELD32(0x00070000)
553 #define MACCSR1_KICK_RX FIELD32(0x00000001)
554 #define MACCSR1_ONESHOT_RXMODE FIELD32(0x00000002)
555 #define MACCSR1_BBPRX_RESET_MODE FIELD32(0x00000004)
556 #define MACCSR1_AUTO_TXBBP FIELD32(0x00000008)
557 #define MACCSR1_AUTO_RXBBP FIELD32(0x00000010)
558 #define MACCSR1_LOOPBACK FIELD32(0x00000060)
559 #define MACCSR1_INTERSIL_IF FIELD32(0x00000080)
567 #define RALINKCSR_AR_BBP_DATA0 FIELD32(0x000000ff)
568 #define RALINKCSR_AR_BBP_ID0 FIELD32(0x0000ff00)
569 #define RALINKCSR_AR_BBP_DATA1 FIELD32(0x00ff0000)
570 #define RALINKCSR_AR_BBP_ID1 FIELD32(0xff000000)
581 #define BCNCSR_CHANGE FIELD32(0x00000001)
582 #define BCNCSR_DELTATIME FIELD32(0x0000001e)
583 #define BCNCSR_NUM_BEACON FIELD32(0x00001fe0)
584 #define BCNCSR_MODE FIELD32(0x00006000)
585 #define BCNCSR_PLUS FIELD32(0x00008000)
599 #define BBPCSR_VALUE FIELD32(0x000000ff)
600 #define BBPCSR_REGNUM FIELD32(0x00007f00)
601 #define BBPCSR_BUSY FIELD32(0x00008000)
602 #define BBPCSR_WRITE_CONTROL FIELD32(0x00010000)
613 #define RFCSR_VALUE FIELD32(0x00ffffff)
614 #define RFCSR_NUMBER_OF_BITS FIELD32(0x1f000000)
615 #define RFCSR_IF_SELECT FIELD32(0x20000000)
616 #define RFCSR_PLL_LD FIELD32(0x40000000)
617 #define RFCSR_BUSY FIELD32(0x80000000)
627 #define LEDCSR_ON_PERIOD FIELD32(0x000000ff)
628 #define LEDCSR_OFF_PERIOD FIELD32(0x0000ff00)
629 #define LEDCSR_LINK FIELD32(0x00010000)
630 #define LEDCSR_ACTIVITY FIELD32(0x00020000)
654 #define GPIOCSR_VAL0 FIELD32(0x00000001)
655 #define GPIOCSR_VAL1 FIELD32(0x00000002)
656 #define GPIOCSR_VAL2 FIELD32(0x00000004)
657 #define GPIOCSR_VAL3 FIELD32(0x00000008)
658 #define GPIOCSR_VAL4 FIELD32(0x00000010)
659 #define GPIOCSR_VAL5 FIELD32(0x00000020)
660 #define GPIOCSR_VAL6 FIELD32(0x00000040)
661 #define GPIOCSR_VAL7 FIELD32(0x00000080)
662 #define GPIOCSR_DIR0 FIELD32(0x00000100)
663 #define GPIOCSR_DIR1 FIELD32(0x00000200)
664 #define GPIOCSR_DIR2 FIELD32(0x00000400)
665 #define GPIOCSR_DIR3 FIELD32(0x00000800)
666 #define GPIOCSR_DIR4 FIELD32(0x00001000)
667 #define GPIOCSR_DIR5 FIELD32(0x00002000)
668 #define GPIOCSR_DIR6 FIELD32(0x00004000)
669 #define GPIOCSR_DIR7 FIELD32(0x00008000)
681 #define BCNCSR1_PRELOAD FIELD32(0x0000ffff)
688 #define MACCSR2_DELAY FIELD32(0x000000ff)
694 #define ARCSR2_SIGNAL FIELD32(0x000000ff)
695 #define ARCSR2_SERVICE FIELD32(0x0000ff00)
696 #define ARCSR2_LENGTH_LOW FIELD32(0x00ff0000)
697 #define ARCSR2_LENGTH FIELD32(0xffff0000)
703 #define ARCSR3_SIGNAL FIELD32(0x000000ff)
704 #define ARCSR3_SERVICE FIELD32(0x0000ff00)
705 #define ARCSR3_LENGTH FIELD32(0xffff0000)
711 #define ARCSR4_SIGNAL FIELD32(0x000000ff)
712 #define ARCSR4_SERVICE FIELD32(0x0000ff00)
713 #define ARCSR4_LENGTH FIELD32(0xffff0000)
719 #define ARCSR5_SIGNAL FIELD32(0x000000ff)
720 #define ARCSR5_SERVICE FIELD32(0x0000ff00)
721 #define ARCSR5_LENGTH FIELD32(0xffff0000)
745 #define RF1_TUNER FIELD32(0x00020000)
750 #define RF3_TUNER FIELD32(0x00000100)
751 #define RF3_TXPOWER FIELD32(0x00003e00)
819 #define TXD_W0_OWNER_NIC FIELD32(0x00000001)
820 #define TXD_W0_VALID FIELD32(0x00000002)
821 #define TXD_W0_RESULT FIELD32(0x0000001c)
822 #define TXD_W0_RETRY_COUNT FIELD32(0x000000e0)
823 #define TXD_W0_MORE_FRAG FIELD32(0x00000100)
824 #define TXD_W0_ACK FIELD32(0x00000200)
825 #define TXD_W0_TIMESTAMP FIELD32(0x00000400)
826 #define TXD_W0_RTS FIELD32(0x00000800)
827 #define TXD_W0_IFS FIELD32(0x00006000)
828 #define TXD_W0_RETRY_MODE FIELD32(0x00008000)
829 #define TXD_W0_AGC FIELD32(0x00ff0000)
830 #define TXD_W0_R2 FIELD32(0xff000000)
835 #define TXD_W1_BUFFER_ADDRESS FIELD32(0xffffffff)
840 #define TXD_W2_BUFFER_LENGTH FIELD32(0x0000ffff)
841 #define TXD_W2_DATABYTE_COUNT FIELD32(0xffff0000)
847 #define TXD_W3_PLCP_SIGNAL FIELD32(0x000000ff)
848 #define TXD_W3_PLCP_SIGNAL_REGNUM FIELD32(0x00007f00)
849 #define TXD_W3_PLCP_SIGNAL_BUSY FIELD32(0x00008000)
850 #define TXD_W3_PLCP_SERVICE FIELD32(0x00ff0000)
851 #define TXD_W3_PLCP_SERVICE_REGNUM FIELD32(0x7f000000)
852 #define TXD_W3_PLCP_SERVICE_BUSY FIELD32(0x80000000)
854 #define TXD_W4_PLCP_LENGTH_LOW FIELD32(0x000000ff)
855 #define TXD_W3_PLCP_LENGTH_LOW_REGNUM FIELD32(0x00007f00)
856 #define TXD_W3_PLCP_LENGTH_LOW_BUSY FIELD32(0x00008000)
857 #define TXD_W4_PLCP_LENGTH_HIGH FIELD32(0x00ff0000)
858 #define TXD_W3_PLCP_LENGTH_HIGH_REGNUM FIELD32(0x7f000000)
859 #define TXD_W3_PLCP_LENGTH_HIGH_BUSY FIELD32(0x80000000)
864 #define TXD_W5_BBCR4 FIELD32(0x0000ffff)
865 #define TXD_W5_AGC_REG FIELD32(0x007f0000)
866 #define TXD_W5_AGC_REG_VALID FIELD32(0x00800000)
867 #define TXD_W5_XXX_REG FIELD32(0x7f000000)
868 #define TXD_W5_XXX_REG_VALID FIELD32(0x80000000)
873 #define TXD_W6_SK_BUFF FIELD32(0xffffffff)
878 #define TXD_W7_RESERVED FIELD32(0xffffffff)
887 #define RXD_W0_OWNER_NIC FIELD32(0x00000001)
888 #define RXD_W0_UNICAST_TO_ME FIELD32(0x00000002)
889 #define RXD_W0_MULTICAST FIELD32(0x00000004)
890 #define RXD_W0_BROADCAST FIELD32(0x00000008)
891 #define RXD_W0_MY_BSS FIELD32(0x00000010)
892 #define RXD_W0_CRC_ERROR FIELD32(0x00000020)
893 #define RXD_W0_PHYSICAL_ERROR FIELD32(0x00000080)
894 #define RXD_W0_DATABYTE_COUNT FIELD32(0xffff0000)
899 #define RXD_W1_BUFFER_ADDRESS FIELD32(0xffffffff)
904 #define RXD_W2_BUFFER_LENGTH FIELD32(0x0000ffff)
905 #define RXD_W2_BBR0 FIELD32(0x00ff0000)
906 #define RXD_W2_SIGNAL FIELD32(0xff000000)
911 #define RXD_W3_RSSI FIELD32(0x000000ff)
912 #define RXD_W3_BBR3 FIELD32(0x0000ff00)
913 #define RXD_W3_BBR4 FIELD32(0x00ff0000)
914 #define RXD_W3_BBR5 FIELD32(0xff000000)
919 #define RXD_W4_RX_END_TIME FIELD32(0xffffffff)
924 #define RXD_W5_RESERVED FIELD32(0xffffffff)
925 #define RXD_W6_RESERVED FIELD32(0xffffffff)
926 #define RXD_W7_RESERVED FIELD32(0xffffffff)