Lines Matching refs:rt2x00_set_field32

58 		rt2x00_set_field32(&reg, BBPCSR_VALUE, value);  in rt2500pci_bbp_write()
59 		rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);  in rt2500pci_bbp_write()
60 		rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);  in rt2500pci_bbp_write()
61 		rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);  in rt2500pci_bbp_write()
87 		rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);  in rt2500pci_bbp_read()
88 		rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);  in rt2500pci_bbp_read()
89 		rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);  in rt2500pci_bbp_read()
116 		rt2x00_set_field32(&reg, RFCSR_VALUE, value);  in rt2500pci_rf_write()
117 		rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);  in rt2500pci_rf_write()
118 		rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);  in rt2500pci_rf_write()
119 		rt2x00_set_field32(&reg, RFCSR_BUSY, 1);  in rt2500pci_rf_write()
148 	rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);  in rt2500pci_eepromregister_write()
149 	rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);  in rt2500pci_eepromregister_write()
150 	rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,  in rt2500pci_eepromregister_write()
152 	rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,  in rt2500pci_eepromregister_write()
213 		rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);  in rt2500pci_brightness_set()
215 		rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled);  in rt2500pci_brightness_set()
229 	rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, *delay_on);  in rt2500pci_blink_set()
230 	rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, *delay_off);  in rt2500pci_blink_set()
263 	rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,  in rt2500pci_config_filter()
265 	rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,  in rt2500pci_config_filter()
267 	rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,  in rt2500pci_config_filter()
269 	rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,  in rt2500pci_config_filter()
271 	rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,  in rt2500pci_config_filter()
274 	rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);  in rt2500pci_config_filter()
275 	rt2x00_set_field32(&reg, RXCSR0_DROP_MCAST,  in rt2500pci_config_filter()
277 	rt2x00_set_field32(&reg, RXCSR0_DROP_BCAST, 0);  in rt2500pci_config_filter()
296 		rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);  in rt2500pci_config_intf()
297 		rt2x00_set_field32(&reg, BCNCSR1_BEACON_CWMIN, queue->cw_min);  in rt2500pci_config_intf()
304 		rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);  in rt2500pci_config_intf()
331 		rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, 0x162);  in rt2500pci_config_erp()
332 		rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, 0xa2);  in rt2500pci_config_erp()
333 		rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);  in rt2500pci_config_erp()
334 		rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);  in rt2500pci_config_erp()
338 		rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00);  in rt2500pci_config_erp()
339 		rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);  in rt2500pci_config_erp()
340 		rt2x00_set_field32(&reg, ARCSR2_LENGTH,  in rt2500pci_config_erp()
345 		rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);  in rt2500pci_config_erp()
346 		rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);  in rt2500pci_config_erp()
347 		rt2x00_set_field32(&reg, ARCSR2_LENGTH,  in rt2500pci_config_erp()
352 		rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);  in rt2500pci_config_erp()
353 		rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);  in rt2500pci_config_erp()
354 		rt2x00_set_field32(&reg, ARCSR2_LENGTH,  in rt2500pci_config_erp()
359 		rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);  in rt2500pci_config_erp()
360 		rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);  in rt2500pci_config_erp()
361 		rt2x00_set_field32(&reg, ARCSR2_LENGTH,  in rt2500pci_config_erp()
371 		rt2x00_set_field32(&reg, CSR11_SLOT_TIME, erp->slot_time);  in rt2500pci_config_erp()
375 		rt2x00_set_field32(&reg, CSR18_SIFS, erp->sifs);  in rt2500pci_config_erp()
376 		rt2x00_set_field32(&reg, CSR18_PIFS, erp->pifs);  in rt2500pci_config_erp()
380 		rt2x00_set_field32(&reg, CSR19_DIFS, erp->difs);  in rt2500pci_config_erp()
381 		rt2x00_set_field32(&reg, CSR19_EIFS, erp->eifs);  in rt2500pci_config_erp()
387 		rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,  in rt2500pci_config_erp()
389 		rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,  in rt2500pci_config_erp()
420 		rt2x00_set_field32(&reg, BBPCSR1_CCK, 0);  in rt2500pci_config_ant()
421 		rt2x00_set_field32(&reg, BBPCSR1_OFDM, 0);  in rt2500pci_config_ant()
426 		rt2x00_set_field32(&reg, BBPCSR1_CCK, 2);  in rt2500pci_config_ant()
427 		rt2x00_set_field32(&reg, BBPCSR1_OFDM, 2);  in rt2500pci_config_ant()
449 		rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 1);  in rt2500pci_config_ant()
450 		rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 1);  in rt2500pci_config_ant()
458 		rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 0);  in rt2500pci_config_ant()
459 		rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 0);  in rt2500pci_config_ant()
475 	rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));  in rt2500pci_config_channel()
482 		rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);  in rt2500pci_config_channel()
483 	rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);  in rt2500pci_config_channel()
523 		rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);  in rt2500pci_config_channel()
527 	rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);  in rt2500pci_config_channel()
542 	rt2x00_set_field32(&rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));  in rt2500pci_config_txpower()
552 	rt2x00_set_field32(&reg, CSR11_LONG_RETRY,  in rt2500pci_config_retry_limit()
554 	rt2x00_set_field32(&reg, CSR11_SHORT_RETRY,  in rt2500pci_config_retry_limit()
569 		rt2x00_set_field32(&reg, CSR20_DELAY_AFTER_TBCN,  in rt2500pci_config_ps()
571 		rt2x00_set_field32(&reg, CSR20_TBCN_BEFORE_WAKEUP,  in rt2500pci_config_ps()
575 		rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);  in rt2500pci_config_ps()
578 		rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 1);  in rt2500pci_config_ps()
582 		rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);  in rt2500pci_config_ps()
724 		rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX, 0);  in rt2500pci_start_queue()
729 		rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);  in rt2500pci_start_queue()
730 		rt2x00_set_field32(&reg, CSR14_TBCN, 1);  in rt2500pci_start_queue()
731 		rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);  in rt2500pci_start_queue()
747 		rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, 1);  in rt2500pci_kick_queue()
752 		rt2x00_set_field32(&reg, TXCSR0_KICK_TX, 1);  in rt2500pci_kick_queue()
757 		rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, 1);  in rt2500pci_kick_queue()
775 		rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);  in rt2500pci_stop_queue()
780 		rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX, 1);  in rt2500pci_stop_queue()
785 		rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);  in rt2500pci_stop_queue()
786 		rt2x00_set_field32(&reg, CSR14_TBCN, 0);  in rt2500pci_stop_queue()
787 		rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);  in rt2500pci_stop_queue()
828 		rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);  in rt2500pci_clear_entry()
832 		rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);  in rt2500pci_clear_entry()
836 		rt2x00_set_field32(&word, TXD_W0_VALID, 0);  in rt2500pci_clear_entry()
837 		rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);  in rt2500pci_clear_entry()
851 	rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);  in rt2500pci_init_queues()
852 	rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);  in rt2500pci_init_queues()
853 	rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->atim->limit);  in rt2500pci_init_queues()
854 	rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);  in rt2500pci_init_queues()
859 	rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,  in rt2500pci_init_queues()
865 	rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,  in rt2500pci_init_queues()
871 	rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,  in rt2500pci_init_queues()
877 	rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,  in rt2500pci_init_queues()
882 	rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);  in rt2500pci_init_queues()
883 	rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);  in rt2500pci_init_queues()
888 	rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,  in rt2500pci_init_queues()
905 	rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);  in rt2500pci_init_registers()
906 	rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);  in rt2500pci_init_registers()
907 	rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);  in rt2500pci_init_registers()
911 	rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,  in rt2500pci_init_registers()
919 	rt2x00_set_field32(&reg, CSR11_CW_SELECT, 0);  in rt2500pci_init_registers()
923 	rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);  in rt2500pci_init_registers()
924 	rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 0);  in rt2500pci_init_registers()
925 	rt2x00_set_field32(&reg, CSR14_TBCN, 0);  in rt2500pci_init_registers()
926 	rt2x00_set_field32(&reg, CSR14_TCFP, 0);  in rt2500pci_init_registers()
927 	rt2x00_set_field32(&reg, CSR14_TATIMW, 0);  in rt2500pci_init_registers()
928 	rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);  in rt2500pci_init_registers()
929 	rt2x00_set_field32(&reg, CSR14_CFP_COUNT_PRELOAD, 0);  in rt2500pci_init_registers()
930 	rt2x00_set_field32(&reg, CSR14_TBCM_PRELOAD, 0);  in rt2500pci_init_registers()
936 	rt2x00_set_field32(&reg, TXCSR8_BBP_ID0, 10);  in rt2500pci_init_registers()
937 	rt2x00_set_field32(&reg, TXCSR8_BBP_ID0_VALID, 1);  in rt2500pci_init_registers()
938 	rt2x00_set_field32(&reg, TXCSR8_BBP_ID1, 11);  in rt2500pci_init_registers()
939 	rt2x00_set_field32(&reg, TXCSR8_BBP_ID1_VALID, 1);  in rt2500pci_init_registers()
940 	rt2x00_set_field32(&reg, TXCSR8_BBP_ID2, 13);  in rt2500pci_init_registers()
941 	rt2x00_set_field32(&reg, TXCSR8_BBP_ID2_VALID, 1);  in rt2500pci_init_registers()
942 	rt2x00_set_field32(&reg, TXCSR8_BBP_ID3, 12);  in rt2500pci_init_registers()
943 	rt2x00_set_field32(&reg, TXCSR8_BBP_ID3_VALID, 1);  in rt2500pci_init_registers()
947 	rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_1MBS, 112);  in rt2500pci_init_registers()
948 	rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_2MBS, 56);  in rt2500pci_init_registers()
949 	rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_5_5MBS, 20);  in rt2500pci_init_registers()
950 	rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_11MBS, 10);  in rt2500pci_init_registers()
954 	rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_6MBS, 45);  in rt2500pci_init_registers()
955 	rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_9MBS, 37);  in rt2500pci_init_registers()
956 	rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_12MBS, 33);  in rt2500pci_init_registers()
957 	rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_18MBS, 29);  in rt2500pci_init_registers()
961 	rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_24MBS, 29);  in rt2500pci_init_registers()
962 	rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_36MBS, 25);  in rt2500pci_init_registers()
963 	rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_48MBS, 25);  in rt2500pci_init_registers()
964 	rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_54MBS, 25);  in rt2500pci_init_registers()
968 	rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 47); /* CCK Signal */  in rt2500pci_init_registers()
969 	rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);  in rt2500pci_init_registers()
970 	rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 51); /* Rssi */  in rt2500pci_init_registers()
971 	rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);  in rt2500pci_init_registers()
972 	rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 42); /* OFDM Rate */  in rt2500pci_init_registers()
973 	rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);  in rt2500pci_init_registers()
974 	rt2x00_set_field32(&reg, RXCSR3_BBP_ID3, 51); /* RSSI */  in rt2500pci_init_registers()
975 	rt2x00_set_field32(&reg, RXCSR3_BBP_ID3_VALID, 1);  in rt2500pci_init_registers()
979 	rt2x00_set_field32(&reg, PCICSR_BIG_ENDIAN, 0);  in rt2500pci_init_registers()
980 	rt2x00_set_field32(&reg, PCICSR_RX_TRESHOLD, 0);  in rt2500pci_init_registers()
981 	rt2x00_set_field32(&reg, PCICSR_TX_TRESHOLD, 3);  in rt2500pci_init_registers()
982 	rt2x00_set_field32(&reg, PCICSR_BURST_LENTH, 1);  in rt2500pci_init_registers()
983 	rt2x00_set_field32(&reg, PCICSR_ENABLE_CLK, 1);  in rt2500pci_init_registers()
984 	rt2x00_set_field32(&reg, PCICSR_READ_MULTIPLE, 1);  in rt2500pci_init_registers()
985 	rt2x00_set_field32(&reg, PCICSR_WRITE_INVALID, 1);  in rt2500pci_init_registers()
1000 	rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);  in rt2500pci_init_registers()
1004 	rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);  in rt2500pci_init_registers()
1005 	rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 26);  in rt2500pci_init_registers()
1006 	rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID0, 1);  in rt2500pci_init_registers()
1007 	rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);  in rt2500pci_init_registers()
1008 	rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 26);  in rt2500pci_init_registers()
1009 	rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID1, 1);  in rt2500pci_init_registers()
1017 	rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);  in rt2500pci_init_registers()
1018 	rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);  in rt2500pci_init_registers()
1019 	rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);  in rt2500pci_init_registers()
1023 	rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);  in rt2500pci_init_registers()
1024 	rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);  in rt2500pci_init_registers()
1134 	rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);  in rt2500pci_toggle_irq()
1135 	rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);  in rt2500pci_toggle_irq()
1136 	rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);  in rt2500pci_toggle_irq()
1137 	rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);  in rt2500pci_toggle_irq()
1138 	rt2x00_set_field32(&reg, CSR8_RXDONE, mask);  in rt2500pci_toggle_irq()
1186 	rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);  in rt2500pci_set_state()
1187 	rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);  in rt2500pci_set_state()
1188 	rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);  in rt2500pci_set_state()
1189 	rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);  in rt2500pci_set_state()
1259 	rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);  in rt2500pci_write_tx_desc()
1263 	rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER);  in rt2500pci_write_tx_desc()
1264 	rt2x00_set_field32(&word, TXD_W2_AIFS, entry->queue->aifs);  in rt2500pci_write_tx_desc()
1265 	rt2x00_set_field32(&word, TXD_W2_CWMIN, entry->queue->cw_min);  in rt2500pci_write_tx_desc()
1266 	rt2x00_set_field32(&word, TXD_W2_CWMAX, entry->queue->cw_max);  in rt2500pci_write_tx_desc()
1270 	rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->u.plcp.signal);  in rt2500pci_write_tx_desc()
1271 	rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->u.plcp.service);  in rt2500pci_write_tx_desc()
1272 	rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW,  in rt2500pci_write_tx_desc()
1274 	rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH,  in rt2500pci_write_tx_desc()
1279 	rt2x00_set_field32(&word, TXD_W10_RTS,  in rt2500pci_write_tx_desc()
1289 	rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);  in rt2500pci_write_tx_desc()
1290 	rt2x00_set_field32(&word, TXD_W0_VALID, 1);  in rt2500pci_write_tx_desc()
1291 	rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,  in rt2500pci_write_tx_desc()
1293 	rt2x00_set_field32(&word, TXD_W0_ACK,  in rt2500pci_write_tx_desc()
1295 	rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,  in rt2500pci_write_tx_desc()
1297 	rt2x00_set_field32(&word, TXD_W0_OFDM,  in rt2500pci_write_tx_desc()
1299 	rt2x00_set_field32(&word, TXD_W0_CIPHER_OWNER, 1);  in rt2500pci_write_tx_desc()
1300 	rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->u.plcp.ifs);  in rt2500pci_write_tx_desc()
1301 	rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,  in rt2500pci_write_tx_desc()
1303 	rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, txdesc->length);  in rt2500pci_write_tx_desc()
1304 	rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);  in rt2500pci_write_tx_desc()
1328 	rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);  in rt2500pci_write_beacon()
1349 	rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);  in rt2500pci_write_beacon()
1444 	rt2x00_set_field32(&reg, irq_field, 0);  in rt2500pci_enable_interrupt()
1470 		rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, 0);  in rt2500pci_txstatus_tasklet()
1471 		rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, 0);  in rt2500pci_txstatus_tasklet()
1472 		rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, 0);  in rt2500pci_txstatus_tasklet()
1533 		rt2x00_set_field32(&mask, CSR8_TXDONE_TXRING, 1);  in rt2500pci_interrupt()
1534 		rt2x00_set_field32(&mask, CSR8_TXDONE_ATIMRING, 1);  in rt2500pci_interrupt()
1535 		rt2x00_set_field32(&mask, CSR8_TXDONE_PRIORING, 1);  in rt2500pci_interrupt()
1953 	rt2x00_set_field32(&reg, GPIOCSR_DIR0, 1);  in rt2500pci_probe_hw()