Lines Matching refs:rt2x00_set_field32
88 rt2x00_set_field32(&word, TXD_W0_SD_PTR0, skbdesc->skb_dma); in rt2800mmio_write_tx_desc()
92 rt2x00_set_field32(&word, TXD_W1_SD_LEN1, entry->skb->len); in rt2800mmio_write_tx_desc()
93 rt2x00_set_field32(&word, TXD_W1_LAST_SEC1, in rt2800mmio_write_tx_desc()
95 rt2x00_set_field32(&word, TXD_W1_BURST, in rt2800mmio_write_tx_desc()
97 rt2x00_set_field32(&word, TXD_W1_SD_LEN0, txwi_size); in rt2800mmio_write_tx_desc()
98 rt2x00_set_field32(&word, TXD_W1_LAST_SEC0, 0); in rt2800mmio_write_tx_desc()
99 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0); in rt2800mmio_write_tx_desc()
103 rt2x00_set_field32(&word, TXD_W2_SD_PTR1, in rt2800mmio_write_tx_desc()
108 rt2x00_set_field32(&word, TXD_W3_WIV, in rt2800mmio_write_tx_desc()
110 rt2x00_set_field32(&word, TXD_W3_QSEL, 2); in rt2800mmio_write_tx_desc()
208 rt2x00_set_field32(®, irq_field, 1); in rt2800mmio_enable_interrupt()
240 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL, in rt2800mmio_tbtt_tasklet()
245 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL, in rt2800mmio_tbtt_tasklet()
349 rt2x00_set_field32(&mask, INT_MASK_CSR_TX_FIFO_STATUS, 1); in rt2800mmio_interrupt()
399 rt2x00_set_field32(®, INT_MASK_CSR_RX_DONE, 1); in rt2800mmio_toggle_irq()
400 rt2x00_set_field32(®, INT_MASK_CSR_TBTT, 1); in rt2800mmio_toggle_irq()
401 rt2x00_set_field32(®, INT_MASK_CSR_PRE_TBTT, 1); in rt2800mmio_toggle_irq()
402 rt2x00_set_field32(®, INT_MASK_CSR_TX_FIFO_STATUS, 1); in rt2800mmio_toggle_irq()
403 rt2x00_set_field32(®, INT_MASK_CSR_AUTO_WAKEUP, 1); in rt2800mmio_toggle_irq()
432 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 1); in rt2800mmio_start_queue()
437 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_TICKING, 1); in rt2800mmio_start_queue()
438 rt2x00_set_field32(®, BCN_TIME_CFG_TBTT_ENABLE, 1); in rt2800mmio_start_queue()
439 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 1); in rt2800mmio_start_queue()
443 rt2x00_set_field32(®, INT_TIMER_EN_PRE_TBTT_TIMER, 1); in rt2800mmio_start_queue()
535 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 0); in rt2800mmio_stop_queue()
540 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_TICKING, 0); in rt2800mmio_stop_queue()
541 rt2x00_set_field32(®, BCN_TIME_CFG_TBTT_ENABLE, 0); in rt2800mmio_stop_queue()
542 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); in rt2800mmio_stop_queue()
546 rt2x00_set_field32(®, INT_TIMER_EN_PRE_TBTT_TIMER, 0); in rt2800mmio_stop_queue()
636 rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma); in rt2800mmio_clear_entry()
640 rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0); in rt2800mmio_clear_entry()
651 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1); in rt2800mmio_clear_entry()
735 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX0, 1); in rt2800mmio_init_registers()
736 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX1, 1); in rt2800mmio_init_registers()
737 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX2, 1); in rt2800mmio_init_registers()
738 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX3, 1); in rt2800mmio_init_registers()
739 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX4, 1); in rt2800mmio_init_registers()
740 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX5, 1); in rt2800mmio_init_registers()
741 rt2x00_set_field32(®, WPDMA_RST_IDX_DRX_IDX0, 1); in rt2800mmio_init_registers()
756 rt2x00_set_field32(®, AUX_CTRL_FORCE_PCIE_CLK, 1); in rt2800mmio_init_registers()
757 rt2x00_set_field32(®, AUX_CTRL_WAKE_PCIE_EN, 1); in rt2800mmio_init_registers()
764 rt2x00_set_field32(®, MAC_SYS_CTRL_RESET_CSR, 1); in rt2800mmio_init_registers()
765 rt2x00_set_field32(®, MAC_SYS_CTRL_RESET_BBP, 1); in rt2800mmio_init_registers()