Lines Matching refs:rt2x00_set_field32
67 rt2x00_set_field32(®, PHY_CSR3_VALUE, value); in rt61pci_bbp_write()
68 rt2x00_set_field32(®, PHY_CSR3_REGNUM, word); in rt61pci_bbp_write()
69 rt2x00_set_field32(®, PHY_CSR3_BUSY, 1); in rt61pci_bbp_write()
70 rt2x00_set_field32(®, PHY_CSR3_READ_CONTROL, 0); in rt61pci_bbp_write()
96 rt2x00_set_field32(®, PHY_CSR3_REGNUM, word); in rt61pci_bbp_read()
97 rt2x00_set_field32(®, PHY_CSR3_BUSY, 1); in rt61pci_bbp_read()
98 rt2x00_set_field32(®, PHY_CSR3_READ_CONTROL, 1); in rt61pci_bbp_read()
125 rt2x00_set_field32(®, PHY_CSR4_VALUE, value); in rt61pci_rf_write()
126 rt2x00_set_field32(®, PHY_CSR4_NUMBER_OF_BITS, 21); in rt61pci_rf_write()
127 rt2x00_set_field32(®, PHY_CSR4_IF_SELECT, 0); in rt61pci_rf_write()
128 rt2x00_set_field32(®, PHY_CSR4_BUSY, 1); in rt61pci_rf_write()
150 rt2x00_set_field32(®, H2M_MAILBOX_CSR_OWNER, 1); in rt61pci_mcu_request()
151 rt2x00_set_field32(®, H2M_MAILBOX_CSR_CMD_TOKEN, token); in rt61pci_mcu_request()
152 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG0, arg0); in rt61pci_mcu_request()
153 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG1, arg1); in rt61pci_mcu_request()
157 rt2x00_set_field32(®, HOST_CMD_CSR_HOST_COMMAND, command); in rt61pci_mcu_request()
158 rt2x00_set_field32(®, HOST_CMD_CSR_INTERRUPT_MCU, 1); in rt61pci_mcu_request()
186 rt2x00_set_field32(®, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in); in rt61pci_eepromregister_write()
187 rt2x00_set_field32(®, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out); in rt61pci_eepromregister_write()
188 rt2x00_set_field32(®, E2PROM_CSR_DATA_CLOCK, in rt61pci_eepromregister_write()
190 rt2x00_set_field32(®, E2PROM_CSR_CHIP_SELECT, in rt61pci_eepromregister_write()
287 rt2x00_set_field32(®, MAC_CSR14_ON_PERIOD, *delay_on); in rt61pci_blink_set()
288 rt2x00_set_field32(®, MAC_CSR14_OFF_PERIOD, *delay_off); in rt61pci_blink_set()
434 rt2x00_set_field32(®, TXRX_CSR0_DROP_CRC, in rt61pci_config_filter()
436 rt2x00_set_field32(®, TXRX_CSR0_DROP_PHYSICAL, in rt61pci_config_filter()
438 rt2x00_set_field32(®, TXRX_CSR0_DROP_CONTROL, in rt61pci_config_filter()
440 rt2x00_set_field32(®, TXRX_CSR0_DROP_NOT_TO_ME, in rt61pci_config_filter()
442 rt2x00_set_field32(®, TXRX_CSR0_DROP_TO_DS, in rt61pci_config_filter()
445 rt2x00_set_field32(®, TXRX_CSR0_DROP_VERSION_ERROR, 1); in rt61pci_config_filter()
446 rt2x00_set_field32(®, TXRX_CSR0_DROP_MULTICAST, in rt61pci_config_filter()
448 rt2x00_set_field32(®, TXRX_CSR0_DROP_BROADCAST, 0); in rt61pci_config_filter()
449 rt2x00_set_field32(®, TXRX_CSR0_DROP_ACK_CTS, in rt61pci_config_filter()
466 rt2x00_set_field32(®, TXRX_CSR9_TSF_SYNC, conf->sync); in rt61pci_config_intf()
472 rt2x00_set_field32(®, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff); in rt61pci_config_intf()
481 rt2x00_set_field32(®, MAC_CSR5_BSS_ID_MASK, 3); in rt61pci_config_intf()
497 rt2x00_set_field32(®, TXRX_CSR0_RX_ACK_TIMEOUT, 0x32); in rt61pci_config_erp()
498 rt2x00_set_field32(®, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER); in rt61pci_config_erp()
503 rt2x00_set_field32(®, TXRX_CSR4_AUTORESPOND_ENABLE, 1); in rt61pci_config_erp()
504 rt2x00_set_field32(®, TXRX_CSR4_AUTORESPOND_PREAMBLE, in rt61pci_config_erp()
515 rt2x00_set_field32(®, TXRX_CSR9_BEACON_INTERVAL, in rt61pci_config_erp()
522 rt2x00_set_field32(®, MAC_CSR9_SLOT_TIME, erp->slot_time); in rt61pci_config_erp()
526 rt2x00_set_field32(®, MAC_CSR8_SIFS, erp->sifs); in rt61pci_config_erp()
527 rt2x00_set_field32(®, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3); in rt61pci_config_erp()
528 rt2x00_set_field32(®, MAC_CSR8_EIFS, erp->eifs); in rt61pci_config_erp()
624 rt2x00_set_field32(®, MAC_CSR13_DIR4, 0); in rt61pci_config_antenna_2529_rx()
625 rt2x00_set_field32(®, MAC_CSR13_VAL4, p1); in rt61pci_config_antenna_2529_rx()
627 rt2x00_set_field32(®, MAC_CSR13_DIR3, 0); in rt61pci_config_antenna_2529_rx()
628 rt2x00_set_field32(®, MAC_CSR13_VAL3, !p2); in rt61pci_config_antenna_2529_rx()
731 rt2x00_set_field32(®, PHY_CSR0_PA_PE_BG, in rt61pci_config_ant()
733 rt2x00_set_field32(®, PHY_CSR0_PA_PE_A, in rt61pci_config_ant()
780 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower)); in rt61pci_config_channel()
781 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset); in rt61pci_config_channel()
837 rt2x00_set_field32(®, TXRX_CSR4_OFDM_TX_RATE_DOWN, 1); in rt61pci_config_retry_limit()
838 rt2x00_set_field32(®, TXRX_CSR4_OFDM_TX_RATE_STEP, 0); in rt61pci_config_retry_limit()
839 rt2x00_set_field32(®, TXRX_CSR4_OFDM_TX_FALLBACK_CCK, 0); in rt61pci_config_retry_limit()
840 rt2x00_set_field32(®, TXRX_CSR4_LONG_RETRY_LIMIT, in rt61pci_config_retry_limit()
842 rt2x00_set_field32(®, TXRX_CSR4_SHORT_RETRY_LIMIT, in rt61pci_config_retry_limit()
857 rt2x00_set_field32(®, MAC_CSR11_DELAY_AFTER_TBCN, in rt61pci_config_ps()
859 rt2x00_set_field32(®, MAC_CSR11_TBCN_BEFORE_WAKEUP, in rt61pci_config_ps()
861 rt2x00_set_field32(®, MAC_CSR11_WAKEUP_LATENCY, 5); in rt61pci_config_ps()
864 rt2x00_set_field32(®, MAC_CSR11_AUTOWAKE, 0); in rt61pci_config_ps()
867 rt2x00_set_field32(®, MAC_CSR11_AUTOWAKE, 1); in rt61pci_config_ps()
878 rt2x00_set_field32(®, MAC_CSR11_DELAY_AFTER_TBCN, 0); in rt61pci_config_ps()
879 rt2x00_set_field32(®, MAC_CSR11_TBCN_BEFORE_WAKEUP, 0); in rt61pci_config_ps()
880 rt2x00_set_field32(®, MAC_CSR11_AUTOWAKE, 0); in rt61pci_config_ps()
881 rt2x00_set_field32(®, MAC_CSR11_WAKEUP_LATENCY, 0); in rt61pci_config_ps()
1049 rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX, 0); in rt61pci_start_queue()
1054 rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 1); in rt61pci_start_queue()
1055 rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 1); in rt61pci_start_queue()
1056 rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 1); in rt61pci_start_queue()
1072 rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC0, 1); in rt61pci_kick_queue()
1077 rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC1, 1); in rt61pci_kick_queue()
1082 rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC2, 1); in rt61pci_kick_queue()
1087 rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC3, 1); in rt61pci_kick_queue()
1103 rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC0, 1); in rt61pci_stop_queue()
1108 rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC1, 1); in rt61pci_stop_queue()
1113 rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC2, 1); in rt61pci_stop_queue()
1118 rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC3, 1); in rt61pci_stop_queue()
1123 rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX, 1); in rt61pci_stop_queue()
1128 rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 0); in rt61pci_stop_queue()
1129 rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 0); in rt61pci_stop_queue()
1130 rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0); in rt61pci_stop_queue()
1224 rt2x00_set_field32(®, MCU_CNTL_CSR_RESET, 1); in rt61pci_load_firmware()
1234 rt2x00_set_field32(®, MCU_CNTL_CSR_RESET, 1); in rt61pci_load_firmware()
1235 rt2x00_set_field32(®, MCU_CNTL_CSR_SELECT_BANK, 1); in rt61pci_load_firmware()
1241 rt2x00_set_field32(®, MCU_CNTL_CSR_SELECT_BANK, 0); in rt61pci_load_firmware()
1244 rt2x00_set_field32(®, MCU_CNTL_CSR_RESET, 0); in rt61pci_load_firmware()
1268 rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 1); in rt61pci_load_firmware()
1269 rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 1); in rt61pci_load_firmware()
1273 rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 0); in rt61pci_load_firmware()
1274 rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 0); in rt61pci_load_firmware()
1278 rt2x00_set_field32(®, MAC_CSR1_HOST_READY, 1); in rt61pci_load_firmware()
1312 rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS, in rt61pci_clear_entry()
1317 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1); in rt61pci_clear_entry()
1321 rt2x00_set_field32(&word, TXD_W0_VALID, 0); in rt61pci_clear_entry()
1322 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0); in rt61pci_clear_entry()
1336 rt2x00_set_field32(®, TX_RING_CSR0_AC0_RING_SIZE, in rt61pci_init_queues()
1338 rt2x00_set_field32(®, TX_RING_CSR0_AC1_RING_SIZE, in rt61pci_init_queues()
1340 rt2x00_set_field32(®, TX_RING_CSR0_AC2_RING_SIZE, in rt61pci_init_queues()
1342 rt2x00_set_field32(®, TX_RING_CSR0_AC3_RING_SIZE, in rt61pci_init_queues()
1347 rt2x00_set_field32(®, TX_RING_CSR1_TXD_SIZE, in rt61pci_init_queues()
1353 rt2x00_set_field32(®, AC0_BASE_CSR_RING_REGISTER, in rt61pci_init_queues()
1359 rt2x00_set_field32(®, AC1_BASE_CSR_RING_REGISTER, in rt61pci_init_queues()
1365 rt2x00_set_field32(®, AC2_BASE_CSR_RING_REGISTER, in rt61pci_init_queues()
1371 rt2x00_set_field32(®, AC3_BASE_CSR_RING_REGISTER, in rt61pci_init_queues()
1376 rt2x00_set_field32(®, RX_RING_CSR_RING_SIZE, rt2x00dev->rx->limit); in rt61pci_init_queues()
1377 rt2x00_set_field32(®, RX_RING_CSR_RXD_SIZE, in rt61pci_init_queues()
1379 rt2x00_set_field32(®, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4); in rt61pci_init_queues()
1384 rt2x00_set_field32(®, RX_BASE_CSR_RING_REGISTER, in rt61pci_init_queues()
1389 rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC0, 2); in rt61pci_init_queues()
1390 rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC1, 2); in rt61pci_init_queues()
1391 rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC2, 2); in rt61pci_init_queues()
1392 rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC3, 2); in rt61pci_init_queues()
1396 rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC0, 1); in rt61pci_init_queues()
1397 rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1); in rt61pci_init_queues()
1398 rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1); in rt61pci_init_queues()
1399 rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1); in rt61pci_init_queues()
1403 rt2x00_set_field32(®, RX_CNTL_CSR_LOAD_RXD, 1); in rt61pci_init_queues()
1414 rt2x00_set_field32(®, TXRX_CSR0_AUTO_TX_SEQ, 1); in rt61pci_init_registers()
1415 rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX, 0); in rt61pci_init_registers()
1416 rt2x00_set_field32(®, TXRX_CSR0_TX_WITHOUT_WAITING, 0); in rt61pci_init_registers()
1420 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */ in rt61pci_init_registers()
1421 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID0_VALID, 1); in rt61pci_init_registers()
1422 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID1, 30); /* Rssi */ in rt61pci_init_registers()
1423 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID1_VALID, 1); in rt61pci_init_registers()
1424 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */ in rt61pci_init_registers()
1425 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID2_VALID, 1); in rt61pci_init_registers()
1426 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID3, 30); /* Rssi */ in rt61pci_init_registers()
1427 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID3_VALID, 1); in rt61pci_init_registers()
1434 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID0, 13); in rt61pci_init_registers()
1435 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID0_VALID, 1); in rt61pci_init_registers()
1436 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID1, 12); in rt61pci_init_registers()
1437 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID1_VALID, 1); in rt61pci_init_registers()
1438 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID2, 11); in rt61pci_init_registers()
1439 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID2_VALID, 1); in rt61pci_init_registers()
1440 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID3, 10); in rt61pci_init_registers()
1441 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID3_VALID, 1); in rt61pci_init_registers()
1448 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID0, 7); in rt61pci_init_registers()
1449 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID0_VALID, 1); in rt61pci_init_registers()
1450 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID1, 6); in rt61pci_init_registers()
1451 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID1_VALID, 1); in rt61pci_init_registers()
1452 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID2, 5); in rt61pci_init_registers()
1453 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID2_VALID, 1); in rt61pci_init_registers()
1457 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_6MBS, 59); in rt61pci_init_registers()
1458 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_9MBS, 53); in rt61pci_init_registers()
1459 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_12MBS, 49); in rt61pci_init_registers()
1460 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_18MBS, 46); in rt61pci_init_registers()
1464 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_24MBS, 44); in rt61pci_init_registers()
1465 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_36MBS, 42); in rt61pci_init_registers()
1466 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_48MBS, 42); in rt61pci_init_registers()
1467 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_54MBS, 42); in rt61pci_init_registers()
1471 rt2x00_set_field32(®, TXRX_CSR9_BEACON_INTERVAL, 0); in rt61pci_init_registers()
1472 rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 0); in rt61pci_init_registers()
1473 rt2x00_set_field32(®, TXRX_CSR9_TSF_SYNC, 0); in rt61pci_init_registers()
1474 rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 0); in rt61pci_init_registers()
1475 rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0); in rt61pci_init_registers()
1476 rt2x00_set_field32(®, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0); in rt61pci_init_registers()
1484 rt2x00_set_field32(®, MAC_CSR9_CW_SELECT, 0); in rt61pci_init_registers()
1537 rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 1); in rt61pci_init_registers()
1538 rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 1); in rt61pci_init_registers()
1542 rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 0); in rt61pci_init_registers()
1543 rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 0); in rt61pci_init_registers()
1547 rt2x00_set_field32(®, MAC_CSR1_HOST_READY, 1); in rt61pci_init_registers()
1646 rt2x00_set_field32(®, INT_MASK_CSR_TXDONE, mask); in rt61pci_toggle_irq()
1647 rt2x00_set_field32(®, INT_MASK_CSR_RXDONE, mask); in rt61pci_toggle_irq()
1648 rt2x00_set_field32(®, INT_MASK_CSR_BEACON_DONE, mask); in rt61pci_toggle_irq()
1649 rt2x00_set_field32(®, INT_MASK_CSR_ENABLE_MITIGATION, mask); in rt61pci_toggle_irq()
1650 rt2x00_set_field32(®, INT_MASK_CSR_MITIGATION_PERIOD, 0xff); in rt61pci_toggle_irq()
1654 rt2x00_set_field32(®, MCU_INT_MASK_CSR_0, mask); in rt61pci_toggle_irq()
1655 rt2x00_set_field32(®, MCU_INT_MASK_CSR_1, mask); in rt61pci_toggle_irq()
1656 rt2x00_set_field32(®, MCU_INT_MASK_CSR_2, mask); in rt61pci_toggle_irq()
1657 rt2x00_set_field32(®, MCU_INT_MASK_CSR_3, mask); in rt61pci_toggle_irq()
1658 rt2x00_set_field32(®, MCU_INT_MASK_CSR_4, mask); in rt61pci_toggle_irq()
1659 rt2x00_set_field32(®, MCU_INT_MASK_CSR_5, mask); in rt61pci_toggle_irq()
1660 rt2x00_set_field32(®, MCU_INT_MASK_CSR_6, mask); in rt61pci_toggle_irq()
1661 rt2x00_set_field32(®, MCU_INT_MASK_CSR_7, mask); in rt61pci_toggle_irq()
1662 rt2x00_set_field32(®, MCU_INT_MASK_CSR_TWAKEUP, mask); in rt61pci_toggle_irq()
1694 rt2x00_set_field32(®, RX_CNTL_CSR_ENABLE_RX_DMA, 1); in rt61pci_enable_radio()
1717 rt2x00_set_field32(®, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep); in rt61pci_set_state()
1718 rt2x00_set_field32(®, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep); in rt61pci_set_state()
1787 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, entry->queue->qid); in rt61pci_write_tx_desc()
1788 rt2x00_set_field32(&word, TXD_W1_AIFSN, entry->queue->aifs); in rt61pci_write_tx_desc()
1789 rt2x00_set_field32(&word, TXD_W1_CWMIN, entry->queue->cw_min); in rt61pci_write_tx_desc()
1790 rt2x00_set_field32(&word, TXD_W1_CWMAX, entry->queue->cw_max); in rt61pci_write_tx_desc()
1791 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset); in rt61pci_write_tx_desc()
1792 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE, in rt61pci_write_tx_desc()
1794 rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1); in rt61pci_write_tx_desc()
1798 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->u.plcp.signal); in rt61pci_write_tx_desc()
1799 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->u.plcp.service); in rt61pci_write_tx_desc()
1800 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, in rt61pci_write_tx_desc()
1802 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, in rt61pci_write_tx_desc()
1812 rt2x00_set_field32(&word, TXD_W5_PID_TYPE, entry->queue->qid); in rt61pci_write_tx_desc()
1813 rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE, entry->entry_idx); in rt61pci_write_tx_desc()
1814 rt2x00_set_field32(&word, TXD_W5_TX_POWER, in rt61pci_write_tx_desc()
1816 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1); in rt61pci_write_tx_desc()
1821 rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS, in rt61pci_write_tx_desc()
1826 rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0, in rt61pci_write_tx_desc()
1837 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1); in rt61pci_write_tx_desc()
1838 rt2x00_set_field32(&word, TXD_W0_VALID, 1); in rt61pci_write_tx_desc()
1839 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG, in rt61pci_write_tx_desc()
1841 rt2x00_set_field32(&word, TXD_W0_ACK, in rt61pci_write_tx_desc()
1843 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP, in rt61pci_write_tx_desc()
1845 rt2x00_set_field32(&word, TXD_W0_OFDM, in rt61pci_write_tx_desc()
1847 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->u.plcp.ifs); in rt61pci_write_tx_desc()
1848 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE, in rt61pci_write_tx_desc()
1850 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, in rt61pci_write_tx_desc()
1852 rt2x00_set_field32(&word, TXD_W0_KEY_TABLE, in rt61pci_write_tx_desc()
1854 rt2x00_set_field32(&word, TXD_W0_KEY_INDEX, txdesc->key_idx); in rt61pci_write_tx_desc()
1855 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, txdesc->length); in rt61pci_write_tx_desc()
1856 rt2x00_set_field32(&word, TXD_W0_BURST, in rt61pci_write_tx_desc()
1858 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, txdesc->cipher); in rt61pci_write_tx_desc()
1887 rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0); in rt61pci_write_beacon()
1927 rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 1); in rt61pci_write_beacon()
1948 rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0); in rt61pci_clear_beacon()
2169 rt2x00_set_field32(®, irq_field, 0); in rt61pci_enable_interrupt()
2187 rt2x00_set_field32(®, irq_field, 0); in rt61pci_enable_mcu_interrupt()
2765 rt2x00_set_field32(®, MAC_CSR13_DIR5, 1); in rt61pci_probe_hw()
2837 rt2x00_set_field32(®, field, queue->txop); in rt61pci_conf_tx()
2845 rt2x00_set_field32(®, field, queue->aifs); in rt61pci_conf_tx()
2849 rt2x00_set_field32(®, field, queue->cw_min); in rt61pci_conf_tx()
2853 rt2x00_set_field32(®, field, queue->cw_max); in rt61pci_conf_tx()