Lines Matching refs:MASKDWORD
225 if (bitmask != MASKDWORD) { in rtl92d_phy_set_bb_reg()
258 tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD); in _rtl92d_phy_rf_serial_read()
262 tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD); in _rtl92d_phy_rf_serial_read()
265 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, in _rtl92d_phy_rf_serial_read()
268 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2); in _rtl92d_phy_rf_serial_read()
271 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, in _rtl92d_phy_rf_serial_read()
304 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr); in _rtl92d_phy_rf_serial_write()
549 rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD, in _rtl92d_phy_config_bb_with_headerfile()
561 MASKDWORD, in _rtl92d_phy_config_bb_with_headerfile()
577 MASKDWORD, in _rtl92d_phy_config_bb_with_headerfile()
593 MASKDWORD, in _rtl92d_phy_config_bb_with_headerfile()
844 MASKDWORD); in rtl92d_phy_get_hw_reg_originalvalue()
1394 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c1f); in _rtl92d_phy_patha_iqk()
1395 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c1f); in _rtl92d_phy_patha_iqk()
1397 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c22); in _rtl92d_phy_patha_iqk()
1398 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c22); in _rtl92d_phy_patha_iqk()
1400 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140102); in _rtl92d_phy_patha_iqk()
1401 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x28160206); in _rtl92d_phy_patha_iqk()
1404 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x10008c22); in _rtl92d_phy_patha_iqk()
1405 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x10008c22); in _rtl92d_phy_patha_iqk()
1406 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140102); in _rtl92d_phy_patha_iqk()
1407 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x28160206); in _rtl92d_phy_patha_iqk()
1411 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911); in _rtl92d_phy_patha_iqk()
1414 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000); in _rtl92d_phy_patha_iqk()
1415 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000); in _rtl92d_phy_patha_iqk()
1422 regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); in _rtl92d_phy_patha_iqk()
1424 rege94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD); in _rtl92d_phy_patha_iqk()
1426 rege9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD); in _rtl92d_phy_patha_iqk()
1428 regea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD); in _rtl92d_phy_patha_iqk()
1464 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x18008c1f); in _rtl92d_phy_patha_iqk_5g_normal()
1465 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x18008c1f); in _rtl92d_phy_patha_iqk_5g_normal()
1466 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140307); in _rtl92d_phy_patha_iqk_5g_normal()
1467 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x68160960); in _rtl92d_phy_patha_iqk_5g_normal()
1470 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x18008c2f); in _rtl92d_phy_patha_iqk_5g_normal()
1471 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x18008c2f); in _rtl92d_phy_patha_iqk_5g_normal()
1472 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82110000); in _rtl92d_phy_patha_iqk_5g_normal()
1473 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x68110000); in _rtl92d_phy_patha_iqk_5g_normal()
1477 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911); in _rtl92d_phy_patha_iqk_5g_normal()
1479 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 0x07000f60); in _rtl92d_phy_patha_iqk_5g_normal()
1480 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, MASKDWORD, 0x66e60e30); in _rtl92d_phy_patha_iqk_5g_normal()
1485 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000); in _rtl92d_phy_patha_iqk_5g_normal()
1486 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000); in _rtl92d_phy_patha_iqk_5g_normal()
1493 regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); in _rtl92d_phy_patha_iqk_5g_normal()
1495 rege94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD); in _rtl92d_phy_patha_iqk_5g_normal()
1497 rege9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD); in _rtl92d_phy_patha_iqk_5g_normal()
1499 regea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD); in _rtl92d_phy_patha_iqk_5g_normal()
1521 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, in _rtl92d_phy_patha_iqk_5g_normal()
1523 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, MASKDWORD, in _rtl92d_phy_patha_iqk_5g_normal()
1538 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000002); in _rtl92d_phy_pathb_iqk()
1539 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000000); in _rtl92d_phy_pathb_iqk()
1545 regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); in _rtl92d_phy_pathb_iqk()
1547 regeb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD); in _rtl92d_phy_pathb_iqk()
1549 regebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD); in _rtl92d_phy_pathb_iqk()
1551 regec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD); in _rtl92d_phy_pathb_iqk()
1553 regecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD); in _rtl92d_phy_pathb_iqk()
1581 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x18008c1f); in _rtl92d_phy_pathb_iqk_5g_normal()
1582 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x18008c1f); in _rtl92d_phy_pathb_iqk_5g_normal()
1583 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82110000); in _rtl92d_phy_pathb_iqk_5g_normal()
1584 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x68110000); in _rtl92d_phy_pathb_iqk_5g_normal()
1587 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x18008c2f); in _rtl92d_phy_pathb_iqk_5g_normal()
1588 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x18008c2f); in _rtl92d_phy_pathb_iqk_5g_normal()
1589 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140307); in _rtl92d_phy_pathb_iqk_5g_normal()
1590 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x68160960); in _rtl92d_phy_pathb_iqk_5g_normal()
1594 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911); in _rtl92d_phy_pathb_iqk_5g_normal()
1597 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 0x0f600700); in _rtl92d_phy_pathb_iqk_5g_normal()
1598 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, MASKDWORD, 0x061f0d30); in _rtl92d_phy_pathb_iqk_5g_normal()
1604 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xfa000000); in _rtl92d_phy_pathb_iqk_5g_normal()
1605 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000); in _rtl92d_phy_pathb_iqk_5g_normal()
1613 regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); in _rtl92d_phy_pathb_iqk_5g_normal()
1615 regeb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD); in _rtl92d_phy_pathb_iqk_5g_normal()
1617 regebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD); in _rtl92d_phy_pathb_iqk_5g_normal()
1619 regec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD); in _rtl92d_phy_pathb_iqk_5g_normal()
1621 regecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD); in _rtl92d_phy_pathb_iqk_5g_normal()
1639 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, in _rtl92d_phy_pathb_iqk_5g_normal()
1641 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, MASKDWORD, in _rtl92d_phy_pathb_iqk_5g_normal()
1655 adda_backup[i] = rtl_get_bbreg(hw, adda_reg[i], MASKDWORD); in _rtl92d_phy_save_adda_registers()
1680 rtl_set_bbreg(hw, adda_reg[i], MASKDWORD, adda_backup[i]); in _rtl92d_phy_reload_adda_registers()
1708 rtl_set_bbreg(hw, adda_reg[i], MASKDWORD, pathon); in _rtl92d_phy_path_adda_on()
1731 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0); in _rtl92d_phy_patha_standby()
1732 rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, MASKDWORD, 0x00010000); in _rtl92d_phy_patha_standby()
1733 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); in _rtl92d_phy_patha_standby()
1744 rtl_set_bbreg(hw, 0x820, MASKDWORD, mode); in _rtl92d_phy_pimode_switch()
1745 rtl_set_bbreg(hw, 0x828, MASKDWORD, mode); in _rtl92d_phy_pimode_switch()
1776 bbvalue = rtl_get_bbreg(hw, RFPGA0_RFMOD, MASKDWORD); in _rtl92d_phy_iq_calibrate()
1799 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600); in _rtl92d_phy_iq_calibrate()
1800 rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4); in _rtl92d_phy_iq_calibrate()
1801 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22204000); in _rtl92d_phy_iq_calibrate()
1804 rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, MASKDWORD, in _rtl92d_phy_iq_calibrate()
1806 rtl_set_bbreg(hw, RFPGA0_XB_LSSIPARAMETER, MASKDWORD, in _rtl92d_phy_iq_calibrate()
1813 rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x0f600000); in _rtl92d_phy_iq_calibrate()
1815 rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x0f600000); in _rtl92d_phy_iq_calibrate()
1818 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); in _rtl92d_phy_iq_calibrate()
1819 rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x01007c00); in _rtl92d_phy_iq_calibrate()
1820 rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800); in _rtl92d_phy_iq_calibrate()
1826 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) & in _rtl92d_phy_iq_calibrate()
1828 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & in _rtl92d_phy_iq_calibrate()
1830 result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) & in _rtl92d_phy_iq_calibrate()
1832 result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) & in _rtl92d_phy_iq_calibrate()
1840 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) & in _rtl92d_phy_iq_calibrate()
1842 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & in _rtl92d_phy_iq_calibrate()
1858 MASKDWORD) & 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate()
1860 MASKDWORD) & 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate()
1862 MASKDWORD) & 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate()
1864 MASKDWORD) & 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate()
1871 MASKDWORD) & 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate()
1873 MASKDWORD) & 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate()
1885 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0); in _rtl92d_phy_iq_calibrate()
1905 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x01008c00); in _rtl92d_phy_iq_calibrate()
1906 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x01008c00); in _rtl92d_phy_iq_calibrate()
1943 bbvalue = rtl_get_bbreg(hw, RFPGA0_RFMOD, MASKDWORD); in _rtl92d_phy_iq_calibrate_5g_normal()
1973 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600); in _rtl92d_phy_iq_calibrate_5g_normal()
1974 rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4); in _rtl92d_phy_iq_calibrate_5g_normal()
1975 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22208000); in _rtl92d_phy_iq_calibrate_5g_normal()
1979 rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x0f600000); in _rtl92d_phy_iq_calibrate_5g_normal()
1981 rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x0f600000); in _rtl92d_phy_iq_calibrate_5g_normal()
1984 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); in _rtl92d_phy_iq_calibrate_5g_normal()
1985 rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x10007c00); in _rtl92d_phy_iq_calibrate_5g_normal()
1986 rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800); in _rtl92d_phy_iq_calibrate_5g_normal()
1990 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
1992 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
1994 result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
1996 result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
2002 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
2004 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
2017 result[t][4] = (rtl_get_bbreg(hw, 0xeb4, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
2019 result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
2021 result[t][6] = (rtl_get_bbreg(hw, 0xec4, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
2023 result[t][7] = (rtl_get_bbreg(hw, 0xecc, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
2028 result[t][4] = (rtl_get_bbreg(hw, 0xeb4, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
2030 result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
2041 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0); in _rtl92d_phy_iq_calibrate_5g_normal()
2141 MASKDWORD) >> 22) & 0x3FF; /* OFDM0_D */ in _rtl92d_phy_patha_fill_iqk_matrix()
2172 MASKDWORD)); in _rtl92d_phy_patha_fill_iqk_matrix()
2200 MASKDWORD) >> 22) & 0x3FF; in _rtl92d_phy_pathb_fill_iqk_matrix()
2854 MASKDWORD); in rtl92d_phy_sw_chnl()
3353 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, MASKDWORD, in rtl92d_update_bbrf_configuration()
3355 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, MASKDWORD, in rtl92d_update_bbrf_configuration()
3409 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, MASKDWORD, in rtl92d_update_bbrf_configuration()
3412 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, MASKDWORD, in rtl92d_update_bbrf_configuration()
3415 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, MASKDWORD, in rtl92d_update_bbrf_configuration()
3418 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, MASKDWORD, in rtl92d_update_bbrf_configuration()
3445 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, MASKDWORD, 0x40000100); in rtl92d_update_bbrf_configuration()
3446 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, MASKDWORD, 0x40000100); in rtl92d_update_bbrf_configuration()