Lines Matching refs:MASKDWORD
69 if (bitmask != MASKDWORD) { in rtl92ee_phy_set_bb_reg()
152 tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD); in _rtl92ee_phy_rf_serial_read()
156 tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD); in _rtl92ee_phy_rf_serial_read()
159 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, in _rtl92ee_phy_rf_serial_read()
161 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2); in _rtl92ee_phy_rf_serial_read()
198 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr); in _rtl92ee_phy_rf_serial_write()
295 getvalue = rtl_get_rfreg(hw, rfpath, addr, MASKDWORD); in _rtl92ee_config_rf_reg()
304 MASKDWORD); in _rtl92ee_config_rf_reg()
314 getvalue = rtl_get_rfreg(hw, rfpath, addr, MASKDWORD); in _rtl92ee_config_rf_reg()
326 MASKDWORD); in _rtl92ee_config_rf_reg()
370 rtl_set_bbreg(hw, addr, MASKDWORD , data); in _rtl92ee_config_bb_reg()
733 rtl_set_bbreg(hw, array[i], MASKDWORD, in phy_config_bb_with_hdr_file()
763 MASKDWORD, in phy_config_bb_with_hdr_file()
1034 ROFDM0_RXDETECTOR2, MASKDWORD); in rtl92ee_phy_get_hw_reg_originalvalue()
1942 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl92ee_phy_path_a_iqk()
1944 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); in _rtl92ee_phy_path_a_iqk()
1946 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1c); in _rtl92ee_phy_path_a_iqk()
1947 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_a_iqk()
1948 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_a_iqk()
1949 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_a_iqk()
1951 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82140303); in _rtl92ee_phy_path_a_iqk()
1952 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x68160000); in _rtl92ee_phy_path_a_iqk()
1955 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x00462911); in _rtl92ee_phy_path_a_iqk()
1958 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000); in _rtl92ee_phy_path_a_iqk()
1959 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); in _rtl92ee_phy_path_a_iqk()
1963 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); in _rtl92ee_phy_path_a_iqk()
1964 reg_e94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD); in _rtl92ee_phy_path_a_iqk()
1965 reg_e9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD); in _rtl92ee_phy_path_a_iqk()
1983 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl92ee_phy_path_b_iqk()
1985 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); in _rtl92ee_phy_path_b_iqk()
1987 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x00000000); in _rtl92ee_phy_path_b_iqk()
1988 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); in _rtl92ee_phy_path_b_iqk()
1990 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_b_iqk()
1991 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_b_iqk()
1992 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x18008c1c); in _rtl92ee_phy_path_b_iqk()
1993 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_b_iqk()
1995 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x821403e2); in _rtl92ee_phy_path_b_iqk()
1996 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x68160000); in _rtl92ee_phy_path_b_iqk()
1999 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x00462911); in _rtl92ee_phy_path_b_iqk()
2002 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xfa000000); in _rtl92ee_phy_path_b_iqk()
2003 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); in _rtl92ee_phy_path_b_iqk()
2007 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); in _rtl92ee_phy_path_b_iqk()
2008 reg_eb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD); in _rtl92ee_phy_path_b_iqk()
2009 reg_ebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD); in _rtl92ee_phy_path_b_iqk()
2028 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl92ee_phy_path_a_rx_iqk()
2040 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); in _rtl92ee_phy_path_a_rx_iqk()
2043 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00); in _rtl92ee_phy_path_a_rx_iqk()
2044 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); in _rtl92ee_phy_path_a_rx_iqk()
2047 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1c); in _rtl92ee_phy_path_a_rx_iqk()
2048 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_a_rx_iqk()
2049 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_a_rx_iqk()
2050 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_a_rx_iqk()
2052 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82160c1f); in _rtl92ee_phy_path_a_rx_iqk()
2053 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x68160c1f); in _rtl92ee_phy_path_a_rx_iqk()
2056 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a911); in _rtl92ee_phy_path_a_rx_iqk()
2059 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xfa000000); in _rtl92ee_phy_path_a_rx_iqk()
2060 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); in _rtl92ee_phy_path_a_rx_iqk()
2065 reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD); in _rtl92ee_phy_path_a_rx_iqk()
2066 reg_e94 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, MASKDWORD); in _rtl92ee_phy_path_a_rx_iqk()
2067 reg_e9c = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, MASKDWORD); in _rtl92ee_phy_path_a_rx_iqk()
2075 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl92ee_phy_path_a_rx_iqk()
2082 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, u32temp); in _rtl92ee_phy_path_a_rx_iqk()
2085 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl92ee_phy_path_a_rx_iqk()
2098 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); in _rtl92ee_phy_path_a_rx_iqk()
2101 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); in _rtl92ee_phy_path_a_rx_iqk()
2104 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_a_rx_iqk()
2105 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x18008c1c); in _rtl92ee_phy_path_a_rx_iqk()
2106 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_a_rx_iqk()
2107 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_a_rx_iqk()
2109 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82160c1f); in _rtl92ee_phy_path_a_rx_iqk()
2110 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28160c1f); in _rtl92ee_phy_path_a_rx_iqk()
2113 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a891); in _rtl92ee_phy_path_a_rx_iqk()
2115 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xfa000000); in _rtl92ee_phy_path_a_rx_iqk()
2116 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); in _rtl92ee_phy_path_a_rx_iqk()
2120 reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD); in _rtl92ee_phy_path_a_rx_iqk()
2121 reg_ea4 = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_A_2, MASKDWORD); in _rtl92ee_phy_path_a_rx_iqk()
2125 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl92ee_phy_path_a_rx_iqk()
2144 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl92ee_phy_path_b_rx_iqk()
2155 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); in _rtl92ee_phy_path_b_rx_iqk()
2158 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00); in _rtl92ee_phy_path_b_rx_iqk()
2159 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); in _rtl92ee_phy_path_b_rx_iqk()
2162 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_b_rx_iqk()
2163 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_b_rx_iqk()
2164 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x18008c1c); in _rtl92ee_phy_path_b_rx_iqk()
2165 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_b_rx_iqk()
2167 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82160c1f); in _rtl92ee_phy_path_b_rx_iqk()
2168 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x68160c1f); in _rtl92ee_phy_path_b_rx_iqk()
2171 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a911); in _rtl92ee_phy_path_b_rx_iqk()
2174 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xfa000000); in _rtl92ee_phy_path_b_rx_iqk()
2175 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); in _rtl92ee_phy_path_b_rx_iqk()
2180 reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD); in _rtl92ee_phy_path_b_rx_iqk()
2181 reg_eb4 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_B, MASKDWORD); in _rtl92ee_phy_path_b_rx_iqk()
2182 reg_ebc = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_B, MASKDWORD); in _rtl92ee_phy_path_b_rx_iqk()
2190 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl92ee_phy_path_b_rx_iqk()
2197 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, u32temp); in _rtl92ee_phy_path_b_rx_iqk()
2200 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl92ee_phy_path_b_rx_iqk()
2212 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); in _rtl92ee_phy_path_b_rx_iqk()
2215 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); in _rtl92ee_phy_path_b_rx_iqk()
2218 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_b_rx_iqk()
2219 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_b_rx_iqk()
2220 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_b_rx_iqk()
2221 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x18008c1c); in _rtl92ee_phy_path_b_rx_iqk()
2223 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82160c1f); in _rtl92ee_phy_path_b_rx_iqk()
2224 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28160c1f); in _rtl92ee_phy_path_b_rx_iqk()
2227 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a891); in _rtl92ee_phy_path_b_rx_iqk()
2229 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xfa000000); in _rtl92ee_phy_path_b_rx_iqk()
2230 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); in _rtl92ee_phy_path_b_rx_iqk()
2234 reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD); in _rtl92ee_phy_path_b_rx_iqk()
2235 reg_ec4 = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_B_2, MASKDWORD); in _rtl92ee_phy_path_b_rx_iqk()
2236 reg_ecc = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_B_2, MASKDWORD); in _rtl92ee_phy_path_b_rx_iqk()
2239 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl92ee_phy_path_b_rx_iqk()
2264 MASKDWORD) >> 22) & 0x3FF; in _rtl92ee_phy_path_a_fill_iqk_matrix()
2309 MASKDWORD) >> 22) & 0x3FF; in _rtl92ee_phy_path_b_fill_iqk_matrix()
2349 addabackup[i] = rtl_get_bbreg(hw, addareg[i], MASKDWORD); in _rtl92ee_phy_save_adda_registers()
2371 rtl_set_bbreg(hw, addareg[i], MASKDWORD, addabackup[i]); in _rtl92ee_phy_reload_adda_registers()
2391 rtl_set_bbreg(hw, addareg[i], MASKDWORD, 0x0fc01616); in _rtl92ee_phy_path_adda_on()
2402 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0); in _rtl92ee_phy_path_a_standby()
2404 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); in _rtl92ee_phy_path_a_standby()
2523 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600); in _rtl92ee_phy_iq_calibrate()
2524 rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4); in _rtl92ee_phy_iq_calibrate()
2525 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22208200); in _rtl92ee_phy_iq_calibrate()
2536 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); in _rtl92ee_phy_iq_calibrate()
2537 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00); in _rtl92ee_phy_iq_calibrate()
2538 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); in _rtl92ee_phy_iq_calibrate()
2548 MASKDWORD) & 0x3FF0000) in _rtl92ee_phy_iq_calibrate()
2551 MASKDWORD) & 0x3FF0000) in _rtl92ee_phy_iq_calibrate()
2568 MASKDWORD) & 0x3FF0000) in _rtl92ee_phy_iq_calibrate()
2572 MASKDWORD) & 0x3FF0000) in _rtl92ee_phy_iq_calibrate()
2590 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); in _rtl92ee_phy_iq_calibrate()
2591 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00); in _rtl92ee_phy_iq_calibrate()
2592 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); in _rtl92ee_phy_iq_calibrate()
2601 MASKDWORD) & 0x3FF0000) in _rtl92ee_phy_iq_calibrate()
2605 MASKDWORD) & 0x3FF0000) in _rtl92ee_phy_iq_calibrate()
2621 MASKDWORD) & 0x3FF0000) in _rtl92ee_phy_iq_calibrate()
2625 MASKDWORD) & 0x3FF0000) in _rtl92ee_phy_iq_calibrate()
2641 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0); in _rtl92ee_phy_iq_calibrate()
2666 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x01008c00); in _rtl92ee_phy_iq_calibrate()
2667 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x01008c00); in _rtl92ee_phy_iq_calibrate()