Lines Matching refs:MASKDWORD
272 rtl_set_bbreg(hw, addr, MASKDWORD, data); in _rtl8723be_config_bb_reg()
796 MASKDWORD); in rtl8723be_phy_get_hw_reg_originalvalue()
1451 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl8723be_phy_path_a_iqk()
1453 rtl_set_bbreg(hw, 0x948, MASKDWORD, 0x00000000); in _rtl8723be_phy_path_a_iqk()
1463 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00); in _rtl8723be_phy_path_a_iqk()
1464 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); in _rtl8723be_phy_path_a_iqk()
1466 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1c); in _rtl8723be_phy_path_a_iqk()
1467 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c); in _rtl8723be_phy_path_a_iqk()
1468 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl8723be_phy_path_a_iqk()
1469 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl8723be_phy_path_a_iqk()
1471 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x821403ea); in _rtl8723be_phy_path_a_iqk()
1472 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28160000); in _rtl8723be_phy_path_a_iqk()
1473 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82110000); in _rtl8723be_phy_path_a_iqk()
1474 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28110000); in _rtl8723be_phy_path_a_iqk()
1476 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x00462911); in _rtl8723be_phy_path_a_iqk()
1478 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); in _rtl8723be_phy_path_a_iqk()
1481 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000); in _rtl8723be_phy_path_a_iqk()
1482 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); in _rtl8723be_phy_path_a_iqk()
1487 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl8723be_phy_path_a_iqk()
1490 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); in _rtl8723be_phy_path_a_iqk()
1491 reg_e94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD); in _rtl8723be_phy_path_a_iqk()
1492 reg_e9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD); in _rtl8723be_phy_path_a_iqk()
1524 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl8723be_phy_path_a_rx_iqk()
1527 rtl_set_bbreg(hw, 0x948, MASKDWORD, 0x00000000); in _rtl8723be_phy_path_a_rx_iqk()
1536 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); in _rtl8723be_phy_path_a_rx_iqk()
1539 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00); in _rtl8723be_phy_path_a_rx_iqk()
1540 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); in _rtl8723be_phy_path_a_rx_iqk()
1543 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1c); in _rtl8723be_phy_path_a_rx_iqk()
1544 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c); in _rtl8723be_phy_path_a_rx_iqk()
1545 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl8723be_phy_path_a_rx_iqk()
1546 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl8723be_phy_path_a_rx_iqk()
1548 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82160ff0); in _rtl8723be_phy_path_a_rx_iqk()
1549 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28110000); in _rtl8723be_phy_path_a_rx_iqk()
1550 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82110000); in _rtl8723be_phy_path_a_rx_iqk()
1551 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28110000); in _rtl8723be_phy_path_a_rx_iqk()
1554 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a911); in _rtl8723be_phy_path_a_rx_iqk()
1557 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); in _rtl8723be_phy_path_a_rx_iqk()
1560 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000); in _rtl8723be_phy_path_a_rx_iqk()
1561 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); in _rtl8723be_phy_path_a_rx_iqk()
1566 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl8723be_phy_path_a_rx_iqk()
1569 reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD); in _rtl8723be_phy_path_a_rx_iqk()
1570 reg_e94 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, MASKDWORD); in _rtl8723be_phy_path_a_rx_iqk()
1571 reg_e9c = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, MASKDWORD); in _rtl8723be_phy_path_a_rx_iqk()
1595 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, u32tmp); in _rtl8723be_phy_path_a_rx_iqk()
1599 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl8723be_phy_path_a_rx_iqk()
1611 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); in _rtl8723be_phy_path_a_rx_iqk()
1614 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c); in _rtl8723be_phy_path_a_rx_iqk()
1615 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x18008c1c); in _rtl8723be_phy_path_a_rx_iqk()
1616 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl8723be_phy_path_a_rx_iqk()
1617 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl8723be_phy_path_a_rx_iqk()
1619 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82110000); in _rtl8723be_phy_path_a_rx_iqk()
1620 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x2816001f); in _rtl8723be_phy_path_a_rx_iqk()
1621 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82110000); in _rtl8723be_phy_path_a_rx_iqk()
1622 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28110000); in _rtl8723be_phy_path_a_rx_iqk()
1625 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a8d1); in _rtl8723be_phy_path_a_rx_iqk()
1628 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); in _rtl8723be_phy_path_a_rx_iqk()
1631 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000); in _rtl8723be_phy_path_a_rx_iqk()
1632 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); in _rtl8723be_phy_path_a_rx_iqk()
1637 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl8723be_phy_path_a_rx_iqk()
1640 reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD); in _rtl8723be_phy_path_a_rx_iqk()
1641 reg_ea4 = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_A_2, MASKDWORD); in _rtl8723be_phy_path_a_rx_iqk()
1644 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl8723be_phy_path_a_rx_iqk()
1671 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl8723be_phy_path_b_iqk()
1673 rtl_set_bbreg(hw, 0x948, MASKDWORD, 0x00000280); in _rtl8723be_phy_path_b_iqk()
1681 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00); in _rtl8723be_phy_path_b_iqk()
1682 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); in _rtl8723be_phy_path_b_iqk()
1684 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1c); in _rtl8723be_phy_path_b_iqk()
1685 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c); in _rtl8723be_phy_path_b_iqk()
1686 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl8723be_phy_path_b_iqk()
1687 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl8723be_phy_path_b_iqk()
1689 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x821403ea); in _rtl8723be_phy_path_b_iqk()
1690 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28110000); in _rtl8723be_phy_path_b_iqk()
1691 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82110000); in _rtl8723be_phy_path_b_iqk()
1692 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28110000); in _rtl8723be_phy_path_b_iqk()
1695 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x00462911); in _rtl8723be_phy_path_b_iqk()
1698 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); in _rtl8723be_phy_path_b_iqk()
1701 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000); in _rtl8723be_phy_path_b_iqk()
1702 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); in _rtl8723be_phy_path_b_iqk()
1707 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl8723be_phy_path_b_iqk()
1710 reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD); in _rtl8723be_phy_path_b_iqk()
1711 reg_e94 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, MASKDWORD); in _rtl8723be_phy_path_b_iqk()
1712 reg_e9c = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, MASKDWORD); in _rtl8723be_phy_path_b_iqk()
1744 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl8723be_phy_path_b_rx_iqk()
1746 rtl_set_bbreg(hw, 0x948, MASKDWORD, 0x00000280); in _rtl8723be_phy_path_b_rx_iqk()
1760 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00); in _rtl8723be_phy_path_b_rx_iqk()
1761 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); in _rtl8723be_phy_path_b_rx_iqk()
1764 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1c); in _rtl8723be_phy_path_b_rx_iqk()
1765 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c); in _rtl8723be_phy_path_b_rx_iqk()
1766 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl8723be_phy_path_b_rx_iqk()
1767 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl8723be_phy_path_b_rx_iqk()
1769 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82160ff0); in _rtl8723be_phy_path_b_rx_iqk()
1770 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28110000); in _rtl8723be_phy_path_b_rx_iqk()
1771 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82110000); in _rtl8723be_phy_path_b_rx_iqk()
1772 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28110000); in _rtl8723be_phy_path_b_rx_iqk()
1775 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a911); in _rtl8723be_phy_path_b_rx_iqk()
1777 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); in _rtl8723be_phy_path_b_rx_iqk()
1780 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000); in _rtl8723be_phy_path_b_rx_iqk()
1781 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); in _rtl8723be_phy_path_b_rx_iqk()
1786 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl8723be_phy_path_b_rx_iqk()
1788 reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD); in _rtl8723be_phy_path_b_rx_iqk()
1789 reg_e94 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, MASKDWORD); in _rtl8723be_phy_path_b_rx_iqk()
1790 reg_e9c = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, MASKDWORD); in _rtl8723be_phy_path_b_rx_iqk()
1814 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, u32tmp); in _rtl8723be_phy_path_b_rx_iqk()
1819 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl8723be_phy_path_b_rx_iqk()
1831 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); in _rtl8723be_phy_path_b_rx_iqk()
1834 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c); in _rtl8723be_phy_path_b_rx_iqk()
1835 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x18008c1c); in _rtl8723be_phy_path_b_rx_iqk()
1836 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl8723be_phy_path_b_rx_iqk()
1837 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl8723be_phy_path_b_rx_iqk()
1839 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82110000); in _rtl8723be_phy_path_b_rx_iqk()
1840 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x2816001f); in _rtl8723be_phy_path_b_rx_iqk()
1841 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82110000); in _rtl8723be_phy_path_b_rx_iqk()
1842 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28110000); in _rtl8723be_phy_path_b_rx_iqk()
1845 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a8d1); in _rtl8723be_phy_path_b_rx_iqk()
1847 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); in _rtl8723be_phy_path_b_rx_iqk()
1850 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000); in _rtl8723be_phy_path_b_rx_iqk()
1851 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); in _rtl8723be_phy_path_b_rx_iqk()
1856 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl8723be_phy_path_b_rx_iqk()
1858 reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD); in _rtl8723be_phy_path_b_rx_iqk()
1859 reg_ea4 = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_A_2, MASKDWORD); in _rtl8723be_phy_path_b_rx_iqk()
1895 MASKDWORD) >> 22) & 0x3FF; in _rtl8723be_phy_path_b_fill_iqk_matrix()
2047 path_sel_bb = rtl_get_bbreg(hw, 0x948, MASKDWORD); in _rtl8723be_phy_iq_calibrate()
2053 rtl_set_bbreg(hw, 0xc04, MASKDWORD, 0x03a05600); in _rtl8723be_phy_iq_calibrate()
2054 rtl_set_bbreg(hw, 0xc08, MASKDWORD, 0x000800e4); in _rtl8723be_phy_iq_calibrate()
2055 rtl_set_bbreg(hw, 0x874, MASKDWORD, 0x22204000); in _rtl8723be_phy_iq_calibrate()
2063 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) & in _rtl8723be_phy_iq_calibrate()
2065 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & in _rtl8723be_phy_iq_calibrate()
2079 result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) & in _rtl8723be_phy_iq_calibrate()
2081 result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) & in _rtl8723be_phy_iq_calibrate()
2100 MASKDWORD) & in _rtl8723be_phy_iq_calibrate()
2103 MASKDWORD) & in _rtl8723be_phy_iq_calibrate()
2117 MASKDWORD) & in _rtl8723be_phy_iq_calibrate()
2120 MASKDWORD) & in _rtl8723be_phy_iq_calibrate()
2130 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0); in _rtl8723be_phy_iq_calibrate()
2141 rtl_set_bbreg(hw, 0x948, MASKDWORD, path_sel_bb); in _rtl8723be_phy_iq_calibrate()
2150 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x01008c00); in _rtl8723be_phy_iq_calibrate()
2151 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x01008c00); in _rtl8723be_phy_iq_calibrate()
2237 rtl_set_bbreg(hw, 0x92C, MASKDWORD, 0x1); in _rtl8723be_phy_set_rfpath_switch()
2239 rtl_set_bbreg(hw, 0x92C, MASKDWORD, 0x2); in _rtl8723be_phy_set_rfpath_switch()
2281 path_sel_bb = rtl_get_bbreg(hw, 0x948, MASKDWORD); in rtl8723be_phy_iq_calibrate()
2379 rtl_set_bbreg(hw, 0x948, MASKDWORD, path_sel_bb); in rtl8723be_phy_iq_calibrate()