Lines Matching defs:rtl_phy
1315 struct rtl_phy { struct
1316 struct bb_reg_def phyreg_def[4]; /*Radio A/B/C/D */
1317 struct init_gain initgain_backup;
1318 enum io_type current_io_type;
1320 u8 rf_mode;
1321 u8 rf_type;
1322 u8 current_chan_bw;
1323 u8 set_bwmode_inprogress;
1324 u8 sw_chnl_inprogress;
1325 u8 sw_chnl_stage;
1326 u8 sw_chnl_step;
1327 u8 current_channel;
1328 u8 h2c_box_num;
1329 u8 set_io_inprogress;
1330 u8 lck_inprogress;
1333 s32 reg_e94;
1334 s32 reg_e9c;
1335 s32 reg_ea4;
1336 s32 reg_eac;
1337 s32 reg_eb4;
1338 s32 reg_ebc;
1339 s32 reg_ec4;
1340 s32 reg_ecc;
1341 u8 rfpienable;
1342 u8 reserve_0;
1343 u16 reserve_1;
1344 u32 reg_c04, reg_c08, reg_874;
1345 u32 adda_backup[16];
1346 u32 iqk_mac_backup[IQK_MAC_REG_NUM];
1347 u32 iqk_bb_backup[10];
1348 bool iqk_initialized;
1350 bool rfpath_rx_enable[MAX_RF_PATH];
1351 u8 reg_837;
1353 bool need_iqk;
1354 struct iqk_matrix_regs iqk_matrix[IQK_MATRIX_SETTINGS_NUM];
1356 bool rfpi_enable;
1357 bool iqk_in_progress;
1359 u8 pwrgroup_cnt;
1360 u8 cck_high_power;
1362 u32 mcs_txpwrlevel_origoffset[MAX_PG_GROUP][16];
1364 u32 mcs_offset[MAX_PG_GROUP][16];
1365 u32 tx_power_by_rate_offset[TX_PWR_BY_RATE_NUM_BAND]
1369 u8 txpwr_by_rate_base_24g[TX_PWR_BY_RATE_NUM_RF]
1372 u8 txpwr_by_rate_base_5g[TX_PWR_BY_RATE_NUM_RF]
1375 u8 default_initialgain[4];
1378 u8 cur_cck_txpwridx;
1379 u8 cur_ofdm24g_txpwridx;
1380 u8 cur_bw20_txpwridx;
1381 u8 cur_bw40_txpwridx;
1383 s8 txpwr_limit_2_4g[MAX_REGULATION_NUM]
1388 s8 txpwr_limit_5g[MAX_REGULATION_NUM]
1394 u32 rfreg_chnlval[2];
1395 bool apk_done;
1396 u32 reg_rf3c[2]; /* pathA / pathB */
1398 u32 backup_rf_0x1a;/*92ee*/
1400 u8 framesync;
1401 u32 framesync_c34;
1403 u8 num_total_rfpath;
1404 struct phy_parameters hwparam_tables[MAX_TAB];
1405 u16 rf_pathmap;
1407 u8 hw_rof_enable; /*Enable GPIO[9] as WL RF HW PDn source*/
1408 enum rt_polarity_ctl polarity_ctl;