Lines Matching refs:tx_rings
174 tx_ring = &rtwpci->tx_rings[i]; in rtw_pci_free_trx_ring()
335 tx_ring = &rtwpci->tx_rings[i]; in rtw_pci_init_trx_ring()
357 tx_ring = &rtwpci->tx_rings[i]; in rtw_pci_init_trx_ring()
411 dma = rtwpci->tx_rings[RTW_TX_QUEUE_BCN].r.dma; in rtw_pci_reset_buf_desc()
415 len = rtwpci->tx_rings[RTW_TX_QUEUE_H2C].r.len; in rtw_pci_reset_buf_desc()
416 dma = rtwpci->tx_rings[RTW_TX_QUEUE_H2C].r.dma; in rtw_pci_reset_buf_desc()
417 rtwpci->tx_rings[RTW_TX_QUEUE_H2C].r.rp = 0; in rtw_pci_reset_buf_desc()
418 rtwpci->tx_rings[RTW_TX_QUEUE_H2C].r.wp = 0; in rtw_pci_reset_buf_desc()
423 len = rtwpci->tx_rings[RTW_TX_QUEUE_BK].r.len; in rtw_pci_reset_buf_desc()
424 dma = rtwpci->tx_rings[RTW_TX_QUEUE_BK].r.dma; in rtw_pci_reset_buf_desc()
425 rtwpci->tx_rings[RTW_TX_QUEUE_BK].r.rp = 0; in rtw_pci_reset_buf_desc()
426 rtwpci->tx_rings[RTW_TX_QUEUE_BK].r.wp = 0; in rtw_pci_reset_buf_desc()
430 len = rtwpci->tx_rings[RTW_TX_QUEUE_BE].r.len; in rtw_pci_reset_buf_desc()
431 dma = rtwpci->tx_rings[RTW_TX_QUEUE_BE].r.dma; in rtw_pci_reset_buf_desc()
432 rtwpci->tx_rings[RTW_TX_QUEUE_BE].r.rp = 0; in rtw_pci_reset_buf_desc()
433 rtwpci->tx_rings[RTW_TX_QUEUE_BE].r.wp = 0; in rtw_pci_reset_buf_desc()
437 len = rtwpci->tx_rings[RTW_TX_QUEUE_VO].r.len; in rtw_pci_reset_buf_desc()
438 dma = rtwpci->tx_rings[RTW_TX_QUEUE_VO].r.dma; in rtw_pci_reset_buf_desc()
439 rtwpci->tx_rings[RTW_TX_QUEUE_VO].r.rp = 0; in rtw_pci_reset_buf_desc()
440 rtwpci->tx_rings[RTW_TX_QUEUE_VO].r.wp = 0; in rtw_pci_reset_buf_desc()
444 len = rtwpci->tx_rings[RTW_TX_QUEUE_VI].r.len; in rtw_pci_reset_buf_desc()
445 dma = rtwpci->tx_rings[RTW_TX_QUEUE_VI].r.dma; in rtw_pci_reset_buf_desc()
446 rtwpci->tx_rings[RTW_TX_QUEUE_VI].r.rp = 0; in rtw_pci_reset_buf_desc()
447 rtwpci->tx_rings[RTW_TX_QUEUE_VI].r.wp = 0; in rtw_pci_reset_buf_desc()
451 len = rtwpci->tx_rings[RTW_TX_QUEUE_MGMT].r.len; in rtw_pci_reset_buf_desc()
452 dma = rtwpci->tx_rings[RTW_TX_QUEUE_MGMT].r.dma; in rtw_pci_reset_buf_desc()
453 rtwpci->tx_rings[RTW_TX_QUEUE_MGMT].r.rp = 0; in rtw_pci_reset_buf_desc()
454 rtwpci->tx_rings[RTW_TX_QUEUE_MGMT].r.wp = 0; in rtw_pci_reset_buf_desc()
458 len = rtwpci->tx_rings[RTW_TX_QUEUE_HI0].r.len; in rtw_pci_reset_buf_desc()
459 dma = rtwpci->tx_rings[RTW_TX_QUEUE_HI0].r.dma; in rtw_pci_reset_buf_desc()
460 rtwpci->tx_rings[RTW_TX_QUEUE_HI0].r.rp = 0; in rtw_pci_reset_buf_desc()
461 rtwpci->tx_rings[RTW_TX_QUEUE_HI0].r.wp = 0; in rtw_pci_reset_buf_desc()
550 tx_ring = &rtwpci->tx_rings[queue]; in rtw_pci_dma_release()
626 tx_ring = &rtwpci->tx_rings[queue]; in rtw_pci_deep_ps_enter()
746 struct rtw_pci_tx_ring *ring = &rtwpci->tx_rings[pci_q]; in __pci_flush_queue()
807 ring = &rtwpci->tx_rings[queue]; in rtw_pci_tx_kick_off_queue()
842 ring = &rtwpci->tx_rings[queue]; in rtw_pci_tx_write_data()
955 ring = &rtwpci->tx_rings[queue]; in rtw_pci_tx_write()
979 ring = &rtwpci->tx_rings[hw_queue]; in rtw_pci_tx_isr()