Lines Matching refs:bridge_base_addr
411 void __iomem *bridge_base_addr = in mc_handle_msi() local
417 status = readl_relaxed(bridge_base_addr + ISTATUS_LOCAL); in mc_handle_msi()
419 status = readl_relaxed(bridge_base_addr + ISTATUS_MSI); in mc_handle_msi()
432 void __iomem *bridge_base_addr = in mc_msi_bottom_irq_ack() local
437 writel_relaxed(BIT(bitpos), bridge_base_addr + ISTATUS_MSI); in mc_msi_bottom_irq_ack()
438 status = readl_relaxed(bridge_base_addr + ISTATUS_MSI); in mc_msi_bottom_irq_ack()
441 bridge_base_addr + ISTATUS_LOCAL); in mc_msi_bottom_irq_ack()
475 void __iomem *bridge_base_addr = in mc_irq_msi_domain_alloc() local
493 val = readl_relaxed(bridge_base_addr + IMASK_LOCAL); in mc_irq_msi_domain_alloc()
495 writel_relaxed(val, bridge_base_addr + IMASK_LOCAL); in mc_irq_msi_domain_alloc()
567 void __iomem *bridge_base_addr = in mc_handle_intx() local
573 status = readl_relaxed(bridge_base_addr + ISTATUS_LOCAL); in mc_handle_intx()
589 void __iomem *bridge_base_addr = in mc_ack_intx_irq() local
593 writel_relaxed(mask, bridge_base_addr + ISTATUS_LOCAL); in mc_ack_intx_irq()
599 void __iomem *bridge_base_addr = in mc_mask_intx_irq() local
606 val = readl_relaxed(bridge_base_addr + IMASK_LOCAL); in mc_mask_intx_irq()
608 writel_relaxed(val, bridge_base_addr + IMASK_LOCAL); in mc_mask_intx_irq()
615 void __iomem *bridge_base_addr = in mc_unmask_intx_irq() local
622 val = readl_relaxed(bridge_base_addr + IMASK_LOCAL); in mc_unmask_intx_irq()
624 writel_relaxed(val, bridge_base_addr + IMASK_LOCAL); in mc_unmask_intx_irq()
703 void __iomem *bridge_base_addr = in get_events() local
711 events |= local_events(bridge_base_addr + ISTATUS_LOCAL); in get_events()
921 static void mc_pcie_setup_window(void __iomem *bridge_base_addr, u32 index, in mc_pcie_setup_window() argument
933 writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) + in mc_pcie_setup_window()
938 writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) + in mc_pcie_setup_window()
942 writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) + in mc_pcie_setup_window()
946 writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) + in mc_pcie_setup_window()
950 writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) + in mc_pcie_setup_window()
953 val = readl(bridge_base_addr + ATR0_PCIE_WIN0_SRCADDR_PARAM); in mc_pcie_setup_window()
955 writel(val, bridge_base_addr + ATR0_PCIE_WIN0_SRCADDR_PARAM); in mc_pcie_setup_window()
956 writel(0, bridge_base_addr + ATR0_PCIE_WIN0_SRC_ADDR); in mc_pcie_setup_window()
962 void __iomem *bridge_base_addr = in mc_pcie_setup_windows() local
972 mc_pcie_setup_window(bridge_base_addr, index, in mc_pcie_setup_windows()
987 void __iomem *bridge_base_addr; in mc_platform_init() local
1010 bridge_base_addr = port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; in mc_platform_init()
1064 val = readl_relaxed(bridge_base_addr + IMASK_LOCAL); in mc_platform_init()
1066 writel_relaxed(val, bridge_base_addr + IMASK_LOCAL); in mc_platform_init()
1091 writel_relaxed(0, bridge_base_addr + IMASK_HOST); in mc_platform_init()
1092 writel_relaxed(GENMASK(31, 0), bridge_base_addr + ISTATUS_HOST); in mc_platform_init()
1095 mc_pcie_setup_window(bridge_base_addr, 0, cfg->res.start & 0xffffffff, in mc_platform_init()