Lines Matching refs:pci_dbg
1484 pci_dbg(bridge, "re-enabling LTR\n");
1606 pci_dbg(dev, "saving config space at offset %#x (reading %#x)\n",
1637 pci_dbg(pdev, "restoring config space at offset %#x (was %#x, writing %#x)\n",
2475 pci_dbg(dev, "PME# %s\n", enable ? "enabled" : "disabled");
4352 pci_dbg(dev, "%s bus mastering\n",
4453 pci_dbg(dev, "cache line size of %d is not supported\n",
4482 pci_dbg(dev, "enabling Mem-Wr-Inval\n");
4966 pci_dbg(dev, "waiting %d ms for secondary bus\n", 1000 + delay);
4992 pci_dbg(dev, "waiting %d ms for downstream link\n", delay);
4995 pci_dbg(dev, "waiting %d ms for downstream link, after activation\n",
5005 pci_dbg(child, "waiting additional %d ms to become accessible\n", delay);