Lines Matching refs:dphy
99 struct sun6i_dphy *dphy = phy_get_drvdata(phy); in sun6i_dphy_init() local
101 reset_control_deassert(dphy->reset); in sun6i_dphy_init()
102 clk_prepare_enable(dphy->mod_clk); in sun6i_dphy_init()
103 clk_set_rate_exclusive(dphy->mod_clk, 150000000); in sun6i_dphy_init()
110 struct sun6i_dphy *dphy = phy_get_drvdata(phy); in sun6i_dphy_configure() local
117 memcpy(&dphy->config, opts, sizeof(dphy->config)); in sun6i_dphy_configure()
124 struct sun6i_dphy *dphy = phy_get_drvdata(phy); in sun6i_dphy_power_on() local
125 u8 lanes_mask = GENMASK(dphy->config.lanes - 1, 0); in sun6i_dphy_power_on()
127 regmap_write(dphy->regs, SUN6I_DPHY_TX_CTL_REG, in sun6i_dphy_power_on()
130 regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME0_REG, in sun6i_dphy_power_on()
135 regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME1_REG, in sun6i_dphy_power_on()
141 regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME2_REG, in sun6i_dphy_power_on()
144 regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME3_REG, 0); in sun6i_dphy_power_on()
146 regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME4_REG, in sun6i_dphy_power_on()
150 regmap_write(dphy->regs, SUN6I_DPHY_GCTL_REG, in sun6i_dphy_power_on()
151 SUN6I_DPHY_GCTL_LANE_NUM(dphy->config.lanes) | in sun6i_dphy_power_on()
154 regmap_write(dphy->regs, SUN6I_DPHY_ANA0_REG, in sun6i_dphy_power_on()
161 regmap_write(dphy->regs, SUN6I_DPHY_ANA1_REG, in sun6i_dphy_power_on()
165 regmap_write(dphy->regs, SUN6I_DPHY_ANA4_REG, in sun6i_dphy_power_on()
176 regmap_write(dphy->regs, SUN6I_DPHY_ANA2_REG, in sun6i_dphy_power_on()
180 regmap_write(dphy->regs, SUN6I_DPHY_ANA3_REG, in sun6i_dphy_power_on()
186 regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA3_REG, in sun6i_dphy_power_on()
193 regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA3_REG, in sun6i_dphy_power_on()
198 regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA2_REG, in sun6i_dphy_power_on()
203 regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA1_REG, in sun6i_dphy_power_on()
207 regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA2_REG, in sun6i_dphy_power_on()
216 struct sun6i_dphy *dphy = phy_get_drvdata(phy); in sun6i_dphy_power_off() local
218 regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA1_REG, in sun6i_dphy_power_off()
226 struct sun6i_dphy *dphy = phy_get_drvdata(phy); in sun6i_dphy_exit() local
228 clk_rate_exclusive_put(dphy->mod_clk); in sun6i_dphy_exit()
229 clk_disable_unprepare(dphy->mod_clk); in sun6i_dphy_exit()
230 reset_control_assert(dphy->reset); in sun6i_dphy_exit()
255 struct sun6i_dphy *dphy; in sun6i_dphy_probe() local
258 dphy = devm_kzalloc(&pdev->dev, sizeof(*dphy), GFP_KERNEL); in sun6i_dphy_probe()
259 if (!dphy) in sun6i_dphy_probe()
268 dphy->regs = devm_regmap_init_mmio_clk(&pdev->dev, "bus", in sun6i_dphy_probe()
270 if (IS_ERR(dphy->regs)) { in sun6i_dphy_probe()
272 return PTR_ERR(dphy->regs); in sun6i_dphy_probe()
275 dphy->reset = devm_reset_control_get_shared(&pdev->dev, NULL); in sun6i_dphy_probe()
276 if (IS_ERR(dphy->reset)) { in sun6i_dphy_probe()
278 return PTR_ERR(dphy->reset); in sun6i_dphy_probe()
281 dphy->mod_clk = devm_clk_get(&pdev->dev, "mod"); in sun6i_dphy_probe()
282 if (IS_ERR(dphy->mod_clk)) { in sun6i_dphy_probe()
284 return PTR_ERR(dphy->mod_clk); in sun6i_dphy_probe()
287 dphy->phy = devm_phy_create(&pdev->dev, NULL, &sun6i_dphy_ops); in sun6i_dphy_probe()
288 if (IS_ERR(dphy->phy)) { in sun6i_dphy_probe()
290 return PTR_ERR(dphy->phy); in sun6i_dphy_probe()
293 phy_set_drvdata(dphy->phy, dphy); in sun6i_dphy_probe()