Lines Matching refs:regmap_field_write
298 ret = regmap_field_write(wiz->por_en, 0x1); in wiz_reset()
304 ret = regmap_field_write(wiz->por_en, 0x0); in wiz_reset()
319 ret = regmap_field_write(wiz->p_mac_div_sel0[i], 1); in wiz_p_mac_div_sel()
323 ret = regmap_field_write(wiz->p_mac_div_sel1[i], 2); in wiz_p_mac_div_sel()
347 ret = regmap_field_write(wiz->p_standard_mode[i], mode); in wiz_mode_select()
362 ret = regmap_field_write(wiz->p_align[i], enable); in wiz_init_raw_interface()
366 ret = regmap_field_write(wiz->p_raw_auto_start[i], enable); in wiz_init_raw_interface()
560 regmap_field_write(phy_en_refclk, 1); in wiz_phy_en_refclk_enable()
570 regmap_field_write(phy_en_refclk, 0); in wiz_phy_en_refclk_disable()
636 return regmap_field_write(field, val); in wiz_clk_mux_set_parent()
791 return regmap_field_write(field, val); in wiz_clk_div_set_rate()
932 regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x1); in wiz_clock_init()
934 regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x3); in wiz_clock_init()
946 regmap_field_write(wiz->pma_cmn_refclk_mode, 0x0); in wiz_clock_init()
948 regmap_field_write(wiz->pma_cmn_refclk_mode, 0x2); in wiz_clock_init()
1014 ret = regmap_field_write(wiz->phy_reset_n, false); in wiz_phy_reset_assert()
1018 ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_DISABLE); in wiz_phy_reset_assert()
1028 return regmap_field_write(wiz->p0_fullrt_div[lane], 0x1); in wiz_phy_fullrt_div()
1046 regmap_field_write(wiz->typec_ln10_swap, 1); in wiz_phy_reset_deassert()
1048 regmap_field_write(wiz->typec_ln10_swap, 0); in wiz_phy_reset_deassert()
1052 ret = regmap_field_write(wiz->phy_reset_n, true); in wiz_phy_reset_deassert()
1061 ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE); in wiz_phy_reset_deassert()
1063 ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_FORCE); in wiz_phy_reset_deassert()