Lines Matching refs:g
85 const struct msm_pingroup *g) \
87 return readl(pctrl->regs[g->tile] + g->name##_reg); \
90 const struct msm_pingroup *g) \
92 writel(val, pctrl->regs[g->tile] + g->name##_reg); \
102 const struct msm_pingroup *g) in MSM_ACCESSOR()
104 u32 val = g->intr_ack_high ? BIT(g->intr_status_bit) : 0; in MSM_ACCESSOR()
106 msm_writel_intr_status(val, pctrl, g); in MSM_ACCESSOR()
188 const struct msm_pingroup *g; in msm_pinmux_set_mux() local
193 g = &pctrl->soc->groups[group]; in msm_pinmux_set_mux()
194 mask = GENMASK(g->mux_bit + order_base_2(g->nfuncs) - 1, g->mux_bit); in msm_pinmux_set_mux()
196 for (i = 0; i < g->nfuncs; i++) { in msm_pinmux_set_mux()
197 if (g->funcs[i] == function) in msm_pinmux_set_mux()
201 if (WARN_ON(i == g->nfuncs)) in msm_pinmux_set_mux()
220 val = msm_readl_ctl(pctrl, g); in msm_pinmux_set_mux()
222 val |= i << g->mux_bit; in msm_pinmux_set_mux()
223 msm_writel_ctl(val, pctrl, g); in msm_pinmux_set_mux()
236 msm_ack_intr_status(pctrl, g); in msm_pinmux_set_mux()
249 const struct msm_pingroup *g = &pctrl->soc->groups[offset]; in msm_pinmux_request_gpio() local
252 if (!g->nfuncs) in msm_pinmux_request_gpio()
255 return msm_pinmux_set_mux(pctldev, g->funcs[pctrl->soc->gpio_func], offset); in msm_pinmux_request_gpio()
268 const struct msm_pingroup *g, in msm_config_reg() argument
278 *bit = g->pull_bit; in msm_config_reg()
282 *bit = g->od_bit; in msm_config_reg()
286 *bit = g->drv_bit; in msm_config_reg()
291 *bit = g->oe_bit; in msm_config_reg()
316 const struct msm_pingroup *g; in msm_config_group_get() local
325 g = &pctrl->soc->groups[group]; in msm_config_group_get()
327 ret = msm_config_reg(pctrl, g, param, &mask, &bit); in msm_config_group_get()
331 val = msm_readl_ctl(pctrl, g); in msm_config_group_get()
376 val = msm_readl_io(pctrl, g); in msm_config_group_get()
377 arg = !!(val & BIT(g->in_bit)); in msm_config_group_get()
399 const struct msm_pingroup *g; in msm_config_group_set() local
410 g = &pctrl->soc->groups[group]; in msm_config_group_set()
416 ret = msm_config_reg(pctrl, g, param, &mask, &bit); in msm_config_group_set()
453 val = msm_readl_io(pctrl, g); in msm_config_group_set()
455 val |= BIT(g->out_bit); in msm_config_group_set()
457 val &= ~BIT(g->out_bit); in msm_config_group_set()
458 msm_writel_io(val, pctrl, g); in msm_config_group_set()
481 val = msm_readl_ctl(pctrl, g); in msm_config_group_set()
484 msm_writel_ctl(val, pctrl, g); in msm_config_group_set()
499 const struct msm_pingroup *g; in msm_gpio_direction_input() local
504 g = &pctrl->soc->groups[offset]; in msm_gpio_direction_input()
508 val = msm_readl_ctl(pctrl, g); in msm_gpio_direction_input()
509 val &= ~BIT(g->oe_bit); in msm_gpio_direction_input()
510 msm_writel_ctl(val, pctrl, g); in msm_gpio_direction_input()
519 const struct msm_pingroup *g; in msm_gpio_direction_output() local
524 g = &pctrl->soc->groups[offset]; in msm_gpio_direction_output()
528 val = msm_readl_io(pctrl, g); in msm_gpio_direction_output()
530 val |= BIT(g->out_bit); in msm_gpio_direction_output()
532 val &= ~BIT(g->out_bit); in msm_gpio_direction_output()
533 msm_writel_io(val, pctrl, g); in msm_gpio_direction_output()
535 val = msm_readl_ctl(pctrl, g); in msm_gpio_direction_output()
536 val |= BIT(g->oe_bit); in msm_gpio_direction_output()
537 msm_writel_ctl(val, pctrl, g); in msm_gpio_direction_output()
547 const struct msm_pingroup *g; in msm_gpio_get_direction() local
550 g = &pctrl->soc->groups[offset]; in msm_gpio_get_direction()
552 val = msm_readl_ctl(pctrl, g); in msm_gpio_get_direction()
554 return val & BIT(g->oe_bit) ? GPIO_LINE_DIRECTION_OUT : in msm_gpio_get_direction()
560 const struct msm_pingroup *g; in msm_gpio_get() local
564 g = &pctrl->soc->groups[offset]; in msm_gpio_get()
566 val = msm_readl_io(pctrl, g); in msm_gpio_get()
567 return !!(val & BIT(g->in_bit)); in msm_gpio_get()
572 const struct msm_pingroup *g; in msm_gpio_set() local
577 g = &pctrl->soc->groups[offset]; in msm_gpio_set()
581 val = msm_readl_io(pctrl, g); in msm_gpio_set()
583 val |= BIT(g->out_bit); in msm_gpio_set()
585 val &= ~BIT(g->out_bit); in msm_gpio_set()
586 msm_writel_io(val, pctrl, g); in msm_gpio_set()
600 const struct msm_pingroup *g; in msm_gpio_dbg_show_one() local
625 g = &pctrl->soc->groups[offset]; in msm_gpio_dbg_show_one()
626 ctl_reg = msm_readl_ctl(pctrl, g); in msm_gpio_dbg_show_one()
627 io_reg = msm_readl_io(pctrl, g); in msm_gpio_dbg_show_one()
629 is_out = !!(ctl_reg & BIT(g->oe_bit)); in msm_gpio_dbg_show_one()
630 func = (ctl_reg >> g->mux_bit) & 7; in msm_gpio_dbg_show_one()
631 drive = (ctl_reg >> g->drv_bit) & 7; in msm_gpio_dbg_show_one()
632 pull = (ctl_reg >> g->pull_bit) & 3; in msm_gpio_dbg_show_one()
635 val = !!(io_reg & BIT(g->out_bit)); in msm_gpio_dbg_show_one()
637 val = !!(io_reg & BIT(g->in_bit)); in msm_gpio_dbg_show_one()
639 seq_printf(s, " %-8s: %-3s", g->name, is_out ? "out" : "in"); in msm_gpio_dbg_show_one()
745 const struct msm_pingroup *g, in msm_gpio_update_dual_edge_pos() argument
753 val = msm_readl_io(pctrl, g) & BIT(g->in_bit); in msm_gpio_update_dual_edge_pos()
755 pol = msm_readl_intr_cfg(pctrl, g); in msm_gpio_update_dual_edge_pos()
756 pol ^= BIT(g->intr_polarity_bit); in msm_gpio_update_dual_edge_pos()
757 msm_writel_intr_cfg(pol, pctrl, g); in msm_gpio_update_dual_edge_pos()
759 val2 = msm_readl_io(pctrl, g) & BIT(g->in_bit); in msm_gpio_update_dual_edge_pos()
760 intstat = msm_readl_intr_status(pctrl, g); in msm_gpio_update_dual_edge_pos()
772 const struct msm_pingroup *g; in msm_gpio_irq_mask() local
782 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_mask()
786 val = msm_readl_intr_cfg(pctrl, g); in msm_gpio_irq_mask()
808 val &= ~BIT(g->intr_raw_status_bit); in msm_gpio_irq_mask()
810 val &= ~BIT(g->intr_enable_bit); in msm_gpio_irq_mask()
811 msm_writel_intr_cfg(val, pctrl, g); in msm_gpio_irq_mask()
822 const struct msm_pingroup *g; in msm_gpio_irq_unmask() local
832 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_unmask()
836 val = msm_readl_intr_cfg(pctrl, g); in msm_gpio_irq_unmask()
837 val |= BIT(g->intr_raw_status_bit); in msm_gpio_irq_unmask()
838 val |= BIT(g->intr_enable_bit); in msm_gpio_irq_unmask()
839 msm_writel_intr_cfg(val, pctrl, g); in msm_gpio_irq_unmask()
883 const struct msm_pingroup *g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_update_dual_edge_parent() local
889 val = msm_readl_io(pctrl, g) & BIT(g->in_bit); in msm_gpio_update_dual_edge_parent()
902 val = msm_readl_io(pctrl, g) & BIT(g->in_bit); in msm_gpio_update_dual_edge_parent()
920 const struct msm_pingroup *g; in msm_gpio_irq_ack() local
929 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_ack()
933 msm_ack_intr_status(pctrl, g); in msm_gpio_irq_ack()
936 msm_gpio_update_dual_edge_pos(pctrl, g, d); in msm_gpio_irq_ack()
956 const struct msm_pingroup *g; in msm_gpio_irq_set_type() local
977 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_set_type()
984 if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH) in msm_gpio_irq_set_type()
994 u32 addr = pctrl->phys_base[0] + g->intr_target_reg; in msm_gpio_irq_set_type()
999 val &= ~(7 << g->intr_target_bit); in msm_gpio_irq_set_type()
1000 val |= g->intr_target_kpss_val << g->intr_target_bit; in msm_gpio_irq_set_type()
1008 val = msm_readl_intr_target(pctrl, g); in msm_gpio_irq_set_type()
1009 val &= ~(7 << g->intr_target_bit); in msm_gpio_irq_set_type()
1010 val |= g->intr_target_kpss_val << g->intr_target_bit; in msm_gpio_irq_set_type()
1011 msm_writel_intr_target(val, pctrl, g); in msm_gpio_irq_set_type()
1019 val = msm_readl_intr_cfg(pctrl, g); in msm_gpio_irq_set_type()
1020 was_enabled = val & BIT(g->intr_raw_status_bit); in msm_gpio_irq_set_type()
1021 val |= BIT(g->intr_raw_status_bit); in msm_gpio_irq_set_type()
1022 if (g->intr_detection_width == 2) { in msm_gpio_irq_set_type()
1023 val &= ~(3 << g->intr_detection_bit); in msm_gpio_irq_set_type()
1024 val &= ~(1 << g->intr_polarity_bit); in msm_gpio_irq_set_type()
1027 val |= 1 << g->intr_detection_bit; in msm_gpio_irq_set_type()
1028 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1031 val |= 2 << g->intr_detection_bit; in msm_gpio_irq_set_type()
1032 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1035 val |= 3 << g->intr_detection_bit; in msm_gpio_irq_set_type()
1036 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1041 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1044 } else if (g->intr_detection_width == 1) { in msm_gpio_irq_set_type()
1045 val &= ~(1 << g->intr_detection_bit); in msm_gpio_irq_set_type()
1046 val &= ~(1 << g->intr_polarity_bit); in msm_gpio_irq_set_type()
1049 val |= BIT(g->intr_detection_bit); in msm_gpio_irq_set_type()
1050 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1053 val |= BIT(g->intr_detection_bit); in msm_gpio_irq_set_type()
1056 val |= BIT(g->intr_detection_bit); in msm_gpio_irq_set_type()
1057 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1062 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1068 msm_writel_intr_cfg(val, pctrl, g); in msm_gpio_irq_set_type()
1076 msm_ack_intr_status(pctrl, g); in msm_gpio_irq_set_type()
1079 msm_gpio_update_dual_edge_pos(pctrl, g, d); in msm_gpio_irq_set_type()
1177 const struct msm_pingroup *g; in msm_gpio_irq_handler() local
1191 g = &pctrl->soc->groups[i]; in msm_gpio_irq_handler()
1192 val = msm_readl_intr_status(pctrl, g); in msm_gpio_irq_handler()
1193 if (val & BIT(g->intr_status_bit)) { in msm_gpio_irq_handler()