Lines Matching refs:irqd
303 static inline void s3c64xx_gpio_irq_set_mask(struct irq_data *irqd, bool mask) in s3c64xx_gpio_irq_set_mask() argument
305 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); in s3c64xx_gpio_irq_set_mask()
307 unsigned char index = EINT_OFFS(bank->eint_offset) + irqd->hwirq; in s3c64xx_gpio_irq_set_mask()
319 static void s3c64xx_gpio_irq_unmask(struct irq_data *irqd) in s3c64xx_gpio_irq_unmask() argument
321 s3c64xx_gpio_irq_set_mask(irqd, false); in s3c64xx_gpio_irq_unmask()
324 static void s3c64xx_gpio_irq_mask(struct irq_data *irqd) in s3c64xx_gpio_irq_mask() argument
326 s3c64xx_gpio_irq_set_mask(irqd, true); in s3c64xx_gpio_irq_mask()
329 static void s3c64xx_gpio_irq_ack(struct irq_data *irqd) in s3c64xx_gpio_irq_ack() argument
331 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); in s3c64xx_gpio_irq_ack()
333 unsigned char index = EINT_OFFS(bank->eint_offset) + irqd->hwirq; in s3c64xx_gpio_irq_ack()
339 static int s3c64xx_gpio_irq_set_type(struct irq_data *irqd, unsigned int type) in s3c64xx_gpio_irq_set_type() argument
341 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); in s3c64xx_gpio_irq_set_type()
354 s3c64xx_irq_set_handler(irqd, type); in s3c64xx_gpio_irq_set_type()
358 shift = EINT_OFFS(bank->eint_offset) + irqd->hwirq; in s3c64xx_gpio_irq_set_type()
366 s3c64xx_irq_set_function(d, bank, irqd->hwirq); in s3c64xx_gpio_irq_set_type()
508 static inline void s3c64xx_eint0_irq_set_mask(struct irq_data *irqd, bool mask) in s3c64xx_eint0_irq_set_mask() argument
511 irq_data_get_irq_chip_data(irqd); in s3c64xx_eint0_irq_set_mask()
517 val |= 1 << ddata->eints[irqd->hwirq]; in s3c64xx_eint0_irq_set_mask()
519 val &= ~(1 << ddata->eints[irqd->hwirq]); in s3c64xx_eint0_irq_set_mask()
523 static void s3c64xx_eint0_irq_unmask(struct irq_data *irqd) in s3c64xx_eint0_irq_unmask() argument
525 s3c64xx_eint0_irq_set_mask(irqd, false); in s3c64xx_eint0_irq_unmask()
528 static void s3c64xx_eint0_irq_mask(struct irq_data *irqd) in s3c64xx_eint0_irq_mask() argument
530 s3c64xx_eint0_irq_set_mask(irqd, true); in s3c64xx_eint0_irq_mask()
533 static void s3c64xx_eint0_irq_ack(struct irq_data *irqd) in s3c64xx_eint0_irq_ack() argument
536 irq_data_get_irq_chip_data(irqd); in s3c64xx_eint0_irq_ack()
539 writel(1 << ddata->eints[irqd->hwirq], in s3c64xx_eint0_irq_ack()
543 static int s3c64xx_eint0_irq_set_type(struct irq_data *irqd, unsigned int type) in s3c64xx_eint0_irq_set_type() argument
546 irq_data_get_irq_chip_data(irqd); in s3c64xx_eint0_irq_set_type()
560 s3c64xx_irq_set_handler(irqd, type); in s3c64xx_eint0_irq_set_type()
564 shift = ddata->eints[irqd->hwirq]; in s3c64xx_eint0_irq_set_type()
576 s3c64xx_irq_set_function(d, bank, irqd->hwirq); in s3c64xx_eint0_irq_set_type()