Lines Matching refs:pm8001_cw32
396 pm8001_cw32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW, shiftValue); in pm8001_bar4_shift()
445 pm8001_cw32(pm8001_ha, 2, offset, 0x80001501); in mpi_set_phys_g3_with_ssc()
455 pm8001_cw32(pm8001_ha, 2, offset, 0x80001501); in mpi_set_phys_g3_with_ssc()
473 pm8001_cw32(pm8001_ha, 2, 0xd8, 0x8000C016); in mpi_set_phys_g3_with_ssc()
510 pm8001_cw32(pm8001_ha, 2, offset, value); in mpi_set_open_retry_interval_reg()
520 pm8001_cw32(pm8001_ha, 2, offset, value); in mpi_set_open_retry_interval_reg()
539 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_UPDATE); in mpi_init_check()
696 pm8001_cw32(pm8001_ha, 1, 0x0033c0, 0x1); in pm8001_chip_init()
697 pm8001_cw32(pm8001_ha, 1, 0x0033c4, 0x0); in pm8001_chip_init()
719 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_RESET); in mpi_uninit_check()
782 pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET, in soft_reset_ready_check()
784 pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET, RB6_MAGIC_NUMBER_RST); in soft_reset_ready_check()
841 pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP, 0x0); in pm8001_chip_soft_rst()
852 pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1, 0x0); in pm8001_chip_soft_rst()
857 pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE, 0x0); in pm8001_chip_soft_rst()
862 pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT, regVal); in pm8001_chip_soft_rst()
867 pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE, 0x0); in pm8001_chip_soft_rst()
871 pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT, regVal); in pm8001_chip_soft_rst()
880 pm8001_cw32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_0, signature); in pm8001_chip_soft_rst()
906 pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal); in pm8001_chip_soft_rst()
917 pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, 0x0); in pm8001_chip_soft_rst()
927 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, 0x0); in pm8001_chip_soft_rst()
936 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, 0x0); in pm8001_chip_soft_rst()
955 pm8001_cw32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET, regVal); in pm8001_chip_soft_rst()
969 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal); in pm8001_chip_soft_rst()
976 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal); in pm8001_chip_soft_rst()
987 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal); in pm8001_chip_soft_rst()
1013 pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal); in pm8001_chip_soft_rst()
1023 pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, regVal1); in pm8001_chip_soft_rst()
1028 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, regVal2); in pm8001_chip_soft_rst()
1034 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, regVal3); in pm8001_chip_soft_rst()
1049 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal); in pm8001_chip_soft_rst()
1086 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL); in pm8001_chip_soft_rst()
1087 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL); in pm8001_chip_soft_rst()
1131 pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal); in pm8001_hw_chip_rst()
1139 pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal); in pm8001_hw_chip_rst()
1186 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL); in pm8001_chip_intx_interrupt_enable()
1187 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL); in pm8001_chip_intx_interrupt_enable()
1197 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_MASK_ALL); in pm8001_chip_intx_interrupt_disable()
1215 pm8001_cw32(pm8001_ha, 0, msi_index, MSIX_INTERRUPT_ENABLE); in pm8001_chip_msix_interrupt_enable()
1217 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, value); in pm8001_chip_msix_interrupt_enable()
1233 pm8001_cw32(pm8001_ha, 0, msi_index, MSIX_INTERRUPT_DISABLE); in pm8001_chip_msix_interrupt_disable()
1352 pm8001_cw32(pm8001_ha, circularQ->pi_pci_bar, in pm8001_mpi_build_cmd()
1391 pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar, circularQ->ci_offset, in pm8001_mpi_msg_free_set()
1454 pm8001_cw32(pm8001_ha, in pm8001_mpi_msg_consume()
1467 pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar, in pm8001_mpi_msg_consume()